Multiple Valued Logic

• Currently Studied for Logic Circuits with More

Than 2 Logic States

– Intel Flash Memory – Multiple Floating Gate Charge

Levels – 2,3 bits per Transistor

http://www.ee.pdx.edu/~mperkows/ISMVL/flash.html

• Techniques for Manipulation Applied to Multi-

output Functions

– Characteristic Equation

– Positional Cube Notation (PCN) Extensions

MVI Functions

• Each Input can have Value in Set {0, 1, 2, ..., pi-1}

1:{0,1,..., } {0,1, }iF p X

• MVI Functions

• X is p-valued variable

• literal over X corresponds to subset of values

of S {0, 1, ... , p-1} denoted by XS

MVL Literals

• Each Variable can have Value in Set {0, 1, 2, ..., pi-1}

• X is a p-valued variable

• MVL Literal is Denoted as X{j} Where j is the Logic

Value

• Empty Literal: X{}

• Full Literal has Values S={0, 1, 2, …, p-1}

X{0,1,…,p-1} Equivalent to Don’t Care

MVL Example• MVI Function with 2 Inputs X, Y

– X is binary valued {0, 1}– Y is ternary valued {0, 1, 2}– n=2 pX=2 pY=3

• Function is TRUE if:– X=1 and Y= 0 or 1– Y=2– SOP form is:– F = X{1}Y{0,1} + X{0,1}Y{2}

• Literal X{0,1} is Full, So it is Don’t Care– implicant is X{1} Y{0,1}

– minterm is X {1}Y{0}

– prime implicants are X{1} and Y{2}

0 1

0 1

1 1

2 1 1

X

Y

F

Multi-output Binary Function

• Consider0( , , )f x y z x z x y x z

1( , , )f x y z z x y x

y

z

f0

f1

x y z f0 f1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1

Multi-output Binary Function

• Consider 0( , , )f x y z x z x y x z

1( , , )f x y z z x y

x

y

z

f0

f1

x y z f0 f1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1

x y z W F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1

x

y

z

F

W

Characteristic Equation

Characteristic Equation

{0} {0} {0} {0} {0} {0} {1} {0}

{0} {0} {1} {1} {0} {1} {0} {0}

{0} {1} {0} {1} {0} {1} {1} {1}

{1} {0} {1} {0} {1} {0} {1} {1}

{1} {1} {1} {0} {1} {1} {1} {1}

F x y z W x y z W

x y z W x y z W

x y z W x y z W

x y z W x y z W

x y z W x y z W

Sum of Minterms

x y z W F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1

PCN for MVL Functions

• Binary Variables, {0,1},

Represented by 2-bit Fields

• MV Variables, {0,1,…,p-1}, Represented

by p-bit Fields

• BV Don’t Care is 11

• MV Don’t Care is 111…1

• MV Literal or Cube is Denoted by C()

00

0 10

1 01

* 11

PCN for MVL Example

• Positional Cube Corresponding to X{1} is C(X{1})

{1} {0,1} {0,1} {2}F X Y X Y

 

X Y 01 110 11 001

{1}( ) 01 111C X

• Since Y{0,1,2} is Don’t Care

PCN for MVI-BO Example

• View This as a SOP of MVI Function:

1

2

3

1 2 3( , ); ( , , )

f a b ab

f ab

f ab a b

f a b f f f f

{0} {0} {0} {0} {1} {2} {1} {0} {2} {1} {1} {0,1}F f a b z a b z a b z a b z

• F is the Characteristic Equation

za b f1 f2 f3

a b

10 10 100

a b 10 01 001

a b 01 10 001

a b 01 01 110

List Oriented Manipulation• Size of Literal = Cardinality of Logic Value Set

x{0,2} size = 2

• Size of Implicant (Cube, Product Term) = Integer

Product of Sizes of Literals in Cube

• Size of Binary Minterm = 1 Implicant of Unit Size

EXAMPLE f (x1,x2,x3,x4,x5,x6){1} {1} {0} {0,1} {0,1} {0,1}

1 3 4 1 3 4 2 5 6

2 5 6

1 1 1 2 2 2 01 0110 1111 11 8

# ' 3 ( , , )

implicant x x x x x x x x x

size

Don t Cares x x x

Logic Operations

• Consider Implicants as Sets

– Apply (, , , etc)

• Apply Bitwise Product, Sum, Complement to PCN

Representation

• Bitwise Operations on Positional Cubes May Have

Different Meaning than Corresponding Set Operations

EXAMPLE

Complement of Implicant Complement of Positional Cube

MVL Logical Operations

• AND Operation – MIN - Set Intersection

• OR Operation – MAX - Set Union

• NOT Operation – Set Complement

EXAMPLE{0,1,3} {1,2} {1} {2} {1} {2}

{0,1,3} {1,2} {1} {2,3} {0,1,3} {1,2,3}

{0,1,3} {2,4}5;

X Y X Y X Y

X Y X Y X Y

p X X

MVL Number of Functions of 1 Variable

p pp 2 4 3 27 4 256 5 3125 6 46656 7 823543 8 16777216

MVL Circuits

MIN-gate

MAX-gate

Cube Merging• Basic Operation – OR of Two Cubes

• MVL Operation – MAX is Union of Two Cubes

EXAMPLE

= 1 {0,1} 0 1 = 0 {0,1} 0 1

Merge and into

= {0,1} {0,1}0 1

( )ac d ac d c d a a c d {1} {0,1} {0} {1} {0} {0,1} {0} {1}

{0,1} {0} {1} {1} {0}

{0,1} {0,1} {0} {1}

( )( )

a b c d a b c d

b c d a a

a b c d

Multi-Output Minimization Example

Input Output X1 X2 X3 f0 f1 f2 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 0

X1 X2 X3 X4 F 1 0 0 0 0 0 2 0 0 0 1 1 3 0 0 0 2 1 4 0 0 1 0 0 5 0 0 1 1 0 6 0 0 1 2 1 7 0 1 0 0 0 8 0 1 0 1 0 9 0 1 0 2 0 10 0 1 1 0 0 11 0 1 1 1 0 12 0 1 1 2 1 13 1 0 0 0 0 14 1 0 0 1 0 15 1 0 0 2 0 16 1 0 1 0 1 17 1 0 1 1 1 18 1 0 1 2 0 19 1 1 0 0 1 20 1 1 0 1 0 21 1 1 0 2 0 22 1 1 1 0 1 23 1 1 1 1 0 24 1 1 1 2 0

Minimization Example (cont)

{0} {0} {0} {1} {0} {0} {0} {2}1 2 3 4 1 2 3 4

{0} {0} {1} {2} {0} {1} {1} {2}1 2 3 4 1 2 3 4

{1} {0} {1} {0} {1} {0} {1} {1}1 2 3 4 1 2 3 4

{1} {1} {0} {0} {1} {1} {1} {0}1 2 3 4 1 2 3 4

F X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

Sum of Minterms (Fig. 10.7 PLA Implementation)

Merging• Merge 1st and 2nd

• Merge 3rd and 4th

• Merge 5th and 6th

• Merge 7th and 8th

{0} {0} {0} {1,2} {0} {0,1} {1} {2}1 2 3 4 1 2 3 4

{1} {0} {1} {0,1} {1} {1} {0,1} {0}1 2 3 4 1 2 3 4

F X X X X X X X X

X X X X X X X X

X1 X2 X3 X4 F 1 0 0 0 0 0 2 0 0 0 1 1 3 0 0 0 2 1 4 0 0 1 0 0 5 0 0 1 1 0 6 0 0 1 2 1 7 0 1 0 0 0 8 0 1 0 1 0 9 0 1 0 2 0 10 0 1 1 0 0 11 0 1 1 1 0 12 0 1 1 2 1 13 1 0 0 0 0 14 1 0 0 1 0 15 1 0 0 2 0 16 1 0 1 0 1 17 1 0 1 1 1 18 1 0 1 2 0 19 1 1 0 0 1 20 1 1 0 1 0 21 1 1 0 2 0 22 1 1 1 0 1 23 1 1 1 1 0 24 1 1 1 2 0

Minimization Example (cont){0} {0} {0} {1,2} {0} {0,1} {1} {2}

1 2 3 4 1 2 3 4

{1} {0} {1} {0,1} {1} {1} {0,1} {0}1 2 3 4 1 2 3 4

F X X X X X X X X

X X X X X X X X

0 1 2 3 1 2f X X X X X

1 1 2 3 1 2 3f X X X X X X

2 1 2 3 1 2f X X X X X

Multi-Output Function Using of Multi-Output Prime Implicants (Fig. 10.8 PLA Implementation)