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MUX template

The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in

hardware design. The example below demonstrates a simple two to one MUX, with

inputs A and B, selectorS and output X. Note that there are many other ways to expressthe same MUX in VHDL.

X

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CLK, RESET, LOAD : in std_logic;DATA : in unsigned(WIDTH-1 downto 0);

Q : out unsigned(WIDTH-1 downto 0));end entity counter_example;

architecture counter_example_a of counter_example issignal cnt : unsigned(WIDTH-1 downto 0);

beginprocess(RESET, CLK) isbeginif RESET = '1' then

cnt '0');

elsif rising_edge(CLK) thenif LOAD = '1' thencnt

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wait until rising_edge(CLK);end loop;

for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 everycycle

DATA