mycad design practice -...

MyCAD Design PracticeAmplifier

MyAnalog Station & MyChip Station Pro

T a b l e o f c o n t e n t s

1. INTRODUCTION FOR THE MyCAD ...................................................................................................4

1.1. MyChip Station Pro ............................................................................................................5

(1) LayEd Pro...........................................................................................................................6

(2) MyDRC Pro.........................................................................................................................7

(3) LayNet Pro..........................................................................................................................7

(4) MyLVS Pro ..........................................................................................................................7

(5) CifGDS Pro .........................................................................................................................7

1.2. MyAnalog Station ...............................................................................................................8

(1) Schematic Editor................................................................................................................9

(2) Logic2SPICE ......................................................................................................................9

(3) MySPICE.............................................................................................................................9

(4) MyGPP................................................................................................................................9

2. Practice purpose and example of Tutorial..................................................................................... 10

2.1. Practice purpose of Tutorial............................................................................................ 10

2.2. Practice Environment of MyCAD Tutorial ....................................................................... 11

(1) A design environment file & Environment setting .......................................................... 11

① MyAnalog Station......................................................................................................... 11

② MyChip Station Pro ...................................................................................................... 11

③ Practice environment ................................................................................................... 12

④ Explanation for importance file ..................................................................................... 13

(2) The creation file after designing ..................................................................................... 14

2.3. Two stage amp theory ..................................................................................................... 15

(1) Schematic........................................................................................................................ 15

(2) Current mirror ................................................................................................................. 15

① Summary .................................................................................................................... 15

② Example (current mirror simulation) .............................................................................. 16

(3) Differential amplifier........................................................................................................ 18

① Summary .................................................................................................................... 18

② Example (differential amp simulation) ........................................................................... 20

(4) Common source amplifier............................................................................................... 23

① Summary .................................................................................................................... 23

② Example (common source amplifier simulation) ............................................................ 24

2.4. Two stage amp design .................................................................................................... 27

(1) Two stage amp design .................................................................................................... 27

① Library creation............................................................................................................ 27

② Schematic design ........................................................................................................ 33

③ Schematic verification .................................................................................................. 37

④ Netlist file extraction..................................................................................................... 39

⑤ Simulation ................................................................................................................... 43

(2) Amp Layout design ......................................................................................................... 52

① Project creation ........................................................................................................... 52

② Layout design .............................................................................................................. 57

③ Layout verification........................................................................................................ 64

④ SPICE Simulation [MySPICE (Analog Circuit Simulation)] ............................................. 71

(3) Comparison & analysis for Layout & Schematic ............................................................ 78

① Netlist comparison [MyLVS (Hierarchical Layout Versus Schematic Netlist Comparator)] 78

② Discrepancy file confirmation........................................................................................ 83

③ Comparison for Layout Spice Simulation and Schematic Spice Simulation ..................... 85

(4) Layout data transformation............................................................................................. 86

① CifGDS Pro ................................................................................................................. 86

APPENDIX ............................................................................................................................................. 88

A Technology File ...................................................................................................................... 88

A.1. SCMOS_SCN4ME_SUBM.TEC ...................................................................................... 88

A.2. STIPPLE.LST ................................................................................................................. 99

B Verification File..................................................................................................................... 100

B.1. SCMOS_SCN4ME_SUBM_DRC.rul .............................................................................. 100

B.2. SCMOS_SCN4ME_SUBM_ERC.rul .............................................................................. 106

B.3. SCMOS_SCN4ME_SUBM_ERC(nwell).rul .................................................................... 110

C Spice File .............................................................................................................................. 114

C.1. include.inc ( parameter)................................................................................................. 114

C.2. Layout Two stage amp(addition) .................................................................................... 116

1. INTRODUCTION FOR THE MyCAD MyCAD is program for the electronic circuit design and simulation, and supply for domestic and abroad

market is well advanced based on own development.

MyCAD is EDA(Electronic Design Automation) Tool which is composed of MyChip Station Pro, MyAnalog

Station, MyLogic Station, MyVHDL Station in general.

MyChip Station Pro and MyAnalog Station of MyCAD is tool for circuit design, Netlist extraction, Layout and

inspection, and can be translated to the final GDS file.

MyLogic Station is Tool for front-end design and supports schematic capture, function simulation and

EDIF generation. And also, MyCAD is optimized EDA tool to be accomplished all works like as VHDL design,

logical composition and optimization, digital logic circuit design on the PC Windows.

< Figure 1.1 MyCAD IC Design Flow >

1.1. MyChip Station Pro

MyChip StationTM Pro is IC Design Solution which is possible to do exquisite physical design like as

workstation. LayEd Pro for Layout design is Full custom IC layout editor based on Customizable Polygon.

Physical design verification is made of MyDRC Pro to inspect for Design rule, MyLVS Pro to compare the

Netlist of Layout and Schematic, and LayNet Pro to extract Parasitic information and Netlist.

This Verification Tool can use rule file which is defined by users, and compatible also with DRACULATM.

Lastly, CifGDS Pro is possible to Import, Export the Layout data with standardized file(GDS II, CIF, DXF).

A related department with electric, electronic, telecommunication and semiconductor in a lot of university in

the country are now educating for design with the MyCAD, and it also be used for Layout design in related

fields like as IC layout, MEMS Design, LCD and Optical in the industry.

In case of outside the country, it has been using for design of Analog and Mixed IC by brilliant specialists in

U.S.A., Japan, Europe, China and Asia for several years, and superior capacity is demonstrated by them.

< Figure 1.2 MyChip Station Pro Flow >

(1) LayEd Pro

LayEd Pro is editor and using the Graphical User Interface which is based on powerful and

sophisticated Polygon. And also it can be used by not only beginner but also expert because easy

and convenient functions like as fast processing capacity and automatic recovery function against

unanticipated system error..

< Figure 1.3 Design of BFILTER using the LayEd Pro >

(2) MyDRC Pro

This is Tool for verification whether it is designed correctly after designing of Layout, and display a part

of disagreed with rule through the Hierarchical Design Rule Inspection. It is possible to rule check by

real time with Real Time DRC. And this is compatible with DRACULATM and possible also to check a

large capacity data at high speed.

(3) LayNet Pro

This is tool to extract a Netlist from Layout, and possible to Hierarchical ERC rule Check. And also, this

can extract a Netlist which is suitable for SPICE and HSPICE format, and compatible with DRACULATM.

(4) MyLVS Pro

This is tool to do comparative analysis of Hierarchical Layout Netlist and Schematic Netlist, and support

various SPICE Netlist format (standard, SPICE, HSPICE, PSPICE).

(5) CifGDS Pro

This is tool to convert into import and export in various forms from Layout data using the Industry

standard (GDSII, CIF, DXF), and convert Data among the industry standard. And also, this is done to

convert Layer or Cell by user’s option.

1.2. MyAnalog Station

MyAnalog Station is tool for electronic circuit design and mock experimentation. This converts an inside

course automatically in which convert a designed Data by Schematic editor into SPICE-Netlist, and make an

experiment with selected and wanted Analysis from MySPICE after add a line in need into created SPICE-

Netlist.

A result of mock experimentation will be changed into more easily to analyzing and nice report if the Post

Processor (MyGPP) is used for it.

< Figure 1.4 MyAnalog Station Flow >

(1) Schematic Editor

This is possible to design easily a Schematic with provided Analog Library, and possible also to use

with symbol from Symbol Editor. And this also display a disobeyed Error for rule after verifies a

designed circuit which is considered for electric specific with ERC rule.

(2) Logic2SPICE

This is possible to extract a various kinds of SPICE Netlist (Standard SPICE, HSPICE, PSPICE)

(3) MySPICE

MySPICE is analog simulator which is possible to analyze a DC operating point calculation, transient

current, performs Fourier, noise and distorted wave of complicated circuit.

This is provide Berkeley SPICE model basically and GUI which is based on MS Window. And also, this

is providing the new model (BSIM, BSIM2, BSIM3 Losy Trasmission Lines, MOS Level 6)

(4) MyGPP

MyGPP is provide the Function of FFT(Fast Fourier Transform) and Cursor like as the sum and balance,

differential, integral calculus in order to be more easy for analysis of MySPICE.

※ Platform

- CPU : Min. Pentium2 / Pentium-4 (encouragement)

- RAM : Min. 128MB / 512MB (encouragement)

- HDD : Min. 50MB / surplus space of 2GB(encouragement)

- OS : Min. Windows 95 / Windows2000 or XP (encouragement)

2. Practice purpose and example of Tutorial

2.1. Practice purpose of Tutorial

This Tutorial makes a design for Inverter, NAND Gate, Schematic of MUX and Layout, and come to

analyze with mock experimentation.

In the next process, this compares a design of Schematic and Layout, and verify for matching as designed.

Purpose of this is to helping a general understanding for IC design with execution and generation from

Schematic to Layout, GDSII file..

2.2. Practice Environment of MyCAD Tutorial

(1) A design environment file & Environment setting ① MyAnalog Station

i. Library File : This is provided from Analog.lib in C:\MyCADPro\Library\MyAnalog folder, and

provide also all of Cell to need in practice.

ii. Include File : This is provide the SCN4M_SUMB SPICE BSIM3.txt file from the

C:\MyCADPro\Demo\IDS\MyCell\BSIM3 Model folder, and provide also standard

model of NMOS and PMOS in Spice Simulation (Property of MOS have to be same

when MOS model and Spice Netlist are extracted).

② MyChip Station Pro

i. SCMOS_SCN4ME_SUBM.TEC : This is provided from C:\MyCADPro\Demo\IDS\MyCell

\Layout, and has information for layer and display.

ii. Stipple.lst : This is provided from C:\MyCADPro\Demo\IDS\MyCell\Layout, and defined file

for pattern form of fill in the layer.

iii. SCMOS_SCN4ME_SUBM_DRC.rul :

This is provided from C:\MyCADPro\Demo\IDS\MyCell\Layout\Layout\Verification

Rule, and file for verification of design rule as file for execution of MyDRC Pro

iv. SCMOS_SCN4ME_SUBM_ERC.rul :

This is provided from C:\MyCADPro\Demo\IDS\MyCell\Layout\Layout Verification

Rule, and regulation file for extraction of electric element when Netlist is extracted

v. Include File :

SCN4M_SUMB_SPICE _BSIM3.txt file is provided from C:\MyCADPro\Demo\IDS

\MyCell\BSIM3 Model folder, and standard models of NMOS and PMOS are also

provided in Spice Simulation.

Files of SCMOS_SCN4ME_SUBM are regulation of design which is manufactured by MOSIS

company for VLSI circuit. Size of transistor is (W/L)p = (2.4/0.4)㎛, (W/L)n = (1.2/0.4)㎛.

③ Practice environment

※ First of all, create the Layout folder, Schematic folder like as <Figure2.2.(1)-1> for convenience of

design before practice. Position of files which are putted in subordinate folder is described in page

11

< Figure 2.2.(1)-1 Creation of folder and assignment of file position for practice. >

- MyChip Station Pro 2005\Layout folder creation

• SPICE folder: SCN4M_SUMB SPICE BSIM3.txt

• Tecfile folder: SCMOS_SCN4ME_SUBM.TEC, STIPPLE.LST

SCMOS_SCN4ME_SUBM_DRC.rul,

SCMOS_SCN4ME_SUBM_ERC.rul

SCMOS_SCN4ME_SUBM_ERC(nwell).rul (APPENDIX B.3 reference)

- MyAnalog V63\Schematic folder creation

• Library folder: C:\MyAnalogV63\Library\MyAnalog folder copy for all

• SPICE folder: SCN4M_SUMB SPICE BSIM3.txt

④ Explanation for importance file

Extention name

Contents

*.TEC This is technology file for using in MyChip Station. Users can change and use

this file with process as wish.

*.LST This file has pattern information of layer fill for library work and changeable by

users.

DRC.rul File for standard in search of design error. Rule check is progressed in this file

basis when MyDRC Pro is executed.

*.rul

ERC.rul

This has devices and net information which are needed in electrical error

searching and Netlist extraction. Rule check is progressed in this file basis

when MyDRC Pro is used.

*.cir, *.spc These are result files in Netlist extraction of SPICE form, and have connection

information of circuit.

*.dis

This file has information for comparison and analysis result of Layout and

Schematic after execution of MyLVSPro, and possible to check a contents of

Discrepancy.

*.inc This file has model parameter to using in SPICE Simulation. There are

provided the TSMC 0.35 um processing model parameter in MyCAD Tutorial.

(2) The creation file after designing

When do Schematic design and Layout design, many kinds of files are created. The files function

as like this (as below)

section Extention

name Contents

schematic This is made in inv folder when creating the Schematic.

symbol This is made in inv folder when creating the Symbol.

netlist This file has information for extraction.

*.mdc executing file for Schematic.

*.lib This is information file which is created if you save it after design.

MyAnalog

Station

*.log This file has message which is occurred on simulation.

layout.1 This is layout data which is made in cell.

drc_bin.1 This file has an error of practice result, and provides graphic

information.

drc.1 This has an error of practice result, and provides a XY coordinates

of positions which are occurred an error by text file.

extract.1 This is file for practice result, and has information for element and

connecting condition in layout.

devshape.1

This is made from practice result, and provides information which

can search an element as wish on layout through Find Device

order in LayEd Pro.

netshape.1 This is file for practice result, and has information for an element

connecting net.

erc_bin.1 This file has a practice result of ERC.

MyChip

Station Pro

lvs_bin.1 This is information for error which is not corresponding with

Schematic and Layout as practice result of LVS.

2.3. Two stage amp theory (1) Schematic

Current mirror CS amplifier

Differential amp

<Figure 2.3.(1)-1 Schematic of the two stage amp>

(2) Current mirror

① Summary We study movement characteristic of basic current mirror circuit as follows

< Figure 2.3.(2)-1 Basic current mirror schematic > figure 2.3(2)-1 is basic current mirror.

An electric current on M1,M2 can calculate using below a formula.

M2 M1

R ID1 ID2=Io

+

Vo

-1

1

LW

2

2

LW

VSS

21

11 )(

2 THNGSD VVI −⋅=β

(2.1)

22

22 )(

2 THNGSD VVI −⋅=β

(2.2)

If calculating the ratio of drain electric current since VGS1=VGS2

1

2

21

12

1

1

2

2

1

2

ββ

===LWLW

LWLW

II

D

D (2.3)

electric current ID1 on figure 2.3.(2)-1 can calculate as follows

21

1

11 )(

2 THNGSGS

D VVLWKP

RVSSVVDDI −⋅

⋅=

−−= (2.4)

Output resistance power of current source is output resistance power of M2.

2

211

Doo II

rλλ

== (2.5)

② Example (current mirror simulation)

i. Design for source of electricity

< Figure 2.3.(2)-2 Schematic of current mirror >

design to be 10uA on current reference circuit

Current

reference

I0 L=5um, W=50um, *M=1

I1 L=5um, W=50um, *M=2

I2 L=5um, W=50um, *M=3

*M (multiplier) : multiply the size of ‘W’ as like ‘M’s constant.

ex) L = 5um, W = 5um, M = 3 L = 5um, W=5umⅹ3 = 15um

VGS of MOS I0

22 )(2

)(2 THNGSTHNGSD VV

LWKPnVVI −⋅⋅=−⋅=

β

][702.0502.050/5051022

2

VumVuAumuAV

WKPLI

V THNn

DGS =+

⋅××

=+⋅⋅

=

If determine R of resistance value

][260][8.25910

0702.03.3Ω≈Ω=

−−=

−−= kk

uAV

IVSSVVDD

RD

GS

ii. Extracted Netlist from Current mirror schematic

< Figure 2.3.(2)-3 Extracted netlist >

Addition part of red color

iii. Simulation result

<Figure 2.3.(2)-4 Movement characteristic of current mirror >

(3) Differential amplifier ① Summary

< Figure 2.3.(3)-1 Differential amp >

Source of electric current of M1,M2 that AC component and DC component are combined as

follows.

21 DDSS iiI += (3.1)

Input voltage of M1,M2 gate is

+

vI1

-

+

vI2

-

VSS

Iss

M2 M1

iD2=ID2+id2ID1+id1=iD1

221121 gsGSgsGSIIDI vVvVvvv −−+=−= (3.2)

(VGS1, VGS2 DC component of voltage, vgs1, vgs2 AC component of voltage)

The size of differential input voltage can show as below formula.

221 )(

2 DDDI iiv −=β

(3.3)

The size for tolerable maximum input voltage is as below When input of differential amplifier

β

SSDIMAX

Iv 2= (3.4)

β

SSDIMIN

Iv 2−= (3.5)

When input of differential amplifier, The size of tolerable maximum input voltage

+

vI

-

VSS

Iss

M4 M3

M2 M1

<Figure 2.3.(3)-2 Differential amplifier for making a decision range of common mode input >

VSSIVIv SSTHN

SSIMIN +++=

61

2ββ

(3.6)

THNTHPSS

IMAX VVIVDDv +⎥⎦

⎤⎢⎣

⎡+−=

3β (3.7)

<Figure 2.3.(3)-3 Differential amplifier at AC mode >

voltage benefit of differential amplifier is as follows.

+

vI1

-

+

vout

-

M4 M3

M2 M1

)||( 42211

oomii

out

i

outv rrg

vvv

vvA =

−== (3.8)

② Example (differential amp simulation) i. Design for differential amplifier

<Figure 2.3.(3)-4 schematic of differential amplifier >

ii. Extracted Netlist from schematic of differential amplifier

<Figure 2.3.(3)-5 Extracted Netlist >

Above simulation added the part of red color for seeing DC characteristic of differential

amplifier ( increase DC voltage of differential input from -0.02V to +0.02V )

iii. Simulation result a. Output wave at the point of DC input

(Change DC input voltage from 0.02V to 0.02V)

<Figure 2.3.(3)-6 DC Characteristic of differential amplifier >

b. Output wave at the point of AC input

(increase frequency of AC 1V input voltage by 10Hz within range from 10HZ to 100Mhz)

< Figure 2.3.(3)-7 Characteristic of voltage benefit by frequency >

c. Phase at the point of AC input

(increase frequency of input voltage AC 1V by 10Hz within range from 10 Hz to 100Mhz)

< Figure 2.3.(3)-8 phase characteristic by frequency >

(4) Common source amplifier ① Summary

<Figure 2.4.(4)-1 Common source amplifier>

Small signal voltage benefit of the left common source amplifier is as follows.

2

1

1

2

1

2

source in the resistancedrain in the resistance

1

1

1

1

m

m

m

m

md

md

in

out

gg

g

g

gi

gi

vv

−=−=−=⋅

⋅= (4.1)

<Figure 2.4.(4)-2 common source amplifier which have current source load >

Current source load provide the largest resistance in the process of CMOS.

Figure 2.4.(4)-1 is common source amplifier which have current source load. M1 is part of common

source at amplifier, M2 is current source load.

VDD

VSS

M1

M2vin

vout

VDD

VSS

M1

M2

vin

vout

id

VDD

VSS

M1

M2

vi

vout

Id=gm1vi

10uA

Calculating the voltage benefit for common source

21

1

1

21

1||

oo

m

m

oo

i

ov gg

g

g

rrvvA

+−=−== ⎟⎟

⎠

⎞

⎝

⎛=

Do I

rλ

1Θ⎜⎜ (4.2)

② Example (common source amplifier simulation)

i. Design for Common source amplifier

<Figure 2.4.(4)-3 Schematic of common source amplifier >

ii. Extracted Netlist from schematic of Common source amplifier

< Figure 2.4.(4)-4 extracted netlist >

iii. Simulation result

a. Output wave at the point of DC input

(Increase DC input voltage from 0v to 3.3V)

< Figure 2.4.(4)-5 DC characteristic of common source amplifier >

b. Output type at the point of AC input

(increase frequency for AC 1V input voltage by 10 Hz within range from 10Hz to 100 Mhz)

< Figure 2.4.(4)-6 Characteristic of voltage benefit by frequency >

c. Output wave at the point of AC input

(Increase frequency of AC 1V input voltage by 10Hz within range from 10Hz to 100Mhz)

< Figure 2.4.(4)-7 Phase characteristic by frequency >

2.4. Two stage amp design (1) Two stage amp design

MyCAD Pro execute Schematic Editor for MyAnalog

<Figure 2.3(1)-1 Schematic Editor>

① Library creation

i. New Folder

Menu file after opening new design option, make new work folder at the column of

C:\MyAnalogV63\Schematic\

<Figure 2.3(1)-2 New Design Context>

ii. New Library file

After making New Library file: Work Folder, make file name as amp. Making MDC file

(MyCAD Design Context), Library file is created automatically. The name of extension is

created automatically even though you omit it.

< Figure 2.3(1)-3 Make practice file >

After saving, pressing enter key at “ do you want to make new library ?’ , Library file is

created.

< Figure 2.3(1)-4 Library creation >

iii. New Cell & View

Menu file after selecting at cell/view making, write as “amp” at cell/view creation

window and select schematic under the name of view.

< Figure 2.3(1)-5 Cell creation > < Figure 2.3(1)-6 make cell >

When pressing enter key at the window of cell/view creation, Schematic window is show up.

<Figure 2.3(1)-7 Cell creation >

iv. Add Library

Use symbol with loading which was made to simplify the design.

Menu file if you press enter key add /delete library, window for Add Library is show up.

Choice the Analog at window Reserved Library and press the right arrow in the middle

< Figure 2.3(1)-8 Library add > < Figure 2.3(1)-9 Library add >

When pressing the enter key at Add Library window, Analog Library is added.

< Figure 2.3(1)-10 Added Library >

If there doesn’t exist Analog at Reserved Library, After pressing “add “of User Library, select

C:\MyAnalogV63 \Library\MyAnalog\Analog.lib and then press “open”.

< Figure 2.3(1)-11 Analog Library addition >

< Figure 2.3(1)-12 Analog Library file>

When pressing the enter key at Add Library window, Analog Library is added

< Figure 2.3(1)-13 Analog Library addition >

② Schematic design

i. Symbol composition

Drag the Symbols (NMOS, PMOS, CAP, VDD, GND, RES) which need amp design from

Analog Library and put at the Schematic window.

< Figure 2.3(1)-14 Symbol loading >

Drag all required symbols and then arrange the site for making Two stage amp. Drag Input

and output port from object bar.

< Figure 2.3(1)-15 Symbol loading >

ii. Wire connection

After double click at net point of Symbol and then connect to net point of other with dragging.

< Figure 2.3(1)-16 Connect the Symbol >

Connect each symbol and complete Inverter circuit.

< Figure 2.3(1)-17 Completed Schematic >

iii. Symbol property setting

Property empty at provided symbol. To simulation, you should fix intermediation variable

value. When double click in the middle of system of PMOS, instance window is show up.

< Figure 2.3(1)-18 Property setting of Symbol >

Select property menu


And when double click ‘L =’, property correction window is show up


Insert 0.4u as value and press enter key.

Insert all value for each symbol like this way.

When work is completed, save.

③ Schematic verification

i. ERC (Electric Design Rule Check)

Menu tool after selecting entering circuit verification, press all error confirmation at

error menu of circuit verification window and select all warning confirmation at warning menu

and press search starting key

< Figure 2.3(1)-21 Circuit verification >

ii. Error & Warning

If there happen problem on circuit, error message is show up.

< Figure 2.3(1)-22 Circuit verification result >

Correct according to error message.

④ Netlist file extraction

Menu tools select “SPICE Netlist Translator”

i. New folder

< Figure 2.3(1)-23 Netlist extraction >

< Figure 2.3(1)-24 Netlist extraction >

Select the browse at the right of result file on logic 2 SPICE window.

Make output folder at C:\MyAnalogV63\Schematic.

< Figure 2.3(1)-25 Output folder creation >

ii. New File

Make file name as amp at output folder and save.

< Figure 2.3(1)-26 Netlist file creation >

iii. Include file inclusion

Include to include file which is on SCN4M_SUMB SPICE BSIM3.txt file of Logic2SPICE

window on C:\MyAnalogV63\Schematic\spice file Logic2SPICE.

< Figure 2.3(1)-27 Include file inclusion >

When pressing RUN on Logic2SPICE window, Netlist is created. ( amp.cir file is created to

output folder.)

< Figure 2.3(1)-28 Netlist creation completion >

You can see the extracted Netlist as memorandum when pressing View on Logic2SPICE

window

< Figure 2.3(1)-29 Extracted Netlist >

iv. Option

when pressing Option of Logic2SPICE window, you can fix the kind of Netlist format (Spice3,

HSpice, PSpice), and you can classify Structure (flat, Hierarchical).

< Figure 2.3(1)-30 Option for Netlist format>

⑤ Simulation

i. MySPICE

MyCAD Pro Execute the MySPICE.

< Figure 2.3(1)-31 MySpice execution >

ii. Menu File after selecting “Open”, select amp.cir file on C:\MyAnalogV63\Schematic

\output and press the “Open”.

< Figure 2.3(1)-32 Amp.cir file open >

< Figure 2.3(1)-33 Amp.cir>

iii. Input the part of red color to extracted Netlist file directly. This is to assign value for

simulation.

< Figure 2.3(1)-34 Added content from amp.cir >

iv. Menu Analysis select “Run Standard Spice file”. If there is Error on Netlist, Run

Standard Spice file cannot be activated.

< Figure 2.3(1)-35 Selection plot which will output >

Select wanted result on Select Variables To Plot window. Select the V[vout][voltage] and also

select Phase on AC Option and then press OK.

v. Menu Analysis select “Run Standard Spice file”

< Figure 2.3(1)-36 Selection plot which will output >

vi. Select the result which is wanted on Select Variables To Plot screen(window) as like iv.

Select V[vout][voltage]. Also select 'Phase' on AC Option, then press 'OK'.

< Figure 2.3(1)-37 Simulation operating result >

Two windows are show up as above

vii. select Menu Control Start Simulation from above figure

Confirm the status on “Simulation Statistics” window and then press OK.

< Figure 2.3(1)-38 Simulation result window >

viii. Result confirmation (Both Cc & Rz Stable)

a. Magnitude [dB]

< Figure 2.3(1)-39 Output wave >

b. Phase [deg]


ix. Result confirmation (only Cc unstable)

a. Schematic

< Figure 2.3(1)-41 Circuit which Rz is removed >

b. Netlist

Input part of red color Netlist.


c. Magnitude [dB]


d. Phase [deg]


x. Result confirmation without Cc & Rz

a. Schematic

< Figure 2.3(1)-45 Cc, circuit which Rz is removed >

b. Netlist

Input directly the part of red color Netlist.


c. Magnitude [dB]


d. Phase [deg]


(2) Amp Layout design Execute LayEd Pro (Layout Editor) of MyChip Station Pro 2005.

< Figure 2.3(2)-1 LayEd Pro execution >

① Project creation

i. New Folder

New Folder: Menu Project Select “New Project”.

< Figure 2.3(2)-2 Project creation >

Select Browse of Project Path on New Project window and make work folder on C:\MyChip

Station Pro 2005\Layout에 work Folder.

< Figure 2.3(2)-3 Work directory creation >

ii. New Project & Technology File change

Write “amp” as file name to Work Folder and press open. The name of extension (*.prj ) is

created automatically.

< Figure 2.3(2)-4 Project creation >

Select again Browse of Technology Path on New Project window

< Figure 2.3(2)-5 New project creation >

Select C:\MyChip Station Pro2005\Layout\tecfile\SCMOS_SCN4ME_SUBM.TEC and press

open. It’s o.k. to use for User with edition from Default.tec file

< Figure 2.3(2)-6 Loading for TEC file >

Press OK when input is completed on New Project as below.

< Figure 2.3(2)-7 Loading for TEC file>

It is created amp Project on Project window of LayEd Pro window, you can see the created

Layer on Layer window.

< Figure 2.3(2)-8 Created project and Layer >

iii. New Cell

Menu Cell After selecting New Cell, write ”Inv “ under Cell Name on New Cell window

and then press OK.

< Figure 2.3.(2)-9 Cell addition >

< Figure 2.3.(2)-10 Added Cell >

Figure 2.3.(2)-10 if you complete screen, finish preparation for Layout plan. Before you start

designing, check what setting is fixed (interval space on Layout window) from menu

option Grid on Project option.

② Layout design

Design for amp layout with seeing Schematic circuit. All figures should be drawed in accordance

with design regulation. It refer size & interval for provided figure. There are not only way to

design which use command language on Command window but also way to design with drawing

directly. (if you use command language, you can also design with loading Macro or VBS)

Menu View Ruler measuring the length with selecting Draw Ruler with.

i. Nwell drawing

After making a choice nwell of Layer Panel, draw as figure 2.3.(2)-11 with selection for

Rectangle of Toolbar.

< Figure 2.3.(2)-11 N-well drawing >

ii. Active drawing

After selecting active of Layer Panel, draw as figure 2.3.(2)-11 with selection for Rectangle of

Toolbar.

< Figure 2.3.(2)-12 Active drawing >

iii. Poly drawing

After making a choice poly of Layer Panel, draw as figure 2.3.(2)-13 with selection for

Rectangle of Toolbar.

< Figure 2.3.(2)-13 Poly drawing >

iv. Npuls, Ppuls drawing

After making a choice Npuls, Ppuls of Layer Panel, draw as figure 2.3.(2)-14 with selection

for Rectangle of Toolbar.

< Figure 2.3.(2)-14 Nplus, Pplus drawing >

v. Contact drawing

After making a choice contact of Layer Panel, draw as figure 2.3.(2)-15 and figure 2.3.(2)-16

with selection for Rectangle of Toolbar.

< Figure 2.3.(2)-15 Contact drawing >

< Figure 2.3.(2)-16 Via drawing >

vi. Metal drawing

After making a choice Metal1of Layer Panel, draw as figure 2.3.(2)-17 with selection for

Rectangle of Tool. Metal2 is same as.

< Figure 2.3.(2)-17 Metal drawing >

vii. Metal text drawing

Metal text After making a choice Me1txt of drawing: Layer Panel, After making a Label under

indicating “Á” of Toolbar, Write “IN” on the Label window and fix the site of text with

pressing scroll arrow of Justification

< Figure 2.3.(2)-18 Metal Label addition >

Make VIN, VIP, Vbias, vou, out, Vis, Vout, VDD, VSS same as figure 2.3.(2)-19.

< Figure 2.3.(2)-19 completed Layout >

After completion, Design for Layout is completed when you save.

③ Layout verification

i. DRC (Design Rule Check) - MyDRC Pro

Menu Verification Select DRC. Open right Rule Browse of MyDRC Pro window and

select SCMOS_SCN4ME_SUBM_DRC.rul on C:\MyChip Station Pro 2005\Layout\tecfile

< Figure 2.3.(2)-20 DRC check>

Press Run when DRC.rul file is added on Rule of MyDRC Pro window same as figure

2.3.(2)-21.

< Figure 2.3.(2)-21 DRC check>

Figure 2.3.(2)-21 press Close when screen is show up. So, Verification Errors window is

show up.

< Figure 2.3.(2)-22 Verification>

If you find Error, double click error and you should edit them in accordance with design

regulation as the screen is moved to place which error was happened.



ii. Extract & ERC (Spice Netlist Extract & Electric Rule Check) - LayNet Pro

Menu Verification select Extract & ERC.

After Browse of Rule right on LayNet Pro window, input C:\MyChip Station Pro

2005\Layout\tecfile\SCMOS_SCN4ME_SUBM_ERC(nwell).rul

< Figure 2.3.(2)-25 ERC check>

After pressing right Browse of Output on LayNet Pro window, make output folder on

C:\MyChip Station Pro 2005\Layout\ and write “amp.cir” as file name at output folder and

press save.

< Figure 2.3.(2)-26 Output file save >

Change extension of output path to amp.cir and after making a choice “Generate net and

device shapes, Passive device model name” and press “Run”.

< Figure 2.3(2)-27 Option set up >

< Figure 2.3.(2)-28 LayNetPro execution >

When pressing Close, Verification Errors window is show up.


If you find Error, double click error and you should edit them in accordance with design

regulation as the screen is moved to place which error was happened


iii. Real Time DRC

Menu Verification Real Time DRC execute Rule File Load with selection. Verification

File can use Real Time DRC.rul file or use SCMOS_SCN4ME_SUBM_DRC.rul. Real Time

DRC means that it correct error of Layout happened in order of precedence.

< Figure 2.3.(2)-31 Real time DRC>

④ SPICE Simulation [MySPICE (Analog Circuit Simulation)]

MyCAD Pro Execute MySPICE with selection.

< Figure 2.3(2)-32 MySpice execution >

i. Open File

Menu File after making a choice Open, after selection amp.cir of C:\MyChip Station Pro

2005\Layout\output window at open window and press open.

< Figure 2.3.(2)-33 Extracted Netlist from Layout >

ii. SCN4M_SUMB SPICE BSIM3.txt inclusion

Copy SCN4M_SUMB SPICE BSIM3.txt file of C:\MyChip Station Pro 2005\Layout\spice file

to amp.cir and write the signal or voltage etc for simulation. Also, treat part of non-required

simulation as comment same as part of below figure red square, and put input variable

things.

< Figure 2.3.(2)-34 Change the content of extracted Netlist >

iii. RUN

Menu Analysis Select Run Standard Spice File

Select v[vout][voltage] to “Select Variables to Slot window” and select Magnitude on AC

Options and press OK with checking DB Scale.

< Figure 2.3.(2)-35 Select plot which will be extracted >

< Figure 2.3.(2)-36>

Select v[vout] which is wanted result on Variables To slot window, press OK with selecting

the Phase on AC Option.

< Figure 2.3.(2)-37 Select plot which will be extracted >

< Figure 2.3.(2)-38 >

When all windows that to be output the simulation result as figure 2.3.(2)-38 are show

up ,select menu Control select Start Simulation.

< Figure 2.3.(2)-39 Execution result >

iv. Result confirmation

After confirming the window of Simulation Statistics and press OK and then Simulation is

completed.


In case that the result value doesn’t show up on screen when selecting menu Format

Auto Scale, Result value is show up as below.

< Figure 2.3.(2)-41 Output wave >

(3) Comparison & analysis for Layout & Schematic

① Netlist comparison [MyLVS (Hierarchical Layout Versus Schematic Netlist Comparator)]

MyLVS compare extracted Netlist from Layout & Schematic. When selecting Menu

Verification LVS at LayEd Pro 2005, MyLVS Pro window is show up.

< Figure 2.3.(3)-1 MyLVS execution >

i. Rule & Discrepancy

Use the used rule file on LayNet Pro for Rule. select C:\MyChip Station Pro

2005\Layout\tecfile\SCMOS_SCN4ME_SUBM_ERC.rul

Disc(Discrepancy)file means information for comparison result two Netlist. Fix the file that Rule

can keep information. fix amp.dis on C:\MyChip Station Pro 2005\Layout\Work\amp._00.

amp._00 file is folder to be made when amp Cell is created on LayEd.

< Figure 2.3.(3)-2 Discrepancy file creation >

ii. Layout or Schematic1

Load C:\MyChip Station Pro 2005\Layout\work\amp.prj on Project.

Project & Cell that made on Layout were saved automatically. But it’s ok to insert Schematic

Library if you are doing SVS. Decide what kind of Spice to use in the column of Type. It is

selected to use Spice here

iii. Schematic or Schematic2

Load extracted Netlist on Schematic editor.

Load C:\MyAnalogV63\schematic\output\amp.cir. (Load file that is not included file. It’s not

related with comparison for MOS model)

< Figure 2.3.(3)-3 Load Netlist file to compare >

Select Spice in the column of Type. It’s possible to compare Schematic Netlist of CDL,

HSPICE, PSPICE Type.

< Figure 2.3(3)-4 Option selection >

iv. Mode

It can also compare that LVS (Layout Versus Schematic) to SVS (Schematic Versus

Schematic). Select LVS here

v. Option

Above is part for construction change and below is part for tolerance range for size

difference of two Netlist feature. Click OK.

< Figure 2.3.(3)-5 Option selection >

< Figure 2.3.(3)-6 Execution >

Execute with pressing Run after making like figure 2.3.(3)-6.

② Discrepancy file confirmation

After MyLVS is completed, you can confirm the Error on Message window.


After confirmation, window of Verification Errors is show up when pressing Close. Screen move

to Error point on Layout when double click Error on Message window.


③ Comparison for Layout Spice Simulation and Schematic Spice Simulation

< Figure 2.3.(3)-9 Result wave(from layout)>

< Figure 2.3.(3)-10 Result wave (from schematic)>

(4) Layout data transformation

① CifGDS Pro

MyChip Station Pro CifGDS Pro (It can change Layout design of MyChip as Data Converter to

file which is to manufacture of Mask (GDSll, CIF, DXF) also it’s possible to convert the files

mutually). Have execute. Take MyChip To GDSll conversion as an example

i. Mode

Select MyChip To GDSll.

ii. MyChip To GDSll

Project select C:\MyChip Station Pro 2005\Layout\Work\amp.prj

GDSll File is assigned to Work folder as amp.gds and Technology is assigned as

SCMOS_SCN4ME_SUBM.TEC automatically.

iii. Preferences

Version select to way which meet to Mask manufacture. Select 6.0 version here.

iv. Cell name

Select Case sensitive.

< Figure 2.3.(4)-1 Layout data conversion >

Execute with pressing Translate when it is completed such as figure 2.3.(4)-1.


You can see the results for Layer mapping.. After verification, close the window with pressing

Close and check amp.gds on C:\MyChip Station Pro 2005\Layout\Work.

< Figure 2.3.(4)-3 File for execution result is created >

APPENDIX A Technology File

A.1. SCMOS_SCN4ME_SUBM.TEC

#----------------------------------------------

% definition

#----------------------------------------------

nwell

active

thk_active

poly

nplus

pplus

poly2

contact

via

metal1

metal2

via2

metal3

via3

metal4

glass

probe

res_mask

polytxt

me1txt

me2txt

me3txt

me4txt

#----------------------------------------------

stipple_file

#----------------------------------------------

stipple.lst

#----------------------------------------------

% cif_name

#----------------------------------------------

nwell CWN

active CAA

thk_active CUK

poly CPG

nplus CSN

pplus CSP

poly2 OPS

contact CCC

via CV1

metal1 CM1

metal2 CM2

via2 CV2

metal3 CM3

via3 CV3

metal4 CM4

glass COG

probe XP

res_mask CRM

polytxt CPT

me1txt CM1T

me2txt CM2T

me3txt CM3T

me4txt CM4T

#----------------------------------------------

% dxf_name

#----------------------------------------------

nwell DXF

active DXF

thk_active DXF

poly DXF

nplus DXF

pplus DXF

poly2 DXF

contact DXF

via DXF

metal1 DXF

metal2 DXF

via2 DXF

metal3 DXF

via3 DXF

metal4 DXF

glass DXF

probe DXF

res_mask DXF

polytxt DXF

me1txt DXF

me2txt DXF

me3txt DXF

me4txt DXF

#----------------------------------------------

% gds_num

#----------------------------------------------

nwell 42

active 43

thk_active 60

poly 46

nplus 45

pplus 44

poly2 56

contact 25

via 50

metal1 49

metal2 51

via2 61

metal3 62

via3 30

metal4 31

glass 34

probe 26

res_mask 79

polytxt 74

me1txt 75

me2txt 76

me3txt 77

me4txt 78

#----------------------------------------------

% color

#----------------------------------------------

nwell 255 255 0

active 0 198 0

thk_active 255 255 0

poly 255 0 0

nplus 196 0 196

pplus 255 161 0

poly2 255 128 64

contact 128 128 128

via 125 125 0

metal1 0 0 250

metal2 0 255 255

via2 0 198 0

metal3 255 213 0

via3 255 128 0

metal4 212 153 255

glass 255 255 157

probe 255 0 0

res_mask 0 255 0

polytxt 255 0 0

me1txt 0 0 255

me2txt 0 204 204

me3txt 255 213 0

me4txt 212 153 255

#----------------------------------------------

% fill_style

#----------------------------------------------

nwell empty

active stipple_9

thk_active empty

poly stipple_9

nplus stipple_3

pplus stipple_3

poly2 stipple_10

contact solid

via solid

metal1 stipple_2

metal2 stipple_3

via2 solid

metal3 stipple_2

via3 solid

metal4 stipple_3

glass solid

probe empty

res_mask empty

polytxt empty

me1txt empty

me2txt empty

me3txt empty

me4txt stipple_5

#----------------------------------------------

% line_color

#----------------------------------------------

nwell 255 255 0

active 0 198 0

thk_active 255 255 0

poly 255 0 0

nplus 196 0 196

pplus 255 161 0

poly2 255 128 64

contact 128 128 128

via 125 125 0

metal1 0 0 250

metal2 0 255 255

via2 0 198 0

metal3 255 213 0

via3 255 128 0

metal4 212 153 255

glass 255 255 157

probe 255 0 0

res_mask 0 255 0

polytxt 255 0 0

me1txt 0 0 255

me2txt 0 204 204

me3txt 255 213 0

me4txt 212 153 255

#----------------------------------------------

% line_style

#----------------------------------------------

nwell 0

active 0

thk_active 0

poly 0

nplus 0

pplus 0

poly2 0

contact 0

via 0

metal1 0

metal2 0

via2 0

metal3 0

via3 0

metal4 0

glass 0

probe 0

res_mask 0

polytxt 0

me1txt 0

me2txt 0

me3txt 0

me4txt 0

#----------------------------------------------

% line_width

#----------------------------------------------

nwell 1

active 1

thk_active 1

poly 1

nplus 1

pplus 1

poly2 1

contact 1

via 1

metal1 1

metal2 1

via2 1

metal3 1

via3 1

metal4 1

glass 1

probe 1

res_mask 1

polytxt 1

me1txt 1

me2txt 1

me3txt 1

me4txt 1

#----------------------------------------------

% line_color_sel

#----------------------------------------------

nwell 255 0 0

active 255 0 0

thk_active 255 0 0

poly 255 0 0

nplus 255 0 0

pplus 255 0 0

poly2 255 0 0

contact 255 0 0

via 255 0 0

metal1 255 0 0

metal2 255 0 0

via2 255 0 0

metal3 255 0 0

via3 255 0 0

metal4 255 0 0

glass 255 0 0

probe 255 0 0

res_mask 255 0 0

polytxt 255 0 0

me1txt 255 0 0

me2txt 255 0 0

me3txt 255 0 0

me4txt 255 0 0

#----------------------------------------------

% line_style_sel

#----------------------------------------------

nwell 0

active 0

thk_active 0

poly 0

nplus 0

pplus 0

poly2 0

contact 0

via 0

metal1 0

metal2 0

via2 0

metal3 0

via3 0

metal4 0

glass 0

probe 0

res_mask 0

polytxt 0

me1txt 0

me2txt 0

me3txt 0

me4txt 0

#----------------------------------------------

% line_width_sel

#----------------------------------------------

nwell 3

active 3

thk_active 1

poly 3

nplus 3

pplus 3

poly2 3

contact 3

via 3

metal1 3

metal2 3

via2 3

metal3 3

via3 3

metal4 3

glass 1

probe 1

res_mask 3

polytxt 3

me1txt 3

me2txt 3

me3txt 3

me4txt 3

#----------------------------------------------

% path

#----------------------------------------------

nwell 1.000 0 0.000 0.0

active 1.000 0 0.000 0.0

thk_active 1.000 0 0.000 0.0

poly 1.000 0 0.000 0.0

nplus 1.000 0 0.000 0.0

pplus 1.000 0 0.000 0.0

poly2 1.000 0 0.000 0.0

contact 1.000 0 0.000 0.0

via 1.000 0 0.000 0.0

metal1 1.000 0 0.000 0.0

metal2 1.000 0 0.000 0.0

via2 1.000 0 0.000 0.0

metal3 1.000 0 0.000 0.0

via3 1.000 0 0.000 0.0

metal4 1.000 0 0.000 0.0

glass 1.000 0 0.000 0.0

probe 1.000 0 0.000 0.0

res_mask 1.000 0 0.000 0.0

polytxt 1.000 0 0.000 0.0

me1txt 1.000 0 0.000 0.0

me2txt 1.000 0 0.000 0.0

me3txt 1.000 0 0.000 0.0

me4txt 1.000 0 0.000 0.0

#----------------------------------------------

% datatype

#----------------------------------------------

nwell 0

active 0

thk_active 0

poly 0

nplus 0

pplus 0

poly2 0

contact 0

via 0

metal1 0

metal2 0

via2 0

metal3 0

via3 0

metal4 0

glass 0

probe 0

res_mask 0

polytxt 0

me1txt 0

me2txt 0

me3txt 0

me4txt 0

#----------------------------------------------

% textsize

#----------------------------------------------

nwell 0.5

active 0.5

thk_active 1.0

poly 0.5

nplus 0.5

pplus 0.5

poly2 0.5

contact 0.5

via 0.5

metal1 0.5

metal2 0.5

via2 0.5

metal3 0.5

via3 0.5

metal4 0.5

glass 1.0

probe 1.0

res_mask 0.5

polytxt 1.0

me1txt 0.5

me2txt 0.5

me3txt 1.0

me4txt 1.0

#----------------------------------------------

% priority

#----------------------------------------------

nwell 17

active 11

thk_active 10

poly 6

nplus 8

pplus 9

poly2 5

contact 15

via 14

metal1 4

metal2 3

via2 13

metal3 2

via3 12

metal4 1

glass 16

probe 18

res_mask 7

polytxt 23

me1txt 22

me2txt 21

me3txt 20

me4txt 19

#----------------------------------------------

% sys_color

#----------------------------------------------

background 0 0 0

foreground 255 255 255

text 255 255 255

noselect 0 128 0

cellbound 255 255 255

grid 255 255 255

drag 255 0 0

error 255 0 0

ruler 255 255 255

instance_select 255 0 0

edge_vertex 0 0 255

#----------------------------------------------

% rule

#----------------------------------------------

DRC_RULE

EXTRACTION_RULE

#----------------------------------------------

A.2. STIPPLE.LST

stipple_1 ffff4242 ffffc3c3 ffff3c3c ffff2424 ffff2424 ffff3c3c ffffc3c3 ffff4242 ffff4242 ffffc3c3

ffff3c3c ffff2424 ffff2424 ffff3c3c ffffc3c3 ffff4242 ZigZags [ ZigZags 45 6 6 5 ]

stipple_2 ffff8888 ffff4444 ffff2222 ffff1111 ffff8888 ffff4444 ffff2222 ffff1111 ffff8888 ffff4444

ffff2222 ffff1111 ffff8888 ffff4444 ffff2222 ffff1111 Stripes [ Stripes 135 5 ]




ffff6060 ffff0000 ffff0000 ffff0606 ffff0606 ffff0000 BrokenStripes.Debug [ BrokenStripes.Debug

4 0 11 11 6 0 ]




ffff0000 ffff8181 ffff8181 ffff0000 ffff0000 ffff1818 Polygons [ Polygons 8 45 11 11 0 2

SQUARE ]


ffff4040 ffff2020 ffff0202 ffff0404 ffff0808 ffff1010 ZigZags [ ZigZags 135 9 8 11 ]


ffff6060 ffff0000 ffff0000 ffff0606 ffff0606 ffff0000 Polygons [ Polygons 10 45 7 7 0 1 CIRCLE ]


ffff5555 ffff0000 ffff5555 ffff0000 ffff5555 ffff0000 Crosses.Debug [ Crosses.Debug 3 0 11 11 0

4 0 ]

stipple_10 ffff8400 ffff1090 ffff0002 ffff2410 ffff0085 ffff0000 ffff8a20 ffff0004 ffff4021 ffff0880

ffff4008 ffff0420 ffff2101 ffff0010 ffff1202 ffff4090 BrokenStripes [ BrokenStripes 6 0 11 11 -10

1 ]


ffff0000 ffff1010 ffff0000 ffff0000 ffff0000 ffff1111 Crosses [ Crosses 9 0 8 8 0 3 0 ]

error ffff8181 ffff4242 ffff2424 ffff1818 ffff1818 ffff2424 ffff4242 ffff8181 ffff8181 ffff4242 ffff2424

ffff1818 ffff1818 ffff2424 ffff4242 ffff8181 Crosses.Debug [ Crosses.Debug 7 45 11 11 0 5 0 ]

B Verification File B.1. SCMOS_SCN4ME_SUBM_DRC.rul

;###################################################################################

;# MyCAD, Inc. shall not be liable for the accuracy of #

;# this design rule file or it's ability to capture errors. #

;# The user is responsible for thoroughly testing and implementing #

;# it's features. #

;###################################################################################

;

;###################################################################################

;# MOSIS SCMOS 0.35um Design rule for MyChip (ref. http://www.mosis.com) #

;# TSMC (0.35um N-well) SCN4ME_SUBM (Lambda=0.2 um) #

;# by MyCAD Support Group #

;# #

;# Support Information: #

;# #

;# This rule file is supported by MyCAD, Inc. customer support. #

;# For contact information consult [email protected] #

;# #

;# Revision History: #

;# #

;# 08/17/2004 Build #

;# #

;# 08/20/2004 First Release #

;###################################################################################

;

;###################################################################################

;# DESCRIPTION BLOCK #

;###################################################################################

;

;technology layers: nwell active thk_active pplus nplus poly poly2 contact

; metal1 via metal2 via2 metal3 via3 metal4

; glass

; probe (non-fab layer used to highlight pads)

;

*DESCRIPTION

LAMBDA = 0.2

CHECK-MODE = FLAT

;

;

;##################################################################################

;# LAYER BLOCK #

;##################################################################################

;

*LAYER

SUBSTRATE = pbulk

CONNECT-LAYER = psub nwell psd nsd poly poly2 metal1 metal2 metal3 metal4

;

;

;##################################################################################

;# OPERATION BLOCK #

;##################################################################################

;

*OPERATION

NOT pbulk nwell psub

AND active pplus pactive

AND active nplus nactive

OR pplus nplus allselect

AND pactive poly pgate

AND nactive poly ngate

NOT pactive pgate psd

NOT nactive ngate nsd

AND psub psd pplug

AND nwell nsd nplug

AND pplug contact ppcont

AND nplug contact npcont

; Interlayer connection

CONNECT metal4 metal3 BY via3


CONNECT metal2 metal1 BY via

CONNECT metal1 poly BY contact

CONNECT metal1 poly2 BY contact

CONNECT metal1 psd BY contact

CONNECT metal1 nsd BY contact

; Substrate & Well connection

SCONNECT psd psub BY ppcont

SCONNECT nsd nwell BY npcont

;

;###############################################################################

; n-well(Lambda base)

;###############################################################################

WIDTH nwell LT 12 "Rule 1.1:width(n-well) < 12"

EXT[N] nwell LT 18 "Rule 1.2:space(n-well) diff vtg < 18"

EXT[N'] nwell LT 6 "Rule 1.3:space(n-well) same vtg < 6"

;###############################################################################

; active(Lambda base)

;###############################################################################

WIDTH active LT 3 "Rule 2.1:width(active) < 3"

EXT active LT 3 "Rule 2.2:space(active) < 3"

ENC pactive nwell LT 6 "Rule 2.3:well edge < 6"

EXT nactive nwell LT 6 "Rule 2.3:well edge < 6"

ENC nplug nwell LT 3 "Rule 2.4:well contact space < 3"

EXT pplug nwell LT 3 "Rule 2.4:well contact space < 3"

AND nactive pactive npact

ERROR npact "Rule 2.5:no overlap violation"

SELECT pactive OVERLAP nactive overpact

SELECT nactive OVERLAP pactive overnact

NOT pactive overpact notoverpact

NOT nactive overnact notovernact

EXT notovernact notoverpact LT 4 "Rule 2.5:space(nactive,pactive)<4"

;###############################################################################

; thick active (Lambda base)

;###############################################################################

WIDTH thk_active LT 4 "Rule 24.1: width(thick active) < 4"

EXT thk_active LT 4 "Rule 24.2: space(thick active) < 4"

ENC active thk_active LT 4 "Rule 24.3: active overlap < 4"

SELECT thk_active ENCLOSE active encthk

EXT thk_active active LT 4 "Rule 24.4. space(thick active, active) < 4"

AND thk_active active thkact

AND thkact poly thkgate

WIDTH thkgate LT 3 "Rule 24.5. width(thick active gate poly) < 3"

NOT thk_active encthk nonthk

ERROR nonthk "Rule 24.6. Not enclose active"

;###############################################################################

; poly(Lambda base)

;###############################################################################

WIDTH poly LT 2 "Rule 3.1:width(poly) < 2"

EXT poly LT 3 "Rule 3.2:space(poly) < 3"

SELECT poly CUT active polyact

AND active polyact actpact

ENC[T] actpact active LT 0.001 &

ENC[T] actpact polyact LT 2 "Rule 3.3:min gate poly extension over active < 2"

SELECT active CUT poly actpoly

AND poly actpoly polyapoly

ENC[T] polyapoly poly LT 0.001 &

ENC[T] polyapoly actpoly LT 3 "Rule 3.4:min active extension over gate poly < 3"

OR poly active polact

EXT[H] polact LT 1 "Rule 3.5:min space between active and routing poly < 1"

;###############################################################################

; poly2(Lambda base) for Capacitor

;###############################################################################

WIDTH poly2 LT 7 "Rule 11.1:width(poly2) < 7"

EXT poly2 LT 3 "Rule 11.2:space(poly2) < 2"

ENC poly2 poly LT 5 "Rule 11.3:poly overlap < 5"

EXT poly2 nwell LT 2 "Rule 11.4:space(poly2,nwell) < 2"

EXT poly2 active LT 2 "Rule 11.4:space(poly2,active) < 2"

EXT poly2 contact LT 6 "Rule 11.5:space(poly2,contact) < 6"

SELECT NOT metal1 CUT poly2 notmet1p2

EXT poly2 notmet1p2 LT 2 "Rule 11.6:min spacing to metal < 2"

;###############################################################################

; select(Lambda base)

;###############################################################################

ENC[O] active poly LT 0.001 &

EXT allselect poly LT 3 "Rule 4.1:min select spacing to channel<3"

ENC active pplus LT 2 "Rule 4.2:min select overlap of active<2"

ENC active nplus LT 2 "Rule 4.2:min select overlap of active<2"

ENC contact pplus LT 1 "Rule 4.3:min select overlap of contact<2"

ENC contact nplus LT 1 "Rule 4.3:min select overlap of contact<2"

WIDTH pplus LT 2 "Rule 4.4:min p+ select width<2"

WIDTH nplus LT 2 "Rule 4.4:min n+ select width<2"

EXT pplus LT 2 "Rule 4.4:min p+ select space<2"

EXT nplus LT 2 "Rule 4.4:min n+ select space<2"

AND nplus pplus npplus

ERROR npplus "Rule 4.4:no overlap violation"

SELECT nplus OVERLAP pplus overnplus

SELECT pplus OVERLAP nplus overpplus

NOT nplus overnplus notovernplus

NOT pplus overpplus notoverpplus

EXT notovernplus notoverpplus LT 2 "Rule 4.4:min space(between n+ and p+ select)<2"

;###############################################################################

; simple contact to poly(Lambda base)

;###############################################################################

LENGTH contact NE 2 "Rule 5.1.1:exact contact size < 2"

AREA contact NE 0.8 "Rule 5.1.3:exact contact size < 0.8"

ENC contact poly LT 1.5 "Rule 5.2:minimum poly overlap < 1.5"

EXT contact LT 3 "Rule 5.3:space(contact)<3"

EXT contact pgate LT 2 "Rule 5.4:space(contact)<2"

EXT contact ngate LT 2 "Rule 5.4:space(contact)<2"

;###############################################################################

; simple contact to active(Lambda base)

;###############################################################################

ENC contact active LT 1.5 "Rule 6.2:min active overlap <1.5"

;###############################################################################

; contact to poly2(Lambda base)

;###############################################################################

AND contact poly2 poly2cont

AND poly poly2 polycap

AND poly2cont polycap pcapcont

NOT poly2cont pcapcont npcapcont

ENC pcapcont poly2 LT 3 "Rule 13.3:minimum electrode overlap on cap <3"

ENC npcapcont poly2 LT 2 "Rule 13.4:minimum electrode overlap not on cap <2"

EXT poly2cont poly LT 3 "Rule 13.5:space(poly2 contact,poly)<3"

EXT poly2cont active LT 3 "Rule 13.5:space(poly2 contact,active)<3"

;###############################################################################

; metal1(Lambda base)

;###############################################################################

WIDTH metal1 LT 3 "Rule 7.1:width(metal1) < 3"

EXT metal1 LT 3 "Rule 7.2:space(metal1) < 3"

ENC contact metal1 LT 1 "Rule 7.3:enclose(metal1, contact) < 1"

;###############################################################################

; via(Lambda base)

;###############################################################################

LENGTH via NE 2 "Rule 8.1.1:exact via size < 2"

AREA via NE 0.8 "Rule 8.1.4:exact via size < 0.8"

EXT via LT 3 "Rule 8.2:min via space < 3"

ENC via metal1 LT 1 "Rule 8.3:enclose(metal1,via)<1"

EXT via contact LT 2 "Rule 8.4:min space(via,contact)<2"

EXT via poly LT 2 "Rule 8.5:min space(via,poly)<2"

EXT via active LT 2 "Rule 8.5:min space(via,active)<2"

;###############################################################################


;###############################################################################

WIDTH metal2 LT 3 "Rule 9.1:min width(metal2)<3"

EXT metal2 LT 3 "Rule 9.2:min space(metal2)<3"

ENC via metal2 LT 1 "Rule 9.3:enclose(metal2,via)<1"

;###############################################################################

; via2(Lambda base)

;###############################################################################

LENGTH via2 NE 2 "Rule 14.1.1:exact via2 size < 2"

AREA via2 NE 0.8 "Rule 14.1.3:exact via2 size < 1.2"

EXT via2 LT 3 "Rule 14.2:min via2 space < 3"

ENC via2 metal2 LT 1 "Rule 14.3:enclose(metal2,via2)<1"

EXT via2 via LT 2 "Rule 14.4:min space(via2,via)<2"

;###############################################################################


;###############################################################################




;###############################################################################

; via3(Lambda base)

;###############################################################################

LENGTH via3 NE 2 "Rule 21.1.1:exact via3 size < 2"

AREA via3 NE 0.8 "Rule 21.1.3:exact via3 size < 1.2"

EXT via3 LT 3 "Rule 21.2:min via3 space < 3"


;###############################################################################


;###############################################################################




;###############################################################################

; overglass(micron base)

; top metal : metal2

;###############################################################################

SELECT glass ENCLOSE probe bpad

NOT glass bpad ppad

SELECT metal2 ENCLOSE glass padmetal

WIDTH bpad LT 300 "Rule 10.1:width(pad) < 60um"

WIDTH ppad LT 100 "Rule 10.2:width(probe pad) < 20um"

ENC glass padmetal LT 30 "Rule 10.3:minimum pad metal overlap < 6um"

EXT[N] padmetal metal2 LT 150 "Rule 10.4:min space(pad-metal,metal4) < 30um"

EXT padmetal active LT 75 "Rule 10.5:min space(pad-metal,active) < 30um"

EXT padmetal poly LT 75 "Rule 10.5:min space(pad-metal,poly) < 30um"

*END

B.2. SCMOS_SCN4ME_SUBM_ERC.rul

;###################################################################################




;# it's features. #

;###################################################################################

;

;####################################################################################

######

;# MOSIS SCMOS 0.35um Extraction, ERC and LVS rule for MyChip (ref. http://www.mosis.com) #

;# TSMC (0.35um N-well) SCN4ME_SUBM (Lambda=0.2 um)

#


;# #


;# #



;# #


;# #

;# 08/17/2004 Build #

;# #


;####################################################################################

######

;

;###################################################################################


;###################################################################################

;



; glass


;

*DESCRIPTION

;

MODEL = MOS[P],pmos MOS[N],nmos

MODEL = DIO[P],pdio DIO[N],ndio

MODEL = CAP[P],C

MODEL = RES[P],R

;

CHECK-MODE = FLAT

;

*LAYER

;

SUBSTRATE = pbulk

;

CONNECT-LAYER = psub nwell psd nsd ipoly poly2 metal1 metal2 metal3 metal4

;

ATTACH me1txt TO metal1




;

;

;##################################################################################


;##################################################################################

;

*OPERATION

;

; p-substrate


; gate and source/drain for MOS






NOT nactive poly nsd

NOT pactive poly psd

; well and substrate contact

AND psub psd pplug

AND nwell nsd nplug



; poly resistor

AND poly res_mask polres

NOT poly polres ipoly

; capacitor of poly and poly2


; parasitic capacitor between poly and metal1

AND metal1 ipoly me1poly



; parasitic capacitor between metal1 and metal2

AND metal1 metal2 me1me2

; parasitic diode

AND psd nwell pdio

AND nsd psub ndio

; interlayer connection





CONNECT metal1 ipoly BY contact



; well and substrate connection


SCONNECT nsd nwell BY npcont

;

; polysilicon resistor

ELEMENT RES[P] polres ipoly

PARAMETER RES[P] 6.0

; mos

ELEMENT MOS[P] pgate ipoly psd nwell

ELEMENT MOS[N] ngate ipoly nsd psub

; parasitic diode

;ELEMENT DIO[P] pdio psd nwell

;ELEMENT DIO[N] ndio nsd psub

; polysilicon capacitor

ELEMENT CAP[P] polycap ipoly poly2

PARAMETER CAP[P] 8.30e-4 0.0


;PARASITIC CAP[A] me1poly metal1 ipoly

;ATTRIBUTE CAP[A] 4.40e-5 5.70e-5


;PARASITIC CAP[B] me2poly metal2 ipoly

;ATTRIBUTE CAP[B] 1.50e-5 3.80e-5


;PARASITIC CAP[C] me1me2 metal1 metal2

;ATTRIBUTE CAP[C] 3.40e-5 5.40e-5

;

; ERC

MULTILAB "Short circuit"

SAMELAB "Open circuit"

PATHCHK LEVEL 1 "no path to power"

LCONNECT psub CONN VDD "psub connected to power"

LCONNECT psub DISC GND "psub not connected to ground"

;ELCOUNT MOS ALL EQ 1 "singular node"

NDCOUNT MOS ALL EQ 1 "all terminal tied together"

ECONNECT MOS[N] ipoly CONN VDD "n-mos gate connected to power"

ECONNECT MOS[P] ipoly CONN GND "p-mos gate connected to ground"

ECONNECT MOS[P] psd CONN GND "p-mos source/drain connected to ground"

;

; LVSCHK

LVSCHK[CS]WPERCENT=5 LPERCENT=5 CAPAREA=5 CAPVAL=5 DIOAREA=10 DIOPERI=10

RESVAL=10

*END

B.3. SCMOS_SCN4ME_SUBM_ERC(nwell).rul

;##########################################################################

#########




;# it's features. #

;##########################################################################

#########

;

;##########################################################################

################

;# MOSIS SCMOS 0.35um Extraction, ERC and LVS rule for MyChip (ref. http://www.mosis.com)

#

;# TSMC (0.35um N-well) SCN4ME_SUBM (Lambda=0.2 um)

#


;# #


;# #



;# #


;# #

;# 08/17/2004 Build #

;# #


;##########################################################################

################

;

;##########################################################################

#########


;##########################################################################

#########

;



; glass


;

*DESCRIPTION

;

MODEL = MOS[P],pmos MOS[N],nmos

MODEL = DIO[P],pdio DIO[N],ndio

MODEL = CAP[P],C

MODEL = RES[P],PR

MODEL = RES[N],NR

;

CHECK-MODE = FLAT

;

*LAYER

;

SUBSTRATE = pbulk

;

CONNECT-LAYER = psub inwell psd nsd ipoly poly2 metal1 metal2 metal3 metal4

;





;

;

;##########################################################################

########


;##########################################################################

########

;

*OPERATION

;

; p-substrate


; gate and source/drain for MOS






NOT nactive poly nsd

NOT pactive poly psd

; well and substrate contact

AND psub psd pplug

AND nwell nsd nplug



; poly resistor

AND poly res_mask polres

NOT poly polres ipoly

; nwell resistor

AND nwell res_mask nwellres

NOT nwell nwellres inwell

; capacitor of poly and poly2







AND metal1 metal2 me1me2

; parasitic diode

AND psd nwell pdio

AND nsd psub ndio

; interlayer connection





CONNECT metal1 ipoly BY contact



; well and substrate connection


SCONNECT nsd inwell BY npcont

;

; polysilicon resistor

ELEMENT RES[P] polres ipoly

PARAMETER RES[P] 6.0

; nwell resistor

ELEMENT RES[N] nwellres inwell

PARAMETER RES[N] 10000

; mos

ELEMENT MOS[P] pgate ipoly psd inwell

ELEMENT MOS[N] ngate ipoly nsd psub

; parasitic diode

;ELEMENT DIO[P] pdio psd inwell

;ELEMENT DIO[N] ndio nsd psub

; polysilicon capacitor

ELEMENT CAP[P] polycap ipoly poly2

PARAMETER CAP[P] 3.1888e-3 0.0


;PARASITIC CAP[A] me1poly metal1 ipoly

;ATTRIBUTE CAP[A] 4.40e-5 5.70e-5


;PARASITIC CAP[B] me2poly metal2 ipoly

;ATTRIBUTE CAP[B] 1.50e-5 3.80e-5


;PARASITIC CAP[C] me1me2 metal1 metal2

;ATTRIBUTE CAP[C] 3.40e-5 5.40e-5

;

; ERC

MULTILAB "Short circuit"

SAMELAB "Open circuit"

PATHCHK LEVEL 1 "no path to power"

LCONNECT psub CONN VDD "psub connected to power"

LCONNECT psub DISC GND "psub not connected to ground"

ELCOUNT MOS ALL EQ 1 "singular node"

NDCOUNT MOS ALL EQ 1 "all terminal tied together"

ECONNECT MOS[N] ipoly CONN VDD "n-mos gate connected to power"

ECONNECT MOS[P] ipoly CONN GND "p-mos gate connected to ground"

ECONNECT MOS[P] psd CONN GND "p-mos source/drain connected to ground"

;

; LVSCHK

LVSCHK[CS]WPERCENT=5 LPERCENT=5 CAPAREA=5 CAPVAL=5 DIOAREA=10 DIOPERI=10

RESVAL=10

*END

C Spice File C.1. include.inc ( parameter)

* Transient Analysis

.TRAN 1ns 200ns

* TSMC 0352P4M

* SPICE BSIM3 VERSION 3.1 PARAMETERS

* SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8

.MODEL NMOS NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 7.6E-9

+XJ = 1E-7 NCH = 2.3579E17 VTH0 = 0.5027514

+K1 = 0.5359893 K2 = 0.0258172 K3 = 24.6606744

+K3B = 1.4055348 W0 = 5.355464E-6 NLX = 2.404522E-9

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = -0.120252 DVT1 = 3.084588E-3 DVT2 = 0.470688

+U0 = 417.429294 UA = -1.40534E-13 UB = 1.355832E-18

+UC = 2.939828E-11 VSAT = 1.208882E5 A0 = 0.9319916

+AGS = 0.1686015 B0 = 1.288356E-6 B1 = 5E-6

+KETA = 0.0105706 A1 = 0 A2 = 1

+RDSW = 1.103044E3 PRWG = 1.750872E-3 PRWB = -0.0916512

+WR = 1 WINT = 6.910593E-8 LINT = 1.993462E-8

+XL = -2E-8 XW = 0 DWG = 1.047524E-9

+DWB = 1.084571E-8 VOFF = -0.0906265 NFACTOR = 0.6164962

+CIT = 0 CDSC = 5.145568E-6 CDSCD = 0

+CDSCB = 0 ETA0 = 4.63499E-3 ETAB = -9.189583E-4

+DSUB = 0.1150044 PCLM = 0.7703416 PDIBLC1 = 0.3438859

+PDIBLC2 = 8.526878E-3 PDIBLCB = 0.0845601 DROUT = 0.6859339

+PSCBE1 = 7.23225E9 PSCBE2 = 5.005586E-10 PVAG = 0.4108257

+DELTA = 0.01 MOBMOD = 1 PRT = 0

+UTE = -1.5 KT1 = -0.11 KT1L = 0

+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18

+UC1 = -5.6E-11 AT = 3.3E4 WL = 0

+WLN = 1 WW = -1.22182E-15 WWN = 1.1837

+WWL = 0 LL = 0 LLN = 1

+LW = 0 LWN = 1 LWL = 0

+CAPMOD = 2 XPART = 0.4 CGDO = 2.95E-10

+CGSO = 2.95E-10 CGBO = 1E-11 CJ = 1.08158E-3

+PB = 0.7719669 MJ = 0.3252096 CJSW = 3.480034E-10

+PBSW = 0.99 MJSW = 0.1576976 PVTH0 = -0.0122678

+PRDSW = -93.3365259 PK2 = -3.470912E-3 WKETA = -3.503848E-3

+LKETA = -0.0105386 )

*

.MODEL PMOS PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 7.6E-9

+XJ = 1E-7 NCH = 8.52E16 VTH0 = -0.6821549

+K1 = 0.4197546 K2 = -6.11453E-3 K3 = 35.791795

+K3B = -2.796173 W0 = 1.990794E-6 NLX = 4.309814E-7

+DVT0W = 0 DVT1W = 0 DVT2W = 0

+DVT0 = 1.134781 DVT1 = 0.3272645 DVT2 = -1.051562E-3

+U0 = 141.3184274 UA = 1.024889E-10 UB = 1.354611E-18

+UC = -3.30244E-11 VSAT = 1.6171E5 A0 = 0.6693235

+AGS = 0.2959248 B0 = 2.86196E-6 B1 = 5E-6

+KETA = -6.382387E-3 A1 = 0 A2 = 1

+RDSW = 3.44286E3 PRWG = -0.0626736 PRWB = 0.0981315

+WR = 1 WINT = 5.340142E-8 LINT = 1.410986E-9

+XL = -2E-8 XW = 0 DWG = -4.209302E-9

+DWB = 1.12145E-8 VOFF = -0.1154702 NFACTOR = 2

+CIT = 0 CDSC = 0 CDSCD = 0

+CDSCB = 4.724734E-5 ETA0 = 0.0115959 ETAB = 2.08259E-4

+DSUB = 0.2766226 PCLM = 7.8965744 PDIBLC1 = 1.97648E-3

+PDIBLC2 = 8.825766E-3 PDIBLCB = 2.37472E-3 DROUT = 0.4321935

+PSCBE1 = 3.010835E10 PSCBE2 = 7.998967E-10 PVAG = 15

+DELTA = 0.01 MOBMOD = 1 PRT = 0

+UTE = -1.5 KT1 = -0.11 KT1L = 0

+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18

+UC1 = -5.6E-11 AT = 3.3E4 WL = 0

+WLN = 1 WW = -5.22182E-16 WWN = 1.195

+WWL = 0 LL = 0 LLN = 1

+LW = 0 LWN = 1 LWL = 0

+CAPMOD = 2 XPART = 0.4 CGDO = 2.77E-10

+CGSO = 2.77E-10 CGBO = 1E-11 CJ = 1.417679E-3

+PB = 0.99 MJ = 0.5636812 CJSW = 4.292884E-10

+PBSW = 0.99 MJSW = 0.3497357 PVTH0 = 0.0116448

+PRDSW = -58.3059685 PK2 = 1.654991E-3 WKETA = -6.310553E-4

+LKETA = 1.189744E-3 )

*

C.2. Layout Two stage amp(addition)

* Power/Ground

VDD VDD 0 DC 3.3V

VSS VSS 0 DC 0V* Load Cap

* Input

Vin VIN 0 DC 1.65 AC 0

Vip VIP 0 DC 1.65 AC 1

.AC DEC 10 10 10000MEG

mycad design practice -...

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