myrisc1

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1 Design Specification

Name: myRISC1

Specification:

1. 8-bit program counter

2.

256x8 instruction memory3. 256x8 data memory

4. 8-bit instruction register

5. 4x8 register file

6. 8-bit ALU

7. 8-bit data bus

8. 8-bit address bus

9. 1-bit status register

10. 16 8-bit instructions

10.1. One miscellaneous type instruction (NOP)

10.2. Eight register type instructions (ADD,SUB,OR,AND,XOR,MOV,LD,ST)

10.3. Four immediate type instructions (ADDI,SUBI,RLI,RHI)

10.4. Three jump type instructions (BZ,BNZ,BRA) – range of jump is from -8 to +7

11. Harvard memory architecture

2 RISC Instruction Set ArchitectureOne of the characteristics of RISC architectures is that it has a single instruction format. By providing a single

instruction format, the decoding of an instruction into its component fields can be performed by a minimum

level of decoding logic. A RISC’s instruction length should be sufficient to accommodate the operation code

field (opcode) and one or more operand fields. Consequently, a RISC processor may not utilize memory space

as efficiently as a conventional CISC microprocessor. Figure below describes the format of a Berkeley RISC

instruction, one of the first RISC processor that came from the University of California at Berkeley.

The op-code field is the Operation code field that indicates the code for each instruction. Each instruction hasits own unique Op-code. Scc field whether the condition code bits are updated after the execution of an

instruction. Destination and Source 1 fields determine the address of register of which the result would be

written into and the first source for an instruction’s operand, respectively. The IM field determines the source

for another instruction’s operand. If it is 0, the source is the 5-bit address of the registers while if it is 1, the

source is the 13-bit immediate number. Because of 5-bits are allocated to each operand field, it follows that

this RISC can access up to 25 = 32 internal registers at a time.

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3 RTL Design Methodology

Design Spcification

Algorithmic Modeling

ASM Flowchart

RTL Code

FBD - DU

RTL-CS Table

FBD - CU

Top Level IOBD

Verilog HDL Code

FBD – Top Level

Synthesizing

Performance Analysis

Testbench

Pre-synthesis

Post-synthesis

RTL Modeling

RTL Design

RTL Verification

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4 Processor Resources

1. Program Counter (PC)

PC

07

2. Instruction Memory (IM)

IM

0x00

0xFF

07

3. Instruction Register (IR)

IR

07

4. Register File (RF)

RF

0

3

07

5. Data Memory (DM)

DM

0x00

0xFF

07

6. Status Register

SR

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5 Processor Functional Units

1. Program Counter (PC)

Program counter contain the next instruction address to be executed. This address will be input theprogram RAM to access a specific line of instructions. Normally, PC would be increased after every

instruction executed to point to the next address except if flow control instructions is executed

which modify the bits contain in the PC.

2. Program/Instructions Memory

Program memory contains the list of instruction to be executed. In Von Neumann architecture

machine, program memory and data memory use the common RAM, while in Harvard architecture

machine, program memory and data memory use separate RAMs.

3. Instruction Register

Instruction register contains the current instruction. It stores the current register temporarily and

connects to various other logic devices such as control logic, and register files. When the next

instruction is executed, it will overwrite the content of this instruction register.

4. Register File (General Purpose Registers)

In RISC machine, register files are the important characteristic. It serves as the general purpose

register to store temporary data that is executed by specific instruction. Register files are pretty

similar to the RAM except that it doesn’t have as much capacity as RAM and thus reduce the cost.

Typically, registers are faster than RAM that makes execution of register-register instruction could

be faster.

5. Arithmetic and Logic Unit

ALU is the unit that does the manipulation to the data such as addition, subtraction, logical AND,

logical OR and many more.

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6. Status Register

Update the flags when a specific instruction requires the flags to be updated. The flags can is the

input to the control unit and will take effect on the sequence of the program execution. The flags

can be zero, negative, carry and over flow.

7. Data Memory

Data memory is the storage device that store data from the program executed. It could be the

constants, variables, address etc. Normally, data that are stores here are not a frequently used data

as accessing the memory is slow thus make the program execution slower.

8. Control Unit

Control logic is among most important modules that make up a processor. It controls the sequence

and datapath flow of an instruction. When an instruction is executed, it fetch and decode the

opcode of that instruction and generate the control logic signals to the appropriate modules such as

register files, ALU and memory.

9. Address Bus and Data Bus

Bus is used to simplify the movement of data from point to point in a computer. Bus is analogous to

a highway and the devices are analogous to junctions that connect to this highway. By having both

address bus and data bus, it is possible to reduce the number of wires that interconnect within a

computer but, it introduces a complexity. In a bused system, only one communication from point to

point could happen at a time. Thus a careful synchronization needs to be taken care of and each

bus access time has to be long enough for the safe reception in a communication.

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6 Instruction Set and Format

opcode operand1 operand2 Assembly Language Mnemonics RTL Operation

0 0 0 0 NOP No Operation

0 0 0 1 Ra Rb ADD Ra,Rb Ra ← Ra + Rb ; update Z

0 0 1 0 Ra Rb SUB Ra,Rb Ra ← Ra - Rb ; update Z

0 0 1 1 Ra Rb OR Ra,Rb Ra ← Ra | Rb ; update Z

0 1 0 0 Ra Rb AND Ra,Rb Ra ← Ra & Rb ; update Z

0 1 0 1 Ra Rb XOR Ra,Rb Ra ← Ra ^ Rb ; update Z

0 1 1 0 Ra Rb MOV Ra,Rb Ra ← Rb ; update Z

0 1 1 1 Ra Rb LD Ra,Rb Ra ← M[Rb]

1 0 0 0 Ra Rb ST Ra,Rb M[Rb]← Ra

1 0 0 1 Ra m ADDI Ra,m Ra ← Ra + 000000m1m0 ; update Z

1 0 1 0 Ra m SUBI Ra,m Ra ← Ra - 000000m1m0 ; update Z

1 0 1 1 n RLI n R0← R0 | 0000n3n2n1n0 ; update Z

1 1 0 0 n RHI n R0← n3n2n1n00000 ; update Z

1 1 0 1 k BZ k(Z) / PC ← PC + k (k is 4 bit signednumber)

1 1 1 0 k BNZ k

(!Z) / PC ← PC + k (k is 4 bit signed

number)

1 1 1 1 k BRA k PC ← PC + k (k is 4 bit signed number)

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7 ASM Flowchart

PC ← 0

opcode

read , IR ← IM[PC]

RF[IR3:2] ← RF[IR3:2] + RF[IR1:0]

RF[IR3:2] ← RF[IR3:2] - RF[IR1:0]

RF[IR3:2] ← RF[IR3:2] | RF[IR1:0]

RF[IR3:2] ← RF[IR3:2] & RF[IR1:0]

RF[IR3:2] ← RF[IR3:2] ̂ RF[IR1:0]

RF[IR3:2] ← RF[IR1:0]

read , RF[IR3:2] ← DM[RF[IR1:0]]

RF[IR3:2] ← RF[IR3:2] + RF[IR1:0]

No action RF[IR3:2] ← RF[IR3:2] - RF[IR1:0]

RF[00] ← RF[00] | {4'b0,RF[IR3:0]}

RF[00] ← {RF[IR3:0],4'b0}

PC ← PC + {4'b0,IR[3:0]}

Z

!Z

PC ← PC + {4'b0,IR[3:0]}

PC ← PC - {4'b0,IR[3:0]}

DM[RF[IR1:0]] ← RF[IR3:2]

ADD

SUB

OR

AND

XOR

MOV

SUBI

LD0

ST

ADDI

RLI

RHI

BZ

BNZ

NOP

BRA

0

0

1

1

rst

S0

S1

IR ← IM[PC]

PC ← PC + 1

S2

S3

S4

S5

S6

S7

S8

S9

S14

S15

S16

S18

S19

S13

S10

S21

S20

S17

read , RF[IR3:2] ← DM[RF[IR1:0]]

LD1

S12

S11

start

1

0

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8 FBD-DU

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9 RTL-CS Table : Control Signal Activated

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10 RTL-CS Table : Control Vector

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11 FBD-CU

CU

opcode

clk rst

CV [14:0]Next State Logic State Register Output Logic15

rst

start

d q

PS[4:0]

PSNS

55z

12 IOBD and Interconnection -Top Level

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13 FBD-Top Level

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14 Verilog Code

1. myRISC1 Top Levelmodule myRISC1(clk,rst,start,PS,opcode,PC,IM_instr,IR_instr,CV,R0,R1,R2,R3,Z,A_ALU,B_ALU);

input clk,rst,start;

output [3:0] opcode;output [4:0] PS;output [7:0] R0,R1,R2,R3,A_ALU,B_ALU;output [7:0] PC;output [7:0] IM_instr;output [7:0] IR_instr;output [14:0] CV;output Z;

wire [3:0] opcode;wire [14:0] CV;wire Z;

wire [7:0] PC;wire [7:0] IM_instr;

wire [7:0] IR_instr;wire [7:0] A;wire [7:0] B;wire [8:0] out_alu;wire [7:0] data;wire [7:0] RF_wdata;wire [4:0] NS;wire [7:0] k;

DU myRISC1_DU(clk,rst,CV[14],CV[13],CV[12],CV[11],CV[10:8],CV[7],CV[6],CV[5],CV[4:3],CV[2:1],CV[0],opcode,out_alu,data,R0,R1,R2,R3,A,B,Z,k,PC,IR_instr,IM_instr,RF_wdata,A_ALU,B_ALU);

CU myRISC1_CU(clk,rst,start,opcode,Z,NS,PS,CV);

endmodule

2. Datapath UnitModule DU(clk,rst,clrPC,selPC,ldPC,ldIR,op_alu,ldSR,wDM,sel_MUX21_1,sel_MUX41_1,sel_MUX41_2,wRF,opcode,out_alu,data,A_reg,B_reg,C_reg,D_reg,A,B,Z,k,PC,IR_instr,IM_instr,RF_wdata,A_ALU,B_ALU);

input clk,rst;input ldPC,clrPC,selPC,ldIR,wRF,wDM,sel_MUX21_1,ldSR;input [1:0] sel_MUX41_1,sel_MUX41_2;input [2:0] op_alu;

output [8:0] out_alu;output [7:0] data;output [7:0] IR_instr,IM_instr,RF_wdata;output [7:0] A_reg,B_reg,C_reg,D_reg,A_ALU,B_ALU;output [7:0] A,B;

output [3:0] opcode;output [7:0] PC;output [7:0] k;output Z;

wire [7:0] i_addr_in;wire [7:0] i_instr;wire [3:0] i_opcode;wire [1:0] i_A_raddr;wire [1:0] i_B_raddr;wire [7:0] i_A_reg,i_B_reg,i_C_reg,i_D_reg;

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wire [7:0] i_A_data,i_B_data;wire [1:0] i_data_MUX21_1_0,i_data_MUX21_1_1,i_data_MUX21_1;wire [7:0] i_data_MUX41_1_0,i_data_MUX41_1_1,i_data_MUX41_1_2,i_data_MUX41_1;wire [1:0] i_A_waddr;wire [7:0] i_w_data;wire [7:0] i_A;wire [7:0] i_B;wire [8:0] i_out_alu;

wire [7:0] i_data;wire i_C,i_Z;wire [7:0] i_rwaddrM,i_PC;wire [7:0] i_wdataM;wire [7:0] i_rdataM;wire [7:0] i_data_MUX41_2_0,i_data_MUX41_2_1,i_data_MUX41_2_2,i_data_MUX41_2;

IFU DU_IFU(clk,rst,ldPC,clrPC,selPC,ldIR,i_instr,i_opcode,k,i_PC,IM_instr);MUX21_1 DU_MUX21_1(sel_MUX21_1,i_data_MUX21_1_0,i_data_MUX21_1_1,i_data_MUX21_1);RF DU_RF(clk,rst,wRF,i_A_raddr,i_B_raddr,i_A_reg,i_B_reg,i_C_reg,i_D_reg,i_A_data,i_B_data,i_A_waddr,i_w_data);

ALU DU_ALU(clk,rst,ldSR,op_alu,i_A,i_data_MUX41_1,i_out_alu,i_data,i_C,i_Z);MUX41_1 DU_MUX41_1(sel_MUX41_1,i_data_MUX41_1_0,i_data_MUX41_1_1,i_data_MUX41_1_2,i_data_MUX41_1);DM DU_DM(clk,wDM,i_rwaddrM,i_wdataM,i_rdataM);MUX41_2 DU_MUX41_2(sel_MUX41_2,i_data_MUX41_2_0,i_data_MUX41_2_1,i_data_MUX41_2_2,i_data_MUX41_2);

assign opcode = i_opcode;assign out_alu = i_out_alu;assign i_data_MUX21_1_0 = 2'b00;assign i_data_MUX21_1_1 = i_instr[3:2];assign data = i_data;assign IR_instr = i_instr;assign A_reg = i_A_reg;assign B_reg = i_B_reg;assign C_reg = i_C_reg;assign D_reg = i_D_reg;assign i_A_raddr = i_data_MUX21_1;assign i_B_raddr = i_instr[1:0];assign i_A_waddr = i_data_MUX21_1;assign i_w_data = i_data_MUX41_2;assign i_A = i_A_data;

assign i_B = i_B_data;assign A = i_A;assign B = i_B;assign i_wdataM = i_A_data;assign i_rwaddrM = i_data_MUX41_1;assign i_data_MUX41_1_0 = i_B;assign i_data_MUX41_1_1 = {6'b000000,i_instr[1:0]};assign i_data_MUX41_1_2 = {4'b0000,i_instr[3:0]};assign i_data_MUX41_2_0 = i_data_MUX41_1;assign i_data_MUX41_2_1 = i_data;assign i_data_MUX41_2_2 = i_rdataM;assign Z = i_Z;assign PC = i_PC;assign RF_wdata = i_data_MUX41_2;assign A_ALU = i_A;assign B_ALU = i_data_MUX41_1;

endmodule

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3. Instruction Fetch Unit (IFU)module IFU(clk,rst,ldPC,clrPC,selPC,ldIR,IR_instr,opcode,k,PC,IM_instr);

input clk,rst;input ldPC,clrPC,selPC,ldIR;output [3:0] k;output [7:0] PC;

output [7:0] IR_instr,IM_instr;output [3:0] opcode;

reg [7:0] k;

wire [7:0] i_PC;wire [7:0] i_w_instr,i_r_instr;wire [3:0] i_opcode;wire iwe;

PC IFU_PC(clk,rst,ldPC,clrPC,selPC,PC,k);IM IFU_IM(clk,iwe,PC,i_w_instr,i_r_instr);IR IFU_IR(clk,rst,ldIR,i_opcode,i_r_instr,IR_instr);

assign opcode = i_opcode;assign IM_instr = i_r_instr;

always@(IR_instr)if(IR_instr[3])

k = {4'b1111,IR_instr[3:0]};else

k = {4'b0000,IR_instr[3:0]};

endmodule

4. Program Counter (PC)module PC(clk,rst,ldPC,clrPC,selPC,PC,k);

input clk,rst,clrPC;input selPC,ldPC;

input [7:0] k;output [7:0] PC;reg [7:0] PC;

//PC_valuealways@(posedge clk or posedge rst)if(rst)

PC<=8'b00000000;else if(clrPC)

PC<=8'b00000000;else

if(ldPC)if(selPC)

PC<=PC+8'b00000001;else

PC<=PC+k;else

PC<=PC;

endmodule

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5. Instruction Memory(IM) //RAM 256 x 8 //using lpm_ram_dq //256 address location,8-bit data

module IM(clk,we,PC,w_instr,r_instr);

input clk;input we;input [i-1:0] w_instr;input [a-1:0] PC;

output [i-1:0] r_instr;

wire high;

assign high = 1;

parameter i=8; //instruction width = 8-bitparameter a=8; //address width = 12-bit

lpm_ram_dq myRAM(.q(r_instr), .data(w_instr), .address(PC), .we(we), .inclock(clk), .outclock(high));

defparam myRAM.lpm_width = 8;defparam myRAM.lpm_widthad = 8;defparam myRAM.lpm_indata = "REGISTERED";defparam myRAM.lpm_outdata = "UNREGISTERED";defparam myRAM.lpm_file = "IM.mif";

endmodule

6. Instruction Registermodule IR(clk,rst,ldIR,opcode,w_instr,r_instr);

input clk,rst;input ldIR;input [7:0] w_instr;

output [7:0] r_instr;output [3:0] opcode;reg [7:0] r_instr;

always@(posedge rst or posedge clk)if(rst) r_instr<=8'b00000000;else if(ldIR) r_instr<=w_instr;else r_instr<=r_instr;

assign opcode = r_instr[7:4];

endmodule

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7. Register File (RF)module RF(clk,rst,we,A_raddr,B_raddr,A_reg,B_reg,C_reg,D_reg,A_data,B_data,A_waddr,w_data);

input clk,rst;input we;input [1:0] A_raddr;input [1:0] B_raddr;

input [1:0] A_waddr;input [7:0] w_data;

output [7:0] A_reg,B_reg,C_reg,D_reg;output [7:0] A_data;output [7:0] B_data;

reg [7:0] A_reg,B_reg,C_reg,D_reg;reg [7:0] A_data;reg [7:0] B_data;

//writing to RFalways@(posedge clk or posedge rst)if(rst)begin

A_reg <= 8'b00000000;B_reg <= 8'b00000000;

C_reg <= 8'b00000000;D_reg <= 8'b00000000;end

else if(we)case(A_waddr)

0: A_reg <= w_data;1: B_reg <= w_data;2: C_reg <= w_data;3: D_reg <= w_data;

endcaseelse begin

A_reg <= A_reg;B_reg <= B_reg;C_reg <= C_reg;D_reg <= D_reg;end

//reading A_data

always@(A_raddr or A_reg or B_reg or C_reg or D_reg)case(A_raddr)

0: A_data = A_reg;1: A_data = B_reg;2: A_data = C_reg;3: A_data = D_reg;

endcase

//reading B_dataalways@(B_raddr or A_reg or B_reg or C_reg or D_reg)case(B_raddr)

0: B_data = A_reg;1: B_data = B_reg;2: B_data = C_reg;3: B_data = D_reg;

endcase

endmodule

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8. Arithmetic Logic Unit (ALU)module ALU(clk,rst,ldSR,op_alu,A,B,out_alu,data,C,Z);

input clk,rst;input ldSR;input [2:0] op_alu;input [7:0] A,B;

output [8:0] out_alu;output [7:0] data;output C,Z;reg [8:0] out_alu;reg Z;

always@(op_alu or A or B)case(op_alu)

0: out_alu = A + B;1: out_alu = A - B;2: out_alu = A | B;3: out_alu = A & B;4: out_alu = A ^ B;5: out_alu = A;6: out_alu = B;7: out_alu = {B[3:0],4'b0000};

default: out_alu = 9'bxxxxxxxx;endcase

//Status_Regalways@(posedge clk or posedge rst)if(rst)

Z<=1'b0;else

if(ldSR)Z<=(data==0);

elseZ<=Z;

assign data = out_alu[7:0];assign C = out_alu[8];

endmodule

9. Data Memory (DM)module DM(clk,we,rwaddrM,wdataM,rdataM);

input clk;input we;input [d-1:0] wdataM;input [a-1:0] rwaddrM;output [d-1:0] rdataM;

wire high;assign high = 1;parameter d = 8; //data width = 8-bitparameter a = 8; //address width = 8-bit

lpm_ram_dq myRAM(.q(rdataM), .data(wdataM), .address(rwaddrM), .we(we), .inclock(clk), .outclock(high));

defparam myRAM.lpm_width = 8;defparam myRAM.lpm_widthad = 8;defparam myRAM.lpm_indata = "REGISTERED";defparam myRAM.lpm_outdata = "UNREGISTERED";defparam myRAM.lpm_file = "DM.mif";

endmodule

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10. MUX21_1module MUX21_1(sel_MUX21_1,data_MUX21_1_0,data_MUX21_1_1,data_MUX21_1);

input sel_MUX21_1;input [1:0] data_MUX21_1_0,data_MUX21_1_1;

output [1:0] data_MUX21_1;

reg [1:0] data_MUX21_1;

always@(sel_MUX21_1 or data_MUX21_1_0 or data_MUX21_1_1)if(sel_MUX21_1)

data_MUX21_1 = data_MUX21_1_1;else

data_MUX21_1 = 2'b00;

endmodule

11. MUX41_1module MUX41_1(sel_MUX41_1,data_MUX41_1_0,data_MUX41_1_1,data_MUX41_1_2,data_MUX41_1);

input [1:0] sel_MUX41_1;input [7:0] data_MUX41_1_0,data_MUX41_1_1,data_MUX41_1_2;

output [7:0] data_MUX41_1;reg [7:0] data_MUX41_1;

always@(sel_MUX41_1 or data_MUX41_1_0 or data_MUX41_1_1 or data_MUX41_1_2)case(sel_MUX41_1)

0: data_MUX41_1 = data_MUX41_1_0;1: data_MUX41_1 = data_MUX41_1_1;2: data_MUX41_1 = data_MUX41_1_2;default data_MUX41_1 = 8'bxxxxxxxx;

endcase

endmodule

12. MUX41_2module MUX41_2(sel_MUX41_2,data_MUX41_2_0,data_MUX41_2_1,data_MUX41_2_2,data_MUX41_2);

input [1:0] sel_MUX41_2;input [7:0] data_MUX41_2_0,data_MUX41_2_1,data_MUX41_2_2;

output [7:0] data_MUX41_2;reg [7:0] data_MUX41_2;

always@(sel_MUX41_2 or data_MUX41_2_0 or data_MUX41_2_1 or data_MUX41_2_2)case(sel_MUX41_2)

0: data_MUX41_2 = data_MUX41_2_0;1: data_MUX41_2 = data_MUX41_2_1;2: data_MUX41_2 = data_MUX41_2_2;default data_MUX41_2 = 8'bxxxxxxxx;

endcase

endmodule

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S14: NS = S1;S15: NS = S1;S16: NS = S1;S17: if(Z)

NS = S18;else

NS = S1;S18: NS = S1;

S19: if(!Z)NS = S20;

elseNS = S1;

S20: NS = S1;S21: NS = S1;default: NS = S1;

endcaseend

//define OUTPUT LOGIC:always@(PS or start)begin

case(PS)S0 : begin CV = 15'h4000; endS1 : begin CV = 15'h0800; endS2 : begin CV = 15'h3800; endS3 : begin CV = 15'h0000; endS4 : begin CV = 15'h00A3; endS5 : begin CV = 15'h01A3; endS6 : begin CV = 15'h02A3; endS7 : begin CV = 15'h03A3; endS8 : begin CV = 15'h04A3; endS9 : begin CV = 15'h00A1; endS10 : begin CV = 15'h0025; endS11 : begin CV = 15'h0025; endS12 : begin CV = 15'h0060; endS13 : begin CV = 15'h00AB; endS14 : begin CV = 15'h01AB; endS15 : begin CV = 15'h0293; endS16 : begin CV = 15'h0793; end

S17 : begin CV = 15'h0000; endS18 : begin CV = 15'h1000; endS19 : begin CV = 15'h0000; endS20 : begin CV = 15'h1000; endS21 : begin CV = 15'h1000; enddefault :begin CV = 15'h0000; end

endcaseendendmodule

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15 Test Pattern

1. Input Program

Address

Instruction Machine Code

Instruction in decimalopcode operand1 operand2 opcode operand1 operand2

0x00 RHI #0 1 1 0 0 0 0 0 0 192

0x01 RLI #4 1 0 1 1 0 1 0 0 180

0x02 MOV R1 R0 0 1 1 0 0 1 0 0 100

0x03 RHI #0 1 1 0 0 0 0 0 0 192

0x04 MOV R2 R0 0 1 1 0 1 0 0 0 104

0x05 MOV R3 R0 0 1 1 0 1 1 0 0 108

0x06 ADDI R3 #2 1 0 0 1 1 1 1 0 158

0x07 ST R3 R2 1 0 0 0 1 1 1 0 142

0x08 ADDI R2 #1 1 0 0 1 1 0 0 1 153

0x09 SUBI R1 #1 1 0 1 0 0 1 0 1 165

0x0A NOP 0 0 0 0 0 0 0 0 0

0x0B BNZ #-6 1 1 1 0 1 0 1 0 234

0x0C NOP 0 0 0 0 0 0 0 0 0

0x0D RHI #0 1 1 0 0 0 0 0 0 192

0x0E RLI #4 1 0 1 1 0 1 0 0 180

0x0F MOV R1 R0 0 1 1 0 0 1 0 0 100

0x10 RHI #0 1 1 0 0 0 0 0 0 192

0x11 MOV R2 R0 0 1 1 0 1 0 0 0 104

0x12 LD R3 R2 0 1 1 1 1 1 1 0 126

0x13 ADD R0 R3 0 0 0 1 0 0 1 1 19

0x14 ADDI R0 #1 1 0 0 1 0 0 0 1 1450x15 SUBI R1 #1 1 0 1 0 0 1 0 1 165

0x16 NOP 0 0 0 0 0 0 0 0 0

0x17 BNZ #-6 1 1 1 0 1 0 1 0 234

0x18 NOP 0 0 0 0 0 0 0 0 0

0x19 MOV R3 R0 0 1 1 0 1 1 0 0 108

0x1A RHI #0 1 1 0 0 0 0 0 0 192

0x1B RLI #4 1 0 1 1 0 1 0 0 180

0x1C ST R3 R0 1 0 0 0 1 1 0 0 140

0x1D NOP 0 0 0 0 0 0 0 0 0

2. Instruction Memory

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16 Simulation Result

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17 Result Analysis

1. Programming Analysis

Addr Instruction R0 R1counter

R2memory

address

R3result data

Data Memory

00 RHI 0 00000000

01 RLI 4 00000100

02 MOV R1,R0 00000100

03 RHI 0 00000000

04 MOV R2,R0 00000000

05 MOV R3,R0 00000000

06 ADDI R3,2 0+2=22+2=44+2=66+2=8

07 ST R3,R2 M[0]=2M[1]=4M[2]=6M[3]=8

08 ADDI R2,1 0+1=11+1=22+1=33+1=4

09 SUBI R1,1 4-1=33-1=22-1=11-1=0 =zero

0A NOP

0B BNZ -6

0C NOP

0D RHI 0 00000000

0E RLI 4 00000100

0F MOV R1,R0 00000100

10 RHI 0 00000000

11 MOV R2,R0 00000000

12 LD R3,R2 2222

13 ADD R0,R3 2+0=23+2=56+2=89+2=11

14 ADDI R0,1 2+1=35+1=68+1=911+1=12

15 SUBI R1,1 4-1=33-1=22-1=1

1-1=0 zero16 NOP

17 BNZ -6

18 NOP

19 MOV R3,R0 12

1A RHI 0 00000000

1B RLI 4 00000100

1C ST R3,R0 M[4]=12

1D NOP

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2. Data Memory (Final data stored in DM)

18 Timing AnalysisThe maximum frequency could be performed by this processor is 57.05 MHz and in the running

program, the frequency is used is 50 Mhz. The critical path comes from Present State Register in CU

to Status Register in DU as shown below.

19 Resource UtilizationThe total logic element used is 185 and the total number register used is 54. The number of

memory bit used is 4096. The summary of the compilation is shown below. Here is how the total

number of register used and memory bit used are defined:

Number of Register Used : RF + PC + IR + SR + NS = ( 4 x 8 ) + 8 + 8 + 1 + 5 = 54

Number memory bit used: (256x8 for IM) + (256 x 8 for DM) = 2 x (256 x 8) = 4096

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20 Conclusion

A RISC processor has been designed, synthesized, validated and working correctly as expected byrunning the test pattern. The final result is validated by observing the final data stored data in data

memory as well as in the register files. For further study, the performance of this RISC processor

can be improved by implementing the 5-state pipeline mechanism as shown on figure below which

is based on MIPS architecture.

Furthermore, since the jump type instruction is only can jump in range from -8 to +7, the datapath

unit design have to redesign on order that the jump type instruction can jump from -128 to +127 by

storing the k immediate value into register file first and then supply to program counter with adding

one stack pointer if the ‘return’ instruction is needed as shown in the datapath below.

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21 References1. Dr Mohamed Khalil Hani, Starter’s Guide to Digital Systems VHDL & Verilog Design , Revised

Edition 2, July 2010, Desktop Publisher.

2. Stephen Brown & Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design ,

Second Edition, 2003, McGraw Hill.

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