n 301 von neumann architecture

7/23/2019 n 301 Von Neumann Architecture

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CSCI N301:CSCI N301:Fundamental ComputerFundamental Computer

Science ConceptsScience Concepts

CopyrightCopyright 20042004 Department of Computer & Information ScienceDepartment of Computer & Information Science

Von Neumann ArchitectureVon Neumann Architecture


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N301: Fundamenta Computer Science Concept!N301: Fundamenta Computer Science Concept!


GoalsGoals

Understand how the von NeumannUnderstand how the von Neumann

architecture is constructed.architecture is constructed.

Understand how the von NeumannUnderstand how the von Neumannarchitecture works.architecture works.

Understand how to program in basic aUnderstand how to program in basic a

assembly language.assembly language.


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Where Are We?Where Are We?

We have spent several weeks now, building ourWe have spent several weeks now, building our

understanding o computer organi!ation.understanding o computer organi!ation.

We started with transistors, moved up a level toWe started with transistors, moved up a level to

gates, and then up a level to circuits.gates, and then up a level to circuits. "ur ne#t step is a key one$ we will combine"ur ne#t step is a key one$ we will combine

circuits together to build unctional units ocircuits together to build unctional units o

computer operation.computer operation.


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%adder o Abstraction%adder o Abstraction

&t is worth reminding ourselves how we got here$&t is worth reminding ourselves how we got here$' (limbing up the ladder o abstraction, the process is(limbing up the ladder o abstraction, the process is

to take the unctional units o one level, combineto take the unctional units o one level, combinethem, and move this combined unit to the ne#t unit othem, and move this combined unit to the ne#t unit oabstractionabstraction

' As we move to this new level, the level o sub)As we move to this new level, the level o sub)components, we need to remember that this level iscomponents, we need to remember that this level isbuilt rom the components o previous levelsbuilt rom the components o previous levels


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*ub)(omponents*ub)(omponents

At the onset, computers re+uired hardwareAt the onset, computers re+uired hardwarechanges to work on new problems somechanges to work on new problems somehistorians say that this early stage ohistorians say that this early stage o-programming was wiring.-programming was wiring.

(learly, re+uiring hardware changes with each(learly, re+uiring hardware changes with eachnew programming operation was time)new programming operation was time)consuming, error)prone, and costlyconsuming, error)prone, and costly

& you recall rom the movie& you recall rom the movie The Machine ThatThe Machine ThatChanged the WorldChanged the World, one o the key contributors to, one o the key contributors tocomputer evolution was /ohn von Neumanncomputer evolution was /ohn von Neumann


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0he *tored 1rogram (oncept0he *tored 1rogram (oncept

Von Neumann2s proposal was to store the programVon Neumann2s proposal was to store the program

instructions right along with the datainstructions right along with the data

0his may sound trivial, but it represented a proound0his may sound trivial, but it represented a proound

paradigm shitparadigm shit

0he stored program concept was proposed about ity0he stored program concept was proposed about ity

years ago to this day,years ago to this day, it is theit is the fundamentalfundamentalarchitecturearchitecture

that fuels computers.that fuels computers.

0hink about how ama!ing that is, given the short shel0hink about how ama!ing that is, given the short shel

lie o computer products and technologies3lie o computer products and technologies3


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0he *tored 1rogram (oncept and its0he *tored 1rogram (oncept and its

&mplications&mplications

0he *tored 1rogram concept had several0he *tored 1rogram concept had several

technical ramiications$technical ramiications$

' 4our key sub)components operate together to make4our key sub)components operate together to make

the stored program concept workthe stored program concept work' 0he process that moves inormation through the sub)0he process that moves inormation through the sub)

components is called the -etch e#ecute cyclecomponents is called the -etch e#ecute cycle

' Unless otherwise indicated, program instructions areUnless otherwise indicated, program instructions are

e#ecuted in se+uential ordere#ecuted in se+uential order


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4our *ub)(omponents4our *ub)(omponents

0here are our sub)components in von Neumann0here are our sub)components in von Neumann

architecture$architecture$

' 5emory5emory

' &nput6"utput 7called -&"8&nput6"utput 7called -&"8

' Arithmetic)%ogic UnitArithmetic)%ogic Unit

' (ontrol Unit(ontrol Unit

While only 9 sub)components are called out, there is a :While only 9 sub)components are called out, there is a : thth,,

key player in this operation$ a bus, or wire, that connectskey player in this operation$ a bus, or wire, that connects

the components together and over which data lows romthe components together and over which data lows romone sub)component to anotherone sub)component to another

%et2s look at each sub)component in more detail 3%et2s look at each sub)component in more detail 3


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5emory5emory

As you already know, there are severalAs you already know, there are several

dierent lavors o memorydierent lavors o memory

Why isn2t ;ust one kind used?Why isn2t ;ust one kind used?


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5emory 0ypes$ =A55emory 0ypes$ =A5

=A5 is typically volatile memory 7meaning it doesn2t=A5 is typically volatile memory 7meaning it doesn2tretain voltage settings once power is removed8retain voltage settings once power is removed8

=A5 is an array o cells, each with a uni+ue address=A5 is an array o cells, each with a uni+ue address

A cell is the minimum unit o access. "riginally, this wasA cell is the minimum unit o access. "riginally, this was> bits taken together as a byte. &n today2s computer,> bits taken together as a byte. &n today2s computer,word)si!ed cells 7@ bits, grouped in 98 are more typical.word)si!ed cells 7@ bits, grouped in 98 are more typical.

=A5 gets its name rom its access perormance. &n =A5=A5 gets its name rom its access perormance. &n =A5memory, theoretically, it would take the same amount omemory, theoretically, it would take the same amount o

time to access any memory cell, regardless o itstime to access any memory cell, regardless o itslocation with the memory bank 7-random access8.location with the memory bank 7-random access8.


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5emory 0ypes$ ="55emory 0ypes$ ="5

&t gets its name rom its cell)protection eature.&t gets its name rom its cell)protection eature.0his type o memory cell can be read rom, but0his type o memory cell can be read rom, butnot written to.not written to.

Unlike =A5, ="5 is non)volatile it retains itsUnlike =A5, ="5 is non)volatile it retains itssettings ater power is removed.settings ater power is removed.

="5 is more e#pensive than =A5, and to="5 is more e#pensive than =A5, and toprotect this investment, you only store criticalprotect this investment, you only store critical

inormation in ="5 3inormation in ="5 3


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5emory 0ypes$ =egisters5emory 0ypes$ =egisters

0here is a third, key type o memory in0here is a third, key type o memory inevery computer ' registers.every computer ' registers.

=egister cells are powerul, costly, and=egister cells are powerul, costly, and

physically located close to the heart ophysically located close to the heart ocomputing.computing.

We will see later that among the registers,We will see later that among the registers,

several o them are the main participantsseveral o them are the main participantsin the etch e#ecute cycle.in the etch e#ecute cycle.


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5emory 0ypes$ "ther5emory 0ypes$ "ther

5odern computers include other orms o5odern computers include other orms omemory, such as cache memory.memory, such as cache memory.

=emember, memory types e#ist at dierent trade=emember, memory types e#ist at dierent trade

os.os. 0he study o memory organi!ations and access0he study o memory organi!ations and access

schemes is an innovative one within (omputerschemes is an innovative one within (omputer*cience. &n your lie time, you should e#pect to*cience. &n your lie time, you should e#pect to

see numerous innovations in memory types andsee numerous innovations in memory types andcapabilities.capabilities.


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What2s Up with 5emoryWhat2s Up with 5emory

=egardless o the type o memory, several concepts=egardless o the type o memory, several concepts

apply in this key component.apply in this key component.

(ell si!e or cell width$ a key concept within memory is(ell si!e or cell width$ a key concept within memory is

how many individual memory cells 7which we now knowhow many individual memory cells 7which we now know

are switches8 are addressed at a time.are switches8 are addressed at a time.

At a minimum, this is a byte 7> bits8 in today2sAt a minimum, this is a byte 7> bits8 in today2s

computers, but to support all data types and operations,computers, but to support all data types and operations,

cell si!e can be larger 7a word, or instance, at @ bits8.cell si!e can be larger 7a word, or instance, at @ bits8.


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(ell address and contents$ another key concept(ell address and contents$ another key concept

is to recogni!e that all cells have an address,is to recogni!e that all cells have an address,

and can contain data contents.and can contain data contents.

0he cell address is a label 7like a !ip code8 that0he cell address is a label 7like a !ip code8 thatidentiies a particular cell.identiies a particular cell.

0he cell contents are whatever data is stored at0he cell contents are whatever data is stored at

a given address location.a given address location.


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0wo other key concepts in the study o memory0wo other key concepts in the study o memory

are memory si!e and address space.are memory si!e and address space.

5emory si!e reers to the number o5emory si!e reers to the number o

addressable cells ' how many dierent memoryaddressable cells ' how many dierent memorylocations a computer has.locations a computer has.

Address space reers to the range oAddress space reers to the range o

addressable cell labels. (ell labels begin with theaddressable cell labels. (ell labels begin with the

number B. *o, i you had a computer with Cnumber B. *o, i you had a computer with Cnn

memory si!e, its address space would be Cmemory si!e, its address space would be Cnn).).


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Don2t orget that the memory labels areDon2t orget that the memory labels are

themselves binary numbersthemselves binary numbers

"ne o the special registers we talked about"ne o the special registers we talked about

earlier is a register whose ;ob it is to holdearlier is a register whose ;ob it is to holdaddress locations.address locations.


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0he special register is called the 5A= ' the0he special register is called the 5A= ' the

machine address registermachine address register..

4or a machine with C4or a machine with Cnnaddress cells, the 5A=address cells, the 5A=

must be able to hold a number Cmust be able to hold a number Cnn) big.) big.


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5emory "perations5emory "perations

0wo basic operations occur within this0wo basic operations occur within thissubcomponent$ asubcomponent$ a fetch operationfetch operation, and a, and a storestore..

0he etch operation$0he etch operation$' A cell address is loaded into the 5A=.A cell address is loaded into the 5A=.' 0he address is decoded, which means that thru0he address is decoded, which means that thru

circuitry, a speciic cell is located.circuitry, a speciic cell is located.' 0he data contents contained within that cell is copied0he data contents contained within that cell is copied

into another special register, called ainto another special register, called a Machine DataMachine Data

Register (MDR)Register (MDR)

.

.' Note that this operation is non)destructive ' that is,Note that this operation is non)destructive ' that is,

the data contents are copied, but not destroyed.the data contents are copied, but not destroyed.


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5emory "perations5emory "perations

0he second memory operation is called a0he second memory operation is called a storestore..' 0he etch is like a read operation the store is like a0he etch is like a read operation the store is like a

write operationwrite operation' &n the store, the address o the cell into which data is&n the store, the address o the cell into which data is

going to be stored is moved to the 5A= and decoded.going to be stored is moved to the 5A= and decoded.' (ontents rom yet another special register, called an(ontents rom yet another special register, called an

accumulatoraccumulator, are copied into the cell location 7held in, are copied into the cell location 7held inthe 5A=8.the 5A=8.

' 0his operation is destructive, meaning that whatever0his operation is destructive, meaning that whatever

data was originally contained at that memory locationdata was originally contained at that memory locationis overwritten by the value copied rom theis overwritten by the value copied rom theaccumulator.accumulator.


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&6"$ &nput and "utput&6"$ &nput and "utput

0here is both a human)machine interace and a0here is both a human)machine interace and a

machine)machine interace to &6".machine)machine interace to &6".

'


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0he A%U0he A%U

0he third component in the von Neumann0he third component in the von Neumann

architecture is called the Arithmetic %ogic Unit.architecture is called the Arithmetic %ogic Unit.

0his is the subcomponent that perorms the0his is the subcomponent that perorms the

arithmetic and logic operations or which wearithmetic and logic operations or which wehave been building parts.have been building parts.

0he A%U is the -brain o the computer.0he A%U is the -brain o the computer.


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0he A%U0he A%U

&t houses the special memory locations, called&t houses the special memory locations, called

registers, o which we have already considered.registers, o which we have already considered.

0he A%U is important enough that we will come0he A%U is important enough that we will come

back to it later, 4or now, ;ust reali!e that itback to it later, 4or now, ;ust reali!e that itcontains the circuitry to perorm addition,contains the circuitry to perorm addition,

subtraction,multiplication and division, as well assubtraction,multiplication and division, as well as

logical comparisons 7less than, e+ual to andlogical comparisons 7less than, e+ual to and

greater than8.greater than8.


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(ontrol Unit(ontrol Unit

0he last o the our subcomponents is the (ontrol Unit.0he last o the our subcomponents is the (ontrol Unit.

0he control unit is the work horse that drives the etch0he control unit is the work horse that drives the etchand e#ecute cycle.and e#ecute cycle.

=emember we said that in memory, a cell address is=emember we said that in memory, a cell address is

loaded into the 5A= ' it is the control unit that iguresloaded into the 5A= ' it is the control unit that iguresout which address is loaded, and what operation is to beout which address is loaded, and what operation is to beperormed with the data moved to the 5D=.perormed with the data moved to the 5D=.

We will come back and look in detail at how the (ontrolWe will come back and look in detail at how the (ontrol

Unit perorms this task.Unit perorms this task.


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*tored 1rogram (oncept*tored 1rogram (oncept

We saw that it was von Neumann2sWe saw that it was von Neumann2s

organi!ational scheme that was adopted inorgani!ational scheme that was adopted in

computer architecture.computer architecture.

0his architecture was largely driven by the0his architecture was largely driven by thedecision to store program code along with data.decision to store program code along with data.

"nce this decision was made, several by)"nce this decision was made, several by)

product engineering re+uirements emerged.product engineering re+uirements emerged.


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(hoosing a 5emory %ocation(hoosing a 5emory %ocation

%et2s tackle the initial re+uirement irst$ how do we%et2s tackle the initial re+uirement irst$ how do wedetermine which address location holds the data ondetermine which address location holds the data onwhich we need to operate.which we need to operate.

=emember we said that there is a special register,=emember we said that there is a special register,called the 5A= that holds an address )) a binarycalled the 5A= that holds an address )) a binarynumber.number.

We need some circuitry to read that number, andWe need some circuitry to read that number, andbased on its value, ind e#actly the correct addressbased on its value, ind e#actly the correct address

location to read.location to read. 0he circuit is called a decoder 30he circuit is called a decoder 3


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Decoder (ircuitsDecoder (ircuits

0he 5A= is connected to a decoder0he 5A= is connected to a decoder

circuit.circuit.

0his circuitry will identiy the correct0his circuitry will identiy the correct

memory cell.memory cell.

%et2s igure out how this works 3%et2s igure out how this works 3


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Decoder (ircuitsDecoder (ircuits

&nitially, think about the decoder circuit as&nitially, think about the decoder circuit as

a black bo#.a black bo#.

Foing into the black bo# are N input lines,Foing into the black bo# are N input lines,

7which emerge rom the 5A=8.7which emerge rom the 5A=8.

Foing out o the black bo# are CFoing out o the black bo# are Cnn outputoutput

lines 7with each output line connecting to alines 7with each output line connecting to a

speciic memory cell in =A58.speciic memory cell in =A58.


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Decoder (ircuit$ An


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4irst, the 1roblem *tatement4irst, the 1roblem *tatement

Design a circuit with C input lines 7a, b8Design a circuit with C input lines 7a, b8

and 9 output lines 7dand 9 output lines 7dBB,d,d??,d,dCC,d,dHH88

0he output lines are uni+uely high i and0he output lines are uni+uely high i and

only i the ollowing conditions are met$only i the ollowing conditions are met$' ddBB is high &44 both inputs are lowis high &44 both inputs are low

' ddis high &44 a is low and b is highis high &44 a is low and b is high

'ddCCis high &44 a is high and b is lowis high &44 a is high and b is low

' ddHHis high &44 both a and b are highis high &44 both a and b are high


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Ne#t, the 0ruth 0ableNe#t, the 0ruth 0able

INPUT LINESINPUT LINES OUPUT LINESOUPUT LINES

aa bb dd00

dd11

dd22

dd33

00 00 11 00 00 00

00 11 00 11 00 00

11 00 00 00 11 00

11 11 00 00 00 11


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Ne#t, the Eoolean *ub)


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(ircuit Diagram ' Decoder (ircuit(ircuit Diagram ' Decoder (ircuit

aa bb

dd00

dd11

dd22

dd33

To

theMDR

To

theMDR

To

theMDR

To

theMDR

MARMARMARMAR


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Decoder (ircuit


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(ircuit Diagram ' Decoder (ircuit(ircuit Diagram ' Decoder (ircuit

aa bb

dd00

dd11

dd22

dd33

61616161

MARMARMARMAR


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9 J @ decoder9 J @ decoder


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*caling &ssue*caling &ssue

We have built a viable decoder circuit, and illustratedWe have built a viable decoder circuit, and illustratedhow this control circuit could perorm in translatinghow this control circuit could perorm in translatingbetween the address label contained in the 5A= andbetween the address label contained in the 5A= andobtaining contents o the reerenced location.obtaining contents o the reerenced location.

At some point, however, the model isn2t scaleable ' tooAt some point, however, the model isn2t scaleable ' toomuch space re+uired or a linear layout.much space re+uired or a linear layout.

(omputers utili!e a C)dimensional approach in decoder(omputers utili!e a C)dimensional approach in decoderoperation, using a row6column 5A= addressing schemeoperation, using a row6column 5A= addressing schemeto identiy speciic address locations.to identiy speciic address locations.

A C)D grid is illustrated on the ne#t slide 3A C)D grid is illustrated on the ne#t slide 3


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C)D 5emoryC)D 5emory AccessAccess


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C)D 5emory "perationC)D 5emory "peration


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"ne 1roblem *olved"ne 1roblem *olved

Well, we have igured out how to useWell, we have igured out how to use

circuitry to decode the contents o thecircuitry to decode the contents o the

5A= to identiy a speciic memory5A= to identiy a speciic memory

location.location.

We still need to igure out how to interpretWe still need to igure out how to interpret

the results o the A%U circuitry to load athe results o the A%U circuitry to load a

correct process answer into the 5D=.correct process answer into the 5D=.


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5ultiple#or (ircuits5ultiple#or (ircuits

=emember, we said that the A%U actually=emember, we said that the A%U actually

perorms all operational processing on C givenperorms all operational processing on C given

inputs.inputs.

0hus, i the inputs are 9 and C, calculations or 90hus, i the inputs are 9 and C, calculations or 9K C, 9 J C, 9)C, 9 LG C, etc. are all perormed inK C, 9 J C, 9)C, 9 LG C, etc. are all perormed in

parallel.parallel.

What we need to be able to do is to select theWhat we need to be able to do is to select the

correct answer rom among all those calculated.correct answer rom among all those calculated.


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5ultiple#or (ircuits5ultiple#or (ircuits

A multiple#or is a circuit with CA multiple#or is a circuit with Cnninput linesinput lines

and output line.and output line.

0he unction is serves is to select e#actly0he unction is serves is to select e#actly

one o its input lines and copy the binaryone o its input lines and copy the binary

value on that input line to its single outputvalue on that input line to its single output

line.line.


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5ultiple#or 5agic5ultiple#or 5agic

0he multiple#or chooses the correct input line to pass thru to0he multiple#or chooses the correct input line to pass thru to

the output line by using a second set o N lines called selectorthe output line by using a second set o N lines called selector

lines.lines.

*o, the total number o input lines in a multiple#or are C*o, the total number o input lines in a multiple#or are Cnn K N.K N.

0he irst set o input lines are numbered rom B to C0he irst set o input lines are numbered rom B to Cnn), while), whilethe selector lines are numbered rom B to N, such that there isthe selector lines are numbered rom B to N, such that there is

e#actly one selector line or each input line.e#actly one selector line or each input line.


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CopyrightCopyright

20042004

Department of Computer & Information ScienceDepartment of Computer & Information Science

5ultiple#or (ircuit5ultiple#or (ircuit


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CopyrightCopyright

20042004


Where We2ve EeenWhere We2ve Eeen

We have been touring the von NeumannWe have been touring the von Neumann

architecture o 9 sub)components.architecture o 9 sub)components.

We have igured out how to build the appropriateWe have igured out how to build the appropriate

circuitry to perorm arithmetic and logiccircuitry to perorm arithmetic and logicoperations on the data contained at speciicoperations on the data contained at speciic

memory locations.memory locations.

What we don2t know how to do is to igure outWhat we don2t know how to do is to igure out

which arithmetic or logic operations need to bewhich arithmetic or logic operations need to be

perormed and in what order.perormed and in what order.


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CopyrightCopyright

20042004


0he (ontrol Unit0he (ontrol Unit

0he mastermind behind these inal pieces o our0he mastermind behind these inal pieces o our

operational model is the (ontrol Unitoperational model is the (ontrol Unit

&t is the (ontrol Unit that uels the stored&t is the (ontrol Unit that uels the stored

program conceptprogram concept 0o do its ;ob, the (ontrol Unit has several tools0o do its ;ob, the (ontrol Unit has several tools

' *pecial memory registers*pecial memory registers

' --Wired understanding o an &nstruction *etWired understanding o an &nstruction *et


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CopyrightCopyright

20042004


0oolset0oolset

%et2s look at the toolset irst, and then how it is%et2s look at the toolset irst, and then how it is

deployeddeployed

*pecial 5emory =egisters*pecial 5emory =egisters

' 0he (ontrol Unit must keep track o where it is within0he (ontrol Unit must keep track o where it is withina program, and what it should do ne#ta program, and what it should do ne#t

' 0wo special registers are used to accomplish this$0wo special registers are used to accomplish this$

A program counter, typically reerred to as a 1(, holds theA program counter, typically reerred to as a 1(, holds the

address o the N


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N301: Fundamenta Computer Science Concept!N301: Fundamenta Computer Science Concept!CopyrightCopyright 20042004 Department of Computer & Information ScienceDepartment of Computer & Information Science

0oolset 70wo80oolset 70wo8

Along with the special registers, theAlong with the special registers, the

(ontrol Unit utili!es special circuitry, called(ontrol Unit utili!es special circuitry, called

an instruction decoderan instruction decoder

0he instruction decoder is a typical0he instruction decoder is a typical

decoder circuit, and its purpose is to readdecoder circuit, and its purpose is to read

an instruction rom the &=, and activate thean instruction rom the &=, and activate the

appropriate circuit lineappropriate circuit line


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ow this Worksow this Works

=emember, we are trying to igure out how=emember, we are trying to igure out howthe stored program concept works.the stored program concept works.

&n this model, the program and the data&n this model, the program and the data

upon which it operates are stored inupon which it operates are stored inmemory locations.memory locations.

We know how to encode the data.We know how to encode the data.

We need to learn how to encode theWe need to learn how to encode theprogramming instructions.programming instructions.


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0he &nstruction *et0he &nstruction *et

At the heart o all programming are a ew,At the heart o all programming are a ew,

building block instructions.building block instructions.

0he set o instructions is remarkably small, and0he set o instructions is remarkably small, and

particular to a given processor.particular to a given processor. 0he power o the instruction set is that by0he power o the instruction set is that by

identiying a deinite, bounded, simple task, anidentiying a deinite, bounded, simple task, an

instruction can be e#ecuted with appreciableinstruction can be e#ecuted with appreciable

speed ' typically within a ew billionths o aspeed ' typically within a ew billionths o asecond.second.


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&n Einary 7" (ourse8&n Einary 7" (ourse8

0he instruction set is something like the0he instruction set is something like the

A*(&& alphabet encoding scheme.A*(&& alphabet encoding scheme.

0he speciic instructions are given uni+ue0he speciic instructions are given uni+ue

binary codes.binary codes.

"bviously, the &= must be big enough to"bviously, the &= must be big enough to

hold any instruction within the numberedhold any instruction within the numbered

set.set.


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*ample &nstructions*ample &nstructions

&nstructions all into several main categories$ data transer,&nstructions all into several main categories$ data transer,arithmetic, comparisons, and branchingarithmetic, comparisons, and branching

*ome typical instructions might include$*ome typical instructions might include$

' %oad%oad

' *toreh*toreh

' 5ove5ove

' AddAdd

' (ompare(ompare

' EranchEranch

' altalt


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*ample &nstruction 4ormat*ample &nstruction 4ormat

0he ormat o a typical instruction is in0he ormat o a typical instruction is in

machine code, and looks something likemachine code, and looks something like

this$this$

"peration"peration(ode(ode

AddressAddress4ield 4ield

AddressAddress4ield C4ield C


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&nterpreting an &nstruction&nterpreting an &nstruction

&magine a machine with an instruction set&magine a machine with an instruction set

o > individual instructions, numbered romo > individual instructions, numbered rom

BBB to .BBB to .

"ur &= would need to be H bits big."ur &= would need to be H bits big.

5ore realistically, a modern pc today is5ore realistically, a modern pc today is

likely to have HB):B instructions,but we willlikely to have HB):B instructions,but we will

keep our model simple.keep our model simple.


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0ypical &nstructions0ypical &nstructions

&magine the ollowing instruction&magine the ollowing instruction

' BB BBB BBBB BBB BB

%et2s say the BB means to perorm an ADD operation.%et2s say the BB means to perorm an ADD operation.

0he BBB would reer to the address location o the irst0he BBB would reer to the address location o the irst

data element to be added.data element to be added.

0he BB would reer to the address location o the0he BB would reer to the address location o the

second data element to be added.second data element to be added.

*o3 this instruction would mean$ Add the contents o*o3 this instruction would mean$ Add the contents o

address location BBB to BB.address location BBB to BB.


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4ollowing the 4etch


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4etch, Decode,


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1hase "ne$ 4etch1hase "ne$ 4etch

0he (ontrol Unit gets the ne#t instruction rom0he (ontrol Unit gets the ne#t instruction rommemory and moves it into the &nstruction =egistermemory and moves it into the &nstruction =egister7&=87&=8

0his is accomplished by the ollowing steps$0his is accomplished by the ollowing steps$

' 0he address in the 1rogram (ounter 71(8 is moved to the0he address in the 1rogram (ounter 71(8 is moved to the5A=5A=

' A etch is initiated, which brings the contents o the cellA etch is initiated, which brings the contents o the cellreerenced by the 1( to the 5D=reerenced by the 1( to the 5D=

' 5ove the instruction rom the 5D= to the &nstruction5ove the instruction rom the 5D= to the &nstruction=egister 7&=8 or decoding=egister 7&=8 or decoding

' &ncrement the 1( to point to the ne#t instruction&ncrement the 1( to point to the ne#t instruction


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1hase 0wo$ Decode1hase 0wo$ Decode

0he operation code portion o the contents0he operation code portion o the contents

o the instruction register is read rom theo the instruction register is read rom the

&=&=

0he binary number is ed to a decoder0he binary number is ed to a decoder

circuit, which activates the appropriatecircuit, which activates the appropriate

circuitry or the operationcircuitry or the operation


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1hase 0hree$


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(ompleting a 1rogram(ompleting a 1rogram

When one instruction has been e#ecuted, theWhen one instruction has been e#ecuted, the

etch e#ecute cycle moves to the ne#t addressetch e#ecute cycle moves to the ne#t address

&t can do this because the 1( was incremented&t can do this because the 1( was incremented

to relect the address location o the ne#tto relect the address location o the ne#te#ecutable addresse#ecutable address

&n this way, a series o machine level instructions&n this way, a series o machine level instructions

can be e#ecuted, one at a timecan be e#ecuted, one at a time


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Why Not Ouit ere?Why Not Ouit ere?

We could, actuallyWe could, actually

0he process we ;ust outlined is a airly0he process we ;ust outlined is a airly

accurate description o how earlyaccurate description o how early

programming occurredprogramming occurred

1rogrammers wrote lines o code that1rogrammers wrote lines o code that

looked something like this$looked something like this$

' BB BBB BBBBB BBB BBB


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0oo


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Ouestions?Ouestions?

n 301 von neumann architecture

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