nand flash architecture and specification trends

18
NAND Flash Architecture and Specification Trends Michael Abraham ([email protected]) Applications Engineering Manager Micron Technology, Inc. Santa Clara, CA USA August 2009 1

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Page 1: NAND Flash Architecture and Specification Trends

NAND Flash Architecture and Specification Trends

Michael Abraham ([email protected])Applications Engineering ManagerMicron Technology, Inc.

Santa Clara, CA USAAugust 2009 1

Page 2: NAND Flash Architecture and Specification Trends

Abstract

As NAND Flash continues to shrink, page sizes, block sizes, and ECC requirements are increasing while data retention, endurance, and performance are decreasingperformance are decreasing.These changes impact systems including random write performance and more.Learn how to prepare for these changes andLearn how to prepare for these changes and counteract some of them through improved block management techniques and system design.This presentation also discusses some of theThis presentation also discusses some of the tradeoff myths – for example, the myth that you can directly trade ECC for endurance

Santa Clara, CA USAAugust 2009 2

Page 3: NAND Flash Architecture and Specification Trends

NAND Flash:NAND Flash:Shrinking Faster Than Moore’s Law

200

100

80

ion

(nm

)

Logic

DRAM

60

40

Reso

luti

NAND

40Micron 32Gb NAND

(34nm)

Santa Clara, CA USAAugust 2009 3

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Semiconductor International, 1/1/2007

Page 4: NAND Flash Architecture and Specification Trends

Memory Organization TrendsOver time, NAND block size is increasing.g• Larger page sizes increase sequential throughput.• More pages per block reduce die size.

4,194,304

65,536

262,144

1,048,576

1 024

4,096

16,384

,

16

64

256

1,024

Santa Clara, CA USAAugust 2009 4

16

Block size (B) Data Bytes per Page Pages per Block

Page 5: NAND Flash Architecture and Specification Trends

Consumer-grade NAND Flash:Consumer-grade NAND Flash: Endurance and ECC Trends

Process shrinks lead to less electrons per floating gate.p g gECC used to improve data retention and endurance.To adjust for increasing RBERs, ECC is increasing exponentially to achieve equivalent UBERs.For consumer applications, endurance becomes less important as density increases.

30

20

25

30100,000

s)Cyc

les)

10

1510,000

ECC

(bits

ndur

ance

(C

0

5

1,0002005 Future

En

Santa Clara, CA USAAugust 2009 5

SLC Endurance MLC-2 Endurance MLC-2 ECC SLC ECC

Page 6: NAND Flash Architecture and Specification Trends

Myth: More ECC Extends BlockMyth: More ECC Extends Block Endurance

Block endurance is how long a block is usable before program or erase status failures occur.Applying more ECC than required does not pp y g qautomatically extend the block endurance.NAND devices are configured to trigger program and erase status failures for a specific, fixed ECC value ppredetermined at the factory to meet qualification requirements.Applying extra ECC does not change these

d t i d th h ld hi h th tpredetermined thresholds, which means that program and erase status failures begin to occur at the same cycling intervals regardless of the amount of ECC appliedapplied.

Santa Clara, CA USAAugust 2009 6

Page 7: NAND Flash Architecture and Specification Trends

Larger Page Sizes ImproveLarger Page Sizes Improve Sequential Write Performance

For a fixed page size write throughput decreases asFor a fixed page size, write throughput decreases as NAND process shrinksNAND vendors increase the page size to compensate for slowing array performancefor slowing array performanceWrite throughput decreases with more bits per cell

80

20

40

60 SLCSLC MLC-2MLC-2 MLC-3MLC-3

0512 2048 4096 8192 2048 4096 8192 4096 8192

Data Bytes per Page

Santa Clara, CA USAAugust 2009 7

Sequential Programming Throughput (MB/s)

Page 8: NAND Flash Architecture and Specification Trends

More Pages Per Block Affect Random Write PerformanceRandom Write Performance

The block copy time is the largest limiting factor for random write performance.As block copy time increases random performance decreasesAs block copy time increases, random performance decreases.• Number of pages per block is the dominant factor.• Increase of tPROG is the next largest factor.• Increase in I/O transfer time due to increasing page size (effect not shown below)

is also a factor.Some card interfaces have write timeout specs at 250ms, which means that block management algorithms manage partial blocks.

400500 SLCSLC MLCMLC--22 MLCMLC--33

100200300400

032 / 30064 / 25064 / 300128 / 250 128 / 600128 / 900256 / 900 256 /

1200192 /

2000+

Pages per Block & tPROG (typ)

Santa Clara, CA USAAugust 2009 8

g p ( yp)

Block Copy Time (ms)

Page 9: NAND Flash Architecture and Specification Trends

NAND Interface

The NAND interface is increasing in throughput

All b tt tili ti f I/O h l hi h• Allows better utilization of I/O channels – higher bandwidth

• Immediately useful for single die read y gperformance

• Modest improvement for write performance with multiple diemultiple die

Important for SSDs, enterprise applications• Reduces I/O channels

Santa Clara, CA USAAugust 2009 9

Page 10: NAND Flash Architecture and Specification Trends

NAND Interface Trends

Interface Standard (x8)Max Throughput

(MB/s)N t d d 40No standard 40ONFI 1.0 Async (12/06) 50ONFI 2 0 Sync (2/08) 133ONFI 2.0 Sync (2/08) 133ONFI 2.1-2.2 Sync (1/09, 9/09) 200Toggle Mode (not published) 133Toggle Mode (not published) 133ONFI 3.0 Sync 400

Page 11: NAND Flash Architecture and Specification Trends

Th ONFI Ad tThe ONFI AdvantageSingle Channel Package Dual Channel Package

Supports simultaneous read, program, and erase operations on multiple die on the same chip enable since ONFI 1.0

Target800

700

800

900

Only industry-standard NAND interface capable of 200MB/sec data rate from a single dieT o independent channels in a

Target400400

500

600

B/s

Two independent channels in a single package (doubles the bandwidth)In volume production today167

200

400

333

400

200

300

400MB

Headroom for 400MB/sec and beyondWork has already begun on ONFI 3 0

40

167

80

0

100

200

ONFi 1 0 ONFi 2 0 ONFi 2 1 ONFi 3 0 3.0

Santa Clara, CA USAAugust 2009 11

SynchronousAsyncONFi 1.0 ONFi 2.0 ONFi 2.1 ONFi 3.0

Page 12: NAND Flash Architecture and Specification Trends

A-Data Afa Technologies Alcor MicroAleph One Anobit Tech ApacerAleph One Anobit Tech. ApacerArasan Chip Systems ASMedia Technology ATIAvid Electronics BitMicro Biwin TechnologyChipsbank Cypress DataFab SystemsData I/O Datalight Denali SoftwareENE Technology Entorian FCI

Members

ENE Technology Entorian FCIFormFactor Foxconn Fresco LogicFusion Media Tech Genesys Logic Hagiwara Sys-ComHiperSem Hitachi GST HyperstoneInCOMM Indilinx InphiIntelliprop ITE Tech Jinvani SystechKingston Technology Lauron Technologies LotesLSI Macronix MarvellMentor Graphics Metaram Moai ElectronicsMolex NVidia Orient SemiconductorP.A. Semi Powerchip Semi. Power Quotient InternationalProlific Technology Qimonda SandforceProlific Technology Qimonda SandforceSeagate Shenzhen Netcom SigmatelSilicon Integrated Systems Silicon Motion Silicon Storage TechSilicon Systems STEC SkymediSmart Modular Tech. Solid State System Super Talent ElectronicsSynopsys Tandon Tanisys

Santa Clara, CA USAAugust 2009 12

y p y yTelechips Teradyne, Inc. TestmetrixTranscend Information Tyco UCA TechnologyUniversity of York Virident Systems WinBond

Page 13: NAND Flash Architecture and Specification Trends

Improving System PerformanceSystem performance is increased by adding more channels or more die y p y gper channel.Ignoring effects of ECC and block management algorithms, total throughput is either array or I/O throughput limited.

NANDNANDNANDNAND NANDFlash

NAND

NANDFlash

NAND

NANDFlash

NAND

NANDFlash

NANDFlash

NANDFlash

Flash

NANDFlash

Flash

NANDFlash

Flash

NANDFlash

ControllerFlash

NANDFlash

Flash

NANDFlash

Flash

NANDFlash

Flash

NANDFlash

Santa Clara, CA USAAugust 2009 13

Page 14: NAND Flash Architecture and Specification Trends

SLC 4KB 2-plane Throughput Example:Async vs. Sync Interface

800 800 800800

800

600

700

/s)

480

448400 400 400

400300

400

500

form

ance

(MB

/

136160160160

152 160 160224

68 80 80 80

240

224

400

120

200 200 200100

200

300

Perf

1 2 4 8 1 2 4 81 2

4

76 11280 80

3876 80 80

56112

34 40 40 40120

19 38 40 4028 56

112

2000

Santa Clara, CA USAAugust 2009 14

1 2 4 81 2 4 8

1# of NAND Die per Channel

# of Channels

Page 15: NAND Flash Architecture and Specification Trends

MLC 4KB 2-plane Throughput Example:

800 800800

Async vs. Sync Interface

704

600

700

/s)

352352400 400

300

400

500

form

ance

(MB

/

120160160160

160256

60 80 80 80

176176 200 200

100

200

300

Perf

1 2 4 8 1 2 4 81 2

4

28 56112

32 64128

60 80 80

14 28 56 80

16 32 64128

30 40 40 4088

7 14 28 408 16 32 64

0

Santa Clara, CA USAAugust 2009 15

1 2 4 81 2 4 8

1# of NAND Die per Channel

# of Channels

Page 16: NAND Flash Architecture and Specification Trends

Conclusions

Larger block sizes to become more difficult to managePage size doubles increasing sequential performance while reducing random performance to compensate for overall slower array throughputECC increases to compensate for data retention and endurance; evenECC increases to compensate for data retention and endurance; even still endurance is decreasing for consumer NAND memory2bpc MLC has a lower manufacturing cost per bit as long as it is on a smaller process node than 3bpc MLC memory – and it fits more customer applications!ppPages per block increasing to reduce die sizeInterface performance increasing to open up a whole new market –enterprise solutions – while helping improve SSD performanceONFI provides a proactive scalable interface for the future with broadONFI provides a proactive, scalable interface for the future with broad industry support

Santa Clara, CA USAAugust 2009 16

Page 17: NAND Flash Architecture and Specification Trends

Questions?

Santa Clara, CA USAAugust 2009 17

Page 18: NAND Flash Architecture and Specification Trends

About Michael Abraham

Manager of Micron’s NAND FlashManager of Micron s NAND Flash Applications Engineering group

B S i C t E i i fB.S. in Computer Engineering from Brigham Young University

T h i l t ti f MiTechnical representative for Micronin ONFI and JEDEC for NAND Flash

Key role in defining and standardizing the high-speed, synchronous DDR NAND interface within Micron and at ONFI

©2007 2009 Mi T h l I All i ht d P d t t d l t t Mi ’ d ti d t h t ifi ti I f ti d t

Santa Clara, CA USAAugust 2009 18

©2007-2009 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.