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Magneto-Resistive IC Memory Lim itations and Architecture ImplicationsRoy E. Scheuerlein

IBM Almaden Research Center650HanyRoad, San Jose CA 95 [email protected], 408-927-3844

AbstractMagneto Resistive, MR, elements offer an alternativeapproach to non-volatile VLSI memory. The approach hasunique aspects which will be related to the requirements ofhigh speed, dense, deep submicron VLSI memory. Thelimitation of resistor thermal noise, sensing power, writecurrent, switch fan out, bandwidth, and voltage supply arediscussed. Possible MRAM amy architectures are listed inthe first section. A novel architecture called the Cross PointM TJ MRAM is described that potentially offers higher signalto noise ratio, lower power and higher density than thealternatives. In following sections Signal to Noise Ratio(SNR) nd Power Versus Bandwidth constraint equations areproposed for MRAM archtectures. Sensing alternatives forMR elements are reviewed and voltage requirements ofMRAM architectures are described. Finally MRAMalternatives are comparedIntroduction

The role of MRAM in the crowded arena of VLSImemories is not yet clear. Success as a small niche marketdepends on superiority of perhaps a single charateristic suchas durability in hostile environments. But sucess as a majorVLSI memory segment probably requires a combination ofnonvolatility, high density, high performance, and low powerdissipation. DRAM excells in the area of high density at lowcost and low power dissipation. SRAM excells in highperformance and low power Qssipation. Flash providesnonvolatility at high density. FeRAh4 has had some successproviding nonvolalility at modest density levels and modestperformance levels. This paper investigates the potential ofMRAM architectures to achieve a compelling combination ofthe desired features.

The next section summarises the key features of MRAMarclutectures.MRAM Architectures

Early MRAM designs took advantage of the AnisotropicMagneto Resistance AMR effect. In order to achieve highdensity, MRAM architectures must provide a small cell size.In terms of the average feature size A,DRAM cells which usea folded bit line architecture occupy 8 hi. The series AMRcell proposed for high density MRAM [l ] elongates the MRelement by 4 to 1 to achieve resistance values compatiblewith VLSI circuits and has a cell area about 121 The usableAMR effect in memory cells is about 2%. Because there isno cell selection device, a crossing word line is used lo disturbthe selected resistor during sensing opperalions. The disturbcould be destructive or non-destructive to the memory state.Conveniently the sense and word lines can also be used towrite a unique cell in the array.

Giant Magneto Resistance GM R provihng a MR ratio of

about 6% improves MRAM S N R and performance. TheGMR MRAM architecture is also a series string of N resistors[2]. Due to structure and resistance similarities to AMR, thecell size is also about 12 h2. A Pseudo Spin Valve PSVsensing mode [3],[4] doubles the signal provided by the GMRdevice but leads to higher write currents since the data isstored in the harder of the two ferromagnetic layers. A wordline is provided to disturb the cell during sensing. Since theorientation of the magnetization for the data state in GMRcells is parallel to the sense line, an extra write conductor isincluded in the cell for writing [3].

Tunnel Magneto Resistance TMR promises even higherMR ratios [SI and has high resistance and a vertical sensingcurrent direction which allows alternative architectures forMRAM arrays. The S N R of either serial or parallel resistorscan be expressed as:

SNR=VoMR / ( 4kTN Rm BW)* * 1/2S N R would tend to decrease for the TMR architecturesdue to the high resistance Rm of the TMR devices. This ismitigated by the higher Vo bias across the element, and higher

MR ratio. An example calculations for a TMR esistor valueof 10Kn, TMR atio of 15%at 300 mv bias, N of 32, and abandwidth BW of 100 Mhz gives a satisfactory SNR of 62assuming Johnson Noise. TMR evices in the submicron sizerange will require perfecting lower specific resistancemagnetic tunnel junctions.

MTJIGNDPLANE I\ Writeline \

Figure 1)Parallel TMR MRAM (a) Circuit,@) Cross section.A parallel arrangement of resistors, Fig. 1, is suggested bythe high resistance value. In this arrangement the voltagerequired in the array ciltl be reduced by a factor N from theseries arrangement while providing the same signal voltage.

The TM R devics is implementedasa vertical sta& of a lowerelectrode, a very thin tunnel barrier and an upper electrodecomprising a Magnetic Tunnel Junction MTJ. A word lineWL not connected to the MTJ is required for sensing, whichcould be either PSV mode or destructive read mode. Sincethe MTJ can be damaged by voltages about one volt, and theparallel combination of MTJs would shunt write currents, aseparate write conductor is needed. A write conductor pathdiagonally across the array is the most area efficient. A

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planarization processes [6] to passivate the MTJ allowsborderless contact of the top conductor to the MTJ makmg a 7h2 cell possible, Fig. 2. Dissadvantages include the largespacing of the write conductors to the ferromagnetic layersand the need for three lines plus a ground connection per cell.

WL0 $ Write Line

. .._-.%*-Figure 2) Parallel TMR Layout 7h2

A matrix arrangement, Fig. 3, of TM R elements is alsopossible. In this case the electrodes of the MTJ are connectedto two sense line, SLx and Sly. SLY is selectively connectedto ground to complete the sense path. The matrix ofunselected MTJs in an N by N arrangement of cells isequivalent to N/2 parallel resistors, so this arrangement hasslightly better S N R than parallel or series arrangements. Inarrays sizes of interest, pattern sensitivity to the sneak pathswill require a word line to facilitate PSV or destructive readmode sensing. An extra line for write currents is also requiredso there are a total of four lines per cell. Since the bottomelectrode typically overlaps the MTJ, the cell size is 9 h2.

\ write tine \

Figure 3) MatrixTMR MRAM (a)Circuit, (b) Cross SectionA switch plus TM R cell is also possible because TMRresistance is compatible with FET switch impedance levels.

The word line controls the switch which causes the sense pathto go through only a single TMR element, Therefore signalincreases by a factor of N and SNR increases by a factor ofsquare root of N. Since the switch can be off when writing thecell, the sense line SL connected to the top electrode of theMTJ can cany write currents. A third line carries the otherwrite current and can also provide a ground connection duringsensing. The cell is estimated to be 12 h2 because of theswitch area.Cross Point MTJ ArchitectureA final TM R arrangement, called the Cross Point MTJArchitecture [7] shown in Fig. 4, uses a diode to block thesneak paths in a matrix arrangement. Each cell has a MTJ anda diode in series between two metal lines at their cross point.

The cell is selected by grounding one word line. while theother word lines are as high as the sense line. The sensecuent goes through the one diode that is forward biased. Thesame two lines can be used for the write currents because thevoltage drop of the diode protects the MTJ from write curentinducedIR drops. The close proximity of the conductors tothe MTJ reduces the write currents required In addition theRC time constants on the array lines are determined by thecapacitance of the diode rather than the high capacitance ofthe tunnel junction reducing sensing time compared to parallelor matrix TMR arrangements.

Figure 4) Cross Point MTJ MRAM (a) Circuit, (b) StructureThe cell requires a thin film diode integrated with VLSI

metahtion and MTJ processes which is a significantchallenge. The cell size is estimated to be 9 h2or as small as6 3L2, Fig. 5, dependingon achieving borderless contacts to thediode.

Figure 5) Cross Point MTJ MRAM Layout (a) 6h2,(b) 9h2Diode Requirements

The ideality factor of the diode effects the differentialresistance of the diode which must be smaller than theresistance of the MR element. This requirement implies thatthe IR drop across the TMR device must be greater than theideality factor times the diode thermal voltage. The falloff ofTMR to half its maximum occurs at a bias voltage in therange of hundreds of millivolts [6] herefore many times thethermal voltage of the diode. The requirement regarding thediode differential resistance therefore can be met withoutsigtuficantMR rolloff.

Since it provides isolation of the sense path from sneakpaths through the unselected cells, the diode for the crosspoint MTJ array must have an on to off conductance ratio inthe range of four orders of magnitude for arrays 128 by 128bits. The reverse bias on the unselected cells can be less thanone volt. Conductance ratios this large are achievable with

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thin film diodes. However the on conductance of typical thinfilm material is too low for cells with feature sizes less than amicron. Improved mobility thin film imterial would berequired to implement Cross Point MTJ cells.Signal versus PowerAn equation relating signal to sense power in terms ofS M , the resistance of the element, and MR ratio is shown inFig. 6.Small N, high resistance, and high MR reduce sensepower. An alternate expression, in terms of Vo, is the samefor all the MR architectures: Ps 2 N (Vo)?/ Rm, where N isthe number of equivalent series or parallel resistors in thesense path. Matrix arrangements of N by N have (N+1)/2equivalent parallel paths.Series GMR and Parallel TMR havesimilar sense power because both Vo and Rm increasesubstantially for TMR. However, the switched TMRarchitectures will have four orders of magnitude lower sensepower than series GMR because all factors in the equation inFig. 6 improve: N is one, Rm is 100 times and M R is threetimes larger.

vslgSNR= I4 4 k T N R m 0 WV S I ~(SNR)' 4kT N R m BW

I J

N VsigSNR= d 4 k T N Rm B W(N Vslg)' = (SNR)' 4kT N Rm BW

I

-- (NVsig) 2 (-!-) (For Parallel R)R m MRPs, ( NV o Is) andIs=&

Rm

L ' IFigure 7) Power BandwidthRatio for MRAM

Sensing TechniquesVarious sensing approaches have been proposed formagneto resistive memory. Auto zero sensing involves a self-reference to the MR element requiring additional sensingtime. PSV technique also involves a self-reference to the MRelement and auto zero sensing. In addition destructive readouttechniques require longer cycle times to restore data. Allthese approaches will be considerably slower than the directsensing used in DRAM and Flash memories. It is possible toconsider direct sensing for MR cells in the case of switchedMR cells which give large signal levels if the tracking ofresistance value between MR elements is less than the MRratio. The Cross Point MTJ cell could be operated in a twincell arrangemant where two adjacent cells are always writento opposite states and then connected to opposite sides of thesense amplifier for sensing. If the tracking of adjacent M Relements is less than the MR ratio. the data state will beindicated by the remaining signal. Of course a bit wouldoccupy twice the area, but the memory performance in termsof cycle time could be faster than DRAM since this is anondestructive sensing scheme.Array Efficiency

For efficient VLSI memory chips. the switches used todrive the lines that access the arrav of cells need to service alarge fan out of cells. Bi-directional switches are needed forthe write lines. The requirements of selection devices indifferent cell arrangement and the area implication ofselection devices is summarized in Fig. 8. Serial and parallelarchitectures all contain at least four switches to control thelines for a given cell. The effect of non-rectangular arraystypically used because the signal can be improved at a smallcost in selection devices is included. If bi-directional currentswhich require two switches per line are only placed on thelong lines, a sigtllficant area savings can result. However, theIR drop in the write lines for MRAM arrays is a criticallimitation to scaling to multi-megabit memories. The switchesin the cell of TMR architectures are assumed to be equivalentto one eigth the peripheral switches, since only the sensecurrent which is less than 100 PA must be conducted.

,...Wte line lengthbecanes excessive

f

N by N

Log(Number of Switches)Figure 8) Power BandwidthRatio forMRhM vs . SwitchCount

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Comparison of MRAM AlternativesTo compare MRAM architectures, Table 1 summarizescell area estimates, SNR, the ratio of Bandwidth times S N R

to Sense Power, and number of lines required to control thecell to indicate cell complexity. Only the switched TMR areseen to be competitive with DRAM. Others fall far short inregard to S N R nd sense power.

Table 2 compares design points for series GMR, parallelTMR and a switched TMR rchitecture. The switchedTMRis shown to have dramatically higher SNR and lower sensepower.ConclusionsA fundamental constraint equation considering SNR, BWand sense power indicates that the number of MR elements inseries with the sensing ciTcuitry impact the fundamentalconstraint proportional to the number squared. It is unlikelythat traditional MR architectures can achive a desiredcombination of high performance, low power and high densityfor multi-megabit memories because of this constraint.Switched TMR architectures have four orders of magnitudelower sense power at the same signal level, and four orders ofmagnitude advantage in the power versus bandwidthconstraint equation compared to MRAM m y s with N equalto 32. This provides a route to simultaneously achieve highsignal level for high performance, ow sense power and smallcell size in an MRAM design. Switched TMR architecturesare a potential approach for MRAM to achieve multi-megabitmemories, assuming sigtllficant technology hurdles inmagnetic tunnel junctions canbe overcome.AcknowledgmentsS. S. Parkin of IBM Research are gratefblly acknowledged.References1. Pohm, A.V. et al, The Design of a One Megabit Non-

volatile M-R Memory Chip Using 1.5 x 5 pm Cells.IEEETrans. on Magnetics, Vol. 24, No. 6 (Nov. 1988),

2. Tang D. D. et al, Spin-Valve RAM Cell, IEEE Trans.on Magnetics, Vol. 31 (Nov. 1995),pp. 3206-3208.3. Po- A V. et al, Experimental and Analytical Propertiesof 0.2 Micron Wide, Multi-layer, GMR, Memory

Elements, IEEE Trans. on Magnetics, Vol. 32, No. 5(Sept. 1996), pp. 4645-4647.

4. Daughton, J. M., Magnetic Tunneling applied toMemory, 41st Annual Conference on Magnetism andMagnetic Materials, Pqxr AA-04, November 12, 1996.

5. Gallagher, W. J. et a& MicrostructuredMagnetic TunnelJunctions, J. Applied Physics, Vol. 81, No. 8 (Aprrl6. Lu, Y. et al , Bias Voltage and Temperature Dependanceof Magnetic Tunnel Junctions, J. Applied Physics, Vol.

83,No. 11 (June 1998),p. 6515.7. W. Gallagher, J. Kaufmaq S. &kin, R. Scheuerlein,

U.S.P. 5,640,343, June 1997.

Many useful dwcussions with Dr. W. J. Gallagher, and Dr.

p ~ .117-3119.

1997), pp. 3741-3746.

N 32MR 6%Rm 100nv* 3.0mV

Table 1)MRAM architecture comparison of a rea, SVR, sense power, andcomplexiy, assuming ZWR = 15%,GMR = 6%,AMR = 2%,Rm = IO Kf2 orTRM an d I O 0 R or GMR an d AMR. The SNR is for IO 0Mhz, and noisefactor of one. The DRAM SNR, estimated fo r the cell switch, is not thelimiting factor because of non-random coupled noise sources.

32 115% at .3v10kn 10k !21.4 mV 45 mV

15% at .3V

Table 2) MRAM Design Point Comparison fo r GMR, Parallel IUR an darchitechues at 2. 5 v, 0.5micron technology.iode

-PsSNRatlOOMHzconeerns

- r1.25mW 2.4mW 75pw41 62 348 ( R + R d )Vdd Scaling TMR Rolloff lX n Film DiodePower PowerLOW F h HighRm

I 300mV I 300mVo I 50 mVArrayvoltage I 1.6V I 300mV I Vo+VdiodeCell PS I 0.8mw I 0.3 mW I 9 uw

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