nanoelectronics as innovation driver for a green … · 2011. 11. 13. · © imec 2011 /...

© IMEC 2011 / CONFIDENTIAL

NANOELECTRONICS AS INNOVATION DRIVER FOR A GREEN SUSTAINABLE

WORLD

Cor Claeys


TECHNO LO GY IN EVERY ASPECT O F O UR LIFE

HUMAN++++

2 C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS


4.5 BILLIO N CELL PHO NES 3 C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS


4.5 BILLIO N CELL PHO NES 4 C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS


54 MILLIO N UNITS IN 2011 208 MILLIO N BY 2014

2011 EXPLO SIO N TABLET PC



HEALTHY LIFE STYLE SUPPORTED BY ELECTRONICS


© IMEC 2011 / CONFIDENTIAL C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS 8

KEEP INCREASE OF THE NUMBER OF COMPONENTS. COST PER COMPONENTS DECREASES!


TECHNOLOGY ROADMAP: STRATEGIC AGENDA

CNT, nanowire, TFET Graphene Quantum computing Spintronics Polymer electronics ….



SCALING HAMPERED BY LEAKAGE CURRENTS

C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS 10

Sub-VT Leakage

Gate Leakage

2. Gate oxide leakage or Tunneling current – As oxide thins down, leakage increases

exponentially

1. Subthreshold leakage ▸ Shorter channel lengths

▸ Threshold voltage not scaling as fast as VDD


TACKLING THE POWER PROBLEM

11

Solution New Material e.g., High-K dielectric

Gate Leakage

C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS


TACKLING THE POWER PROBLEM

12

Solution New Material e.g., High-K dielectric

Gate Leakage

Solution New Architecture e.g., Fully Depleted Devices

for better Short-Channel control

Sub-VT Leakage


© IMEC 2011 / CONFIDENTIAL 13

time

Front End silicide

TRANSISTOR SCALING

>=130

strain

USJ

90 - 65 - 45 Strain, USJ

NiSi

25 nm

NiSi

25 nm

FUSI

HfO 2 high -k

metal gate

45 - 32 High - k, Metal Gate

FinFET

32 - 22 - 16 Non-planar

devices

FinFET

New process modules New materials New device concepts



• e-SiGe + tCESL

• (100)/[100] + tCESL

90nm • SMTx1

65nm • SMTx2

45nm 32nm

• e-SiGe + tCESL

• (100)/<100> + tCESL

• DUAL CESL

• e-SiGe + tCESL

• e-SiGe + DUAL CESL

• DUAL CESL

• SPT (Stress Proximity Technique)

• (Surface Engineering: (110)/<110> pMOS; (100)/<100> nMOS)

• SMTx3

• e-SiGe + tCESL

• e-SiGe + DUAL CESL

• DUAL CESL

• SPT (Stress Proximity Technique)

• Surface Engineering: (110)/<110> pMOS (100)/<100> nMOS

• e-SiC

STRESS ENGINEERING : A DRIVING FORCE …


time

Front End silicide

TRANSISTOR SCALING

>=130

strain

USJ

90 - 65 - 45 Strain, USJ

NiSi

25 nm

NiSi

25 nm

FUSI

HfO 2 high -k

metal gate

45 - 32 High - k, Metal Gate

FinFET

32 - 22 - 16 Non-planar

devices

FinFET

Ge/IIIV

16 and......

gphene

New process modules New materials New device concepts


TunnelFET

CNT’s Ge/IIIV

nanowires

graphene

??


Ge PMOS

[1]: MIRAI IEDM 2007[2]: CEA-LETI ESSDERC 2008

1

2This work:ION=478µA/µmIOFF=37nA/µm

[1]: MIRAI IEDM 2007[2]: CEA-LETI ESSDERC 2008

1

2This work:ION=478µA/µmIOFF=37nA/µm

0

200

400

600

0 0.2 0.4 0.6 0.8 1

Strained GeUnstrained Ge

Hol

e m

obili

ty (c

m2 /V

s)

Effective Field (MV/cm)

x2.5

x4.3

Si Universal

J. Mitard et al., IEDM 2008, p. 873


Ge PMOS – INTERFACE ENGINEERING


Ge DEVICES – SURFACE PASSIVATION

Cross-sectional TEM images of a high-k gate stack on a Ge surface passivated by different thicknesses of Si. At 12 MLs of silicon, the layer relaxes, giving rise to misfit dislocations at the interface.


0 200 400 600 800 100010-6

10-4

10-2

100

I OFF

_DRA

IN @

V G =

0V

[uA/

um]

ION @VG = -1V [A/um]

W=10umVDD=-1V

HIGH-MOBILITY GE-BASED IMPLANT-FREE QUANTUM WELL DEVICES

HKMG (GF)

Si

rSiGe SiGe_45% QW

HP target

IFQW SiGe 45% + epi S/D booster 25%

REF IFQW SiGe 45%

ION = 1mA/um

2nd generation SiGe QW with additional eSiGe S/D booster achieved extremely high performance (Ion=1mA/um) combined with intrinsically superb Short-

Channel control (DIBL ~ 130mV/V, Lg ~ 30nm)

[uA/um]

2nd

gen.

IFQ

W

(10’

10)

1st g

en. I

FQW

(0

4’10

)


CMOS WITH HIGH-MOBILITY CHANNEL MATERIALS

Combination of high mobility III-V nMOS and (strained) Ge

pMOS integrated on Si substrate for ultimate CMOS performance

Ge has lightest hole m*

good for pMOS Many III-V

materials have light electron m*

ideal for nMOS

S. Takagi, The University of Tokyo, INC4 2008

(In)GaAs or other III-V nMOS Si CMOS

Si wafer Strained Ge grown on Si or GeOI substrate

(In)GaAs or other III-V grown on Ge

Strained Ge pMOS



Ge AS INTERMEDIATE SEMICONDUCTOR

• A wide range of materials could be grown on a Silicon wafer with Ge as an intermediate material to achieve low defect-density III-V Silicon Most interesting candidates: GaAs, InGaAs, InAs, …..

? ?

Ge

InAs InSb ?

Si

InP GaAs

0 10000 20000 30000 40000 50000 60000 70000 80000 90000

Elec

tron

mob

ility


Demonstration of: Common gate stack for IIIV & Ge based devices Selective IIIV integration, directly on Silicon substrate

Issue left of Dit @ interface IIIV – gate stack

HIGH-MOBILITY IIIV-BASED QW DEVICES

pMOS nMOS

[Imec, IEDM’09]

InP

Si

Ge

Gate

N+ InGaAs

Cu

W Plug

InGaAs channel

STI

HK/MG

InGaAs QW

InP buffer

Si

Al2O3

S-passivation



SELECTIVE EPI GROWTH OF Ge AND III/V AFTER STI Selective growth of Ge epi after STI formation on Si wafer

Low defect densities obtained after proper annealing

Provides flat surface that allows further scaling of transistor gate length

Good quality selective growth of thin (In)GaAs on Ge demonstrated No large defects or dislocations can be observed by

TEM

SiO2

Si

n-Ge

Si

SiO2 (In)GaAs (In)GaAs SiO2



SELECTIVE GROWTH OF Ge AND III/V ON SI WAFERS

SiO2 n-Ge

Si

InP SiO2

Si

Down to W ~ 10-15nm

Si

Ox

Si

Ge SiGe III/V

Si

Ox

T_recess = 50-60nm

Si

Ox

Si passivation (t < 10 ML)

Field recess Ge

SiGe III/V

Ox

Local selective growth after STI allows integration of Ge and III/V materials on Si wafers, also for FinFET’s. confined growth to grow materials with high lattice mismatch to Si, >> tc

Si

InP

Ge GaAs

Ge InP

Si

C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS 24


MULTI-GATE STRUCTURES



MATERIALS AND DEVICES

26

poly-Si

Fin

FINFET

Fin

Strained Si High-k

Metal gate Multi gate

SRAM



SRAM CELL SIZE ROADMAP

0

0.2

0.4

0.6

0.8

1

1.2

0 0.2 0.4 0.6 0.8 1 1.2

Vout

(V)

Vin (V)

0.22µm

0.40

6µm

0.089µm2 SRAM

2001 2004 2007 2010

0.1

1 TSMC IBM NEC IFX Toshiba Samsung Motorola Intel Sony Hitachi LSI Logic ST Microelectronics Fujitsu IMEC Texas Instruments

SR

AM ce

ll size

(µm

2 )

Year of publication [IEDM, VLSI]

65

32

90

130

45

0.3

0.5

2

0.2

Optical trend line

E-beam

Intel

(production)

1st SRAM w/ EUVL

22

16 Single Double

patterning

2nd generation FinFET-based 22nm SRAM cell (10% smaller) ... and already gearing for 16nm!

1st gen. 22nm 2nd gen.

22nm IMEC

16nm target



CONCEPTS FOR FULLY DEPLETED CHANNEL

28

Tdep

Thin body channel (<10nm)

S D


2nd Gate (FinFET) Buried Oxide (UTB-SOI) High-bandgap + QW


EXPLORATORY CONCEPTS

29

Tunnel FET Graphene FET



DEVICES WITH REDUCED POWER CONSUMPTION

Improved subthreshold slope devices can have high ION/IOFF ratio at low switching voltage reduced supply voltage and power consumption For carrier transport limited by thermionic emission over a barrier: dψS/d(log10l) ≈ 60 mV/decade at room temperature

OFF Ec

Ev

ON Ec

Ev

p i n

Band gap blocks tunnel current

Band-to-band tunneling

drain

gate

source

p

i

n

gate

drain

gate

source

p

i

n

gate

TunnelFET basic idea: use the band-to-band tunneling as an energy filter to overcome the 60mV/decade subthreshold slope limitation ON/OFF switching determined by band-to-band

tunneling at source side


CHOICE TFET MATERIAL: EFFECT OF BANDGAP

- tunneling probability ~ (E2mr1/2.Eg

-0.5) exp(-A.Eg1.5)

Eg,Si = 1.12 eV

Eg,Ge = 0.66 eV

- I-V curves show:

Ids,Ge ≈ 100 Ids,Si

- smaller bandgap improves tunneling, but want silicon-based TFET… Remark: Ge TFET-curve is shifted to the left for easier comparison



COMPLEMENTARY HETERO-STRUCTURE TFETS

A. Verhulst et al., IEEE Electron Dev. Lett., 29, 1398 (2008)


VDD ~ 0.25V (“Green” Transistor)


TFET Implementations

imec

Hor

izon

tal

Vert

ical

Source

Drain

Gate

Mayer et al., IEDM (2008)

Bhuwulka et al., IEEE TED(2004)

Source

Drain

Leonelli et al., SSDM (2009)

Vandooren et al. VLSI Workshop (2009)

Gate

Source

Drain

Literature FinFET

Nanowires



Progress Toward Hetero-junctions Implementations

34

TFET PERFORMANCE SUMMARY - SEABAUGH



Tunnel FET devices based on nanowires

Possible implementation of Tunnel FETs using etched nanowires

N- Epi layer

N+ substrate

P+ Epi layer

N- N-

P+

N+ substrate

P+

TFET implementation

N- N-

P+

N+ substrate

P+

etched nanowires

TiN

Etched NW

Templated and constrained growth of nanowires

Constrained cat-based

Constrained cat-less InAs NW growth on Si(111)

Growth can be performed

partially or fully constrained, with

or without catalyst

Etched Si nanowire

TUNNEL FET BASED ON NANOWIRES



Progress Toward Hetero-junctions Implementations

36

III-V AND GRAPHENE TFETS


A. Seabaugh – ESSDERC 2011


3D 2D 1D 0D

Curl, Kroto & Smalley 1985 Nobel prize 1996

Fullerenes Carbon nanotubes

Multi-wall 1991 Single-wall 1993

Graphite XVI century

Graphene

2004 Geim, Novoselov Nobel prize 2010

CARBON STRUCTURES



FIELD-EFFECT DEVICES

Lemme et al., IEEE Electron. Dev. Lett. 28, 4 (2007)

“Classical” field-effect approach

• Top and bottom gates • Ion/Ioff ratio ~10 at 300K

p-Si

SiO2

Graphene

300 nm

SiO2 20 nm Drain Source Gate

Cannot switch it off!



COMPARISON OF FREQUENCY PERFORMANCE

39

F. Schwierz, Proc. Int. Conf. on Solid-State and Integrated Circuit Techn., Eds. T.-A. Tang and Y.-L. Jiang , pp. 1202-1205 (2010)



CNT INTERCONNECTS

Current capacity: • Cu ~ 106 A/cm2

• CNTs ~ 109 A/cm2

Thermal conductivity: • Cu ~ 400 W/m.K • CNTs ~ 5000 W/m.K

CNT exhibit enhanced electrical and thermal properties over Cu

M1-Cu

V1 level (CNT)

M1-Cu

M2-Cu

V1-CNT

M2-Cu

High-density of MW CNT obtained with Fe on Ti Approaches density needed for interconnects ~1012 MWCNT or ~1013 cm-2 CNT shells

• Outer diameter of 6.5 – 8.0 nm (with 7- 10 sheets), inner diameter ~ 5nm

XRR 0.43 g/cm3

~1012 CNTs/cm2

10 µm

36 µm

650C* 6.5

6.7

7.0

7.9

7.8

7.8

6 walls

Carpet of densely aligned CNT



Nano-bio vision :Bio ::

transistor

Nano building stone

cm µm nm

x109

BIOTECH

NANOTECH

NANOELECTRONICS

NANO-BIO VISION: BIO AND ICT MEET AT THE NANOSCALE


ARTIFICIAL SYNAPSE

ARTIFICIAL SYNAPSE = functional interface allowing bi-directional communication between a neuron and an integrated circuit = neurons-on-chip


A MEDICAL LAB OF ONLY 1X1 cm2

Detection platforms for low concentrations of disease molecules: Fast Easy to use Cost effective 43 C-COE PICE, TOKYO, OCTOBER 4, 2011 C. CLAEYS


ORGANIC MICROPROCESSOR



1971: Int e l 4004 First Si μProc. 10 µm 4 bit pMOS -15V Vdd 2300 TOR 108 KHz

2011: im ec & Holst First plastic μProc. 5 µm 8 bit pMOS, dual Vt -10V Vdd 2000 TOR 6 Hz


Courtesy P. Heremans


Photovoltaics: IMEC’s terrestial solar cells roadmap

Single X ⇒ Multi X

Thick(>180µm) bulk Si

Single X ⇒ Multi X

Thin-film c-Si < 20 µm Fully organic Thin-film cells for large-scale power generation Epitaxial cells

Cells on ceramic/glass Single X ⇒ Multi X Epitaxial cells Cells on ceramic/glass

Organic cells for consumer applications

2000 2010 2020 2030 Near-term Intermediate term Long term

t

Achievable direct cost module level (€/Wp) 2.7-3.5

300µm multi 150µm multi Thin ribbon Thin-film Organic cells

1.3-1.5 1.1-1.3 0.5-1.0 < 0.5

SOLAR+ Roadmap


ORGANIC SOLAR CELLS EFFICIENCIES ABOVE 5%



MULTI-JUNCTION SOLAR CELLS: STATE-OF-THE-ART (WORLDWIDE)

Record conversion efficiencies obtained (32% under 1 sun, 40.1% under concentration)

Key technologies: • current matching of top and middle cell • wide-gap tunnel junction • exact lattice matching (1% Indium added in GaAs cell) • InGaP disordering • Ge junction formation



GaN ON Si FOR LOWER COST POWER & LED DEVICES

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

-10 -5 0 5 10 15 20 25 30

Peabs(dBm)

Pout

(dB

m),

GP(

dB)

0

5

10

15

20

25

30

35

40

45

50

PAE(

%)

PoutGPPAE 12W

19dB

Vds=60V

GaN growth on Si

200 mm

Thickness (nm)

Power HEMTs LEDs

TDD reduction



TDD reduction


GaN FOR POWER CONVERSION AND SOLID-STATE LIGHTING


CMORE


nanoelectronics as innovation driver for a green … · 2011. 11. 13. · © imec 2011 /...

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