Advanced Electronic Packaging

PACKAGING STANDARD

• State-of-practice relies on standard backplanes and chassis

Cold Capable Electronics

• State-of-practice relies on heaters to keep electronics within the Mil-Spec temperature range

• Operation and survival at low temperatures eliminates battery mass and power for heating of electronics

CHIP ON BOARD TECHNOLOGY

• State-of-practice relies on flat-pack surface-mount technology

• Chip on board eliminates the conventional flat-pack packages, dramatically reducing area on the printed wiring board.

• Our proposed packaging standard requires the density of chip on board technology in order to work

LOW-POWER COMPUTING

• State-of-practice relies on standard cPCI cards requiring several cards to implement command and data handling functionality

• Chip on board and system on a chip technology allow the imple-mentation of a single-board command and data handling system

Low-Power, Low-Temperature Electronics for the Europa Lander

Doug SheldonJet Propulsion Laboratory, California Institute of Technology

Don HunterJet Propulsion Laboratory, California Institute of Technology

Gary BolotinJet Propulsion Laboratory, California Institute of Technology

gary.s.bolotin@jpl.nasa.gov

Objectives

The goal is to develop technologies that maxi-mize the science return from the baseline Europa Lander. These technologies will allow the lander to last longer on the surface or allow more room for additional science instruments. This goal will be achieved through:

• Backplane and chassis mass are eliminated

• External connections – 181 1A capable or 100 3A capable

• Internal connections – 300 slice to slice

• Simplified thermal design – Each slice conducts heat directly to spacecraft

Electronic Packaging

• Dramatically reduce electronics volume [factor of 9.7] and mass [factor of 3.75] through the use of advanced packaging

Low-Power Multi-Core Computing• Develop an advanced embedded processing module

that enables us to:

• Eliminate the need for the mass-intensive Compact PCI backplane and chassis mass

• Lower power by combining instrument and tele-communication interfaces within the embedded processing module. Cold Capable Electronics

• Reduce the power required for survival and opera-tional heating by allowing electronic assemblies to operate and survive at temperatures beyond the Mil-Std temperature range of -55 to +125C

National Aeronautics and Space Administration

Jet Propulsion LaboratoryCalifornia Institute of TechnologyPasadena, California

www.nasa.gov

© 2016 California Institute of Technology. Government sponsorship acknowledged.

National Aeronautics and Space Administration

Yutao HeJet Propulsion Laboratory, California Institute of Technology

MSL Rover RPAM6U Standard cPCI Chassis

Europa Lander Avionics Goal

Slice-Based Packaging Standard

Conventional Packaging Baseline

6U Card 16cm x 23cm

Proposed 10 cm x 10 cm packanging standard

10 cm x 10 cm x 1 cm Motor Control Card

2.0 cm x 2.0 cm Motor Driver Module

System on a Chip

These technologies

make a single-board

CDH possible

17 mm x 12 mm LVDS

Driver COB Package

Performance Metrics State-of-practice Proposed Electronics Goal

Non-operational Temperature Range

-55 to +125C -40 to +115C after DP margin

-100C[TBC] for CDH

-200C[TBC] outside

Operational Temperature Range

-55 to +125C -40 to +115C after DP margin

-70C[TBC] for CDH -70C outside

Advanced conductive epoxies allows for

survival of electronics down to Europa

surface temperatures

Performance Metrics State-of-practice Proposed Electronics

Goal

Volume

51,639 cc – MSL Rover

11,891 cc – Europa Clipper 8,724 cc – Europa Lander

Baseline

< 1500 cc

Mass

46.2 kg – MSL Rover1

23.7 kg– Europa Clipper2 10.5 kg – Europa Lander

Baseline < 4 kg

Power 189 W – MSL Rover

52.0 W – Europa Clipper 26 W – Europa Lander Baseline

< 13 W