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NATIONAL RADIO ASTRONOMY OBSERVATORY

Charlottesville, Virginia

Electronics Division Internal Report No. 235

LOW NOISE, 15 GHz, COOLED, GaAsFET AMPLIFIER

S. Weinreb

R. Harris

September 1983

Number of Copies: 150

LOW NOISE, 15 GHz, COOLED, GaAsFET AMPLIFIER

Table of Contents

I. Introduction 3 II. Construction 5 III. Adjustment and Test 10

Figures

Figure 1 Amplifier Configuration . . . 4 Figure 2 Three-Stage Amplifier Without Cover 4 Figure 3 Schematic of Single Amplifier Stage 7 Figure 4 Amplifier Without Coaxial Components 8 Figure 5 Coaxial Components 8 Figure 6 Middle-Stage View of Amplifier 9 Figure 7 Close-Up View of FET 9 Figure 8 Cryogenic Test Configuration 11 Figure 9 Test Receiver 11 Figure 10 Typical Gain and Noise Temperature 12

References 14

Appendices

Appendix I Parts List for Ku-Band FET Amp (15.1 GHz) 15 Appendix II (Drawings)

A. Amplifier Cover 19 B. Transistor Strap 20 C. Transformer Slug 21 D. Chassis 22 E. Chassis Details 23 F. Interstage Sup 24 G. Interstage Inner Conductor 25 H. Output Endplate 26 I. Input Endplate 27 J. Input SMA Modification 28 K. Output SMA Modification . 29 L. Mounting Plate with Output Transition 30

LOW NOISE, 15 GHz, COOLED» GaAsFET AMPLIFIER

S. Weinreb and R. Harris

I. Introduction

This report describes the testing and construction of 60 amplifiers for

the VLA with the following specifications at a physical temperature of 15K:

FREQUENCY NOISE (including GAIN (including 5 to GHz isolator) 10 dB pad)

15.1 < 57K 19 + 1 dB

15.4 < 66K 19 + 3 dB

14.4 < 106K 19 + 3 dB

The amplifier is incorporated with an input isolator, output attenuator (for

matching), and a SMA to waveguide adaptor as shown in Figure 1. This configui

is designed to easily fit the existing VLA dewar and improve the system noise

temperature from 300K to 100K.

Background information on the amplifier design is given in a paper [1]

by Tomassetti, Weinreb and Wellington describing a similar 10.7 GHz amplifer

and in a report [2] by Sierra describing noise parameter measurements and

computer programs used for the amplifier design. The major characteristics

of the design are as follows:

1) GaAs FET's in the 1.75 mm square package are used. Early experiments

with chips gave similar results and it was believed that better reliability

would be achieved with packaged devices.

2) A coaxial geometry with a round center conductor in a square groove

as suggested by Tomassetti is used. The characteristic impedance of this

_4-

Fig. 1. Input isolator (lower left), amplifier, output 8 dB pad, and outpu coax-to-waveguide transition mounting plate. The isolator input connects via a short .141 coaxial cable to an input coax-to-wavegu transition which is part of a gapped waveguide thermal transition to 300K.

Fig. 2. Three-stage amplifier with cover removed. Input is at left and output and DC bias connector are at right.

-5-

geometry is given by Wheeler [3]. Tuning is accomplished by moving small A/4

slugs on the center conductor and DC blocks are formed by enclosing the FET

leads, cut to specified length, in Teflon tubing within a hollow center conductc

DC bias is provided by small wires, A/4 long, soldered directly to the FET

package. This configuration has been found to be reliable, mechanically stable,

repeatable, and amenable to theoretical analysis.

3) The amplifier input and output return loss is reasonable 10 dB)

but an input isolator and output attenuator are used to provide > 20 dB return

loss. The FET source lead inductance is kept to a minimum.

II. Construction

The chassis is milled from copper stock and plated with 1.2 ym of gold.

A 7/64" carbide mill is useful for the rectangular slot. A thermostatically

controlled hot plate, low power microscope, and a 60W, 700oF soldering iron

with ^ 1 mm tip are needed for construction. The assembly procedure is as

follows:

1) With chassis heated on a hot plate to 175-200oC, solder the input

end plate to the chassis, all chip capacitors except the ATC111 0.8 pF gate

bias bypass, and the ground wire posts utilizing Ersin SN62-.028 rosin filled,

2% silver solder. Clean chassis with flux remover and check all chip

capacitor values with a capacitance meter.

2) Using the small soldering iron, solder chip resistors, bias resistors,

and protection diodes with SN62 solder.

3) Using the hot plate again, but at a temperature of 100o-120oC,

solder the ATC111 0.8 pF gate bias bypass capacitors using Alpha 20E2 solder

and Superior #30 flux.

-6-

4) Glue the rexolite support on interstage center conductors as shown

in Figure 5 using Eastman 910 adhesive.

5) Trim the leads on the MGF1412-09 second-stage FET to 1.8 mm on both

source leads and to the values given in Figure 3 for gate and drain leads.

Solder #40 enameled-copper bias leads to the FET.

6) Install #22 Teflon tubing (OD = 0.94 mm, ID = 0.43 mm) in the center

conductors cutting off the tubing 0.25 mm beyond the end of the center conduct*

Install tuning slugs on center conductors checking for a firm, sliding fit.

7) Install second-stage FET together with both interstage networks into

the chassis and fasten source lead champs.

8) Prepare MGF1412-10 third-stage FET as in paragraph 5), above, and

install in chassis by bending the gate lead.

9) Using the hot plate at 200oC, solder the DC bias connector into the

output end plate with SN62 solder. Solder #32 enameled copper bias wires to

the connector pins using the small soldering iron and SN62 solder. Bolt the

output end plate to the chassis and solder bias wires to chip capacitors.

10) Prepare and install the NE67383 first-stage FET as in paragraph 5),

above.

11) Solder all FET bias wires using SN62 solder except the tie connection

to the ATC111 gate bias bypass capacitor is made with 20E2 solder.

12) Install input and output SMA connectors complete with Teflon tubing

and tuning slugs.

13) Apply a small amount of polystyrene cement to the FET lead to Teflon

tubing interface points.

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5. Close-up view of sliding transformers (top), center conductor, and Teflon-tubing DC blocks.

-9-

Fig. 6. Middle-stage view of amplifier.

Close-up view of FET, bias leads (#40 enameled copper wire), and 0.8 pF gate bypass capacitor. Note the Teflon tubing protruding from within center conductor and pressing against FET for mechani stability.

-10-

III. Adjustment and Test

The test configuration for the amplifier is shown in Figures 8 and 9;

this equipment is used in conjunction with an Apple computer, ADIOS A/D

interface [4], and N0ISE1 program to give data output as shown in Figure 10.

The accuracy of the low-noise temperature measurements is increased by

utilizing a cooled 20 dB Narda Model 4779 attenuator at the amplifier input.

By cooling this attenuator from 300K to 15K, the temperature added to the

amplifier noise temperature of ^ 40K is decreased from 300K to 18K. The

error due to noise source or detector-law inaccuracy is then reduced by a

factor of (300 + 40)/(18 + 40) = 5.9.

The noise source, input coaxial line, attenuator cascade was calibrated

at the isolator input connector by comparison with a NRAO liquid nitrogen

and room temperature noise standard. This was performed with the test dewar

open at 300K. The change in the attenuation value due to cooling from 300K

to 15K was measured at DC and was an increase of 0.18 + .01 dB for two Narda

attenuators. This is approximately compensated by a decrease in the loss of

the coaxial lines as determined from measurements described in a previous

report [5]. An error of 0.1 dB in the noise source excess noise temperature

ratio would produce an amplifier noise temperature error of 1.3K. The

temperature of the cooled attenuator is monitored with a Lake Shore Cryotroni<

DG-400 sensor.

The amplifier is tuned at 300K for minimum noise at 15.1 GHz and for

gain flatness. An initial bias of 5V, 5 mA; 5.5V, 10 mA; and 4V, 10 mA is

used for the first, second and third stages respectively at 300K. These valu<

were then optimized at 15K for minimum noise and gain within specifications;

-11-

ig. 8. Test configuration showing HP346B noise source (top, middle), low-loss coaxial thermal transition into dewar, Narda 20 dB attenuator with temperature sensor, Pamtech input isolator, amplifier under test, Narda 7 or 8 dB output attenuator, output transition, isolator, and test receiver.

Fig. 9. Test receiver consisting of an Avantek 2-8 GHz YIG-tuned oscillator, Aertech RX16000 frequency doubler, isolator, directional coupler to provide reflectometer source, and mixer-preamp for noise temperature measurements.

-12-

1 ) 2ku, Pi3n-123. OPT BIH1;, ? DB P^D 14:16.6 nb'16/-83 TRU=f,4.7 TLU=4.-'.,=i C- r-.|=17'.3 C.H=2l T=11.5k 3.y3»6. 1 r35 5.52.M.3.-1.0? 4,9.7,-1. »"U 1

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Typical gain and noise temperature for an ampli including input isolator and output 7 dB attenu at physical temperatures of 15K (top) and 300K.

-13-

typical final values were 4V, 5 mA; 5.5V, 15 mA; and 4V, 8 mA. The amplifier

gain including a 7 dB pad is typically 12 dB at 300K and 19 dB at 15K as

shown in Figure 10. The typical improvement in noise temperature is a factor

of ^ 8.

A large variation of cold noise temperature with the NE67383 transistor

batch was observed. An initial batch of 20 averaged 35K at optimum frequency;

a second batch 40K; and the third batch 47K. The lowest noise temperature

was 31K and ^ 15% of the transistors gave noise temperatures > 50K and were

rejected. Early tests with the NE13783 produced noise temperatures above 60K.

-14-

REFERENCES

[1] G. Tomassetti, S. Weinreb, and K. Wellington, "Low-Noise 10.7 GHz Cooled

GaAs FET Amplifier," Electronics Letters, vol. 17, no. 25/26,

December 10, 1981, pp. 949-951.

[2] M. Sierra, "15 GHz Cooled GaAsFET Amplifier-Design Background Information,"

NRAO Electronics Division Internal Report No. 229, June 1982.

[3] H. A. Wheeler, "Transmission-Line Impedance Curves," Proc. IRE, vol. 38,

no. 12, December 1950, pp. 1400-1403.

[4] G. Weinreb and S. Weinreb, "ADIOS - Analog-Digital Input Output System

for Apple Computer," NRAO Electronics Division Internal Report No. 212

April 1981.

[5] S. Weinreb, "Cryogenic Performance of Microwave Terminations, Attenuators,

Absorbers, and Coaxial Cable," NRAO Electronics Division Internal

Report No. 223, January 1982.

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