ncv1362 - automotive primary side flyback controller

© Semiconductor Components Industries, LLC, 2019

July, 2021 − Rev. 51 Publication Order Number:

NCV1362/D

Automotive Primary SideFlyback Controller

NCV1362The NCV1362 is a highly integrated primary side quasi−resonant

f lyback cont ro l le r capable o f con t ro l l ing rugged andhigh−performance off−line power supplies.

Thanks to a Novel Method this new controller saves the secondaryfeedback circuitry for Constant Voltage and Constant Currentregulation, achieving excellent line and load regulation withouttraditional opto coupler and TL431 voltage reference.

The NCV1362 operates in valley lockout quasi−resonant peakcurrent mode control mode at high load to provide high efficiency.When the power on the secondary side starts to diminish, thecontroller automatically adjusts the duty−cycle then at lower load thecontroller enters in pulse frequency modulation at fixed peak currentwith a valley switching detection. This technique allows keeping theoutput regulation with tiny dummy load. Valley lockout at the first 4valleys prevent valley jumping operation and then a valley switchingat lower load provides high efficiency.

Features• Qualified for Automotive Applications

• AEC−Q100 Qualified with the Following Results♦ Device Temperature Grade 1: −40°C to +125°C♦ Device HBM Classification Level 2: ±2 kV

• Constant Voltage Primary−Side Regulation < ±5%

• Constant Current Primary−Side Regulation < ±5%

• LFF and BO Feature on a Dedicated Pin:

• Quasi−Resonant with Valley Switching Operation

• Optimized Light Load Efficiency and Stand−by Performance

• Maximum Frequency Clamp (No Clamp, 80, 110 and 140 kHz)

• Cycle by Cycle Peak Current Limit

• Output Voltage Under Voltage and Over Voltage Protection (UVP or OVP)

• Secondary Diode or Winding Short−Circuit Protection

• Wide Operation VCC Range (up to 28 V)

• Low Start−up Current

• CS & VS/ZCD Pin Short and Open Protection

• Internal Temperature Shutdown

• Internal and Fixed Frequency Jittering for Better EMI Signature

• Dual Frozen Peak Current to Both Optimize Light Load Efficiency(10% Load) and Stand−by Performance (No−load)

• Fault Input for Severe Fault Conditions, NTC Compatible for OTP

• These are Pb−Free Devices

Applications• Automotive Auxiliary Power Supplies

• On−Board Charger & Traction Inverters Auxiliary Power Supplies

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See detailed ordering and shipping information on page 28 ofthis data sheet.

ORDERING INFORMATION

MARKING DIAGRAM

SOIC−8CASE 751−07

IC (Pb−Free)

1

8

V1362yyALYW

�1

8

V1362yy = Specific Device Code(See page 28)

A = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

PINOUT DIAGRAM

(Top View)

DRVGNDVCCBO/LFF

CSFault

COMPVs/ZCD

1

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Figure 1. NCV1362 Typical Application Schematic for AC Input Voltage

0

Out

0

RTN_Out

NCV13621 VS/ZCD

5DRV4 CS

2 COMP

3 Fault 6GND

8BO/LFF

7VCC

Ac

1

2

3

Ac

0

1

2

3

4

5

Figure 2. NCV1362 Typical Application Schematic for DC Input Voltage

NCV13621 VS/ZCD

5DRV4 CS

2 COMP

3 Fault 6GND

8BO/LFF

7VCC

Dc+ Out

0

1

2

3

RTN_Out

0

1

2

3

4

5

Dc−

0


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Figure 3. Functional Block Diagram

VCC and LogicManagement ofdouble hiccup

S

R

Q

UVLO

GND

UVLO

POReset

Vdd

VCC (OVP)

FB Reset

Max_Ipk reset

Soft Start

POReset

Vs /ZCD

OCPTimer

Count

Reset Timer

VCC (Reset)

ResetDouble_Hiccup_ends

Comp

Vcc

Clamp

LEB 1

Blanking

CS

VILIM

OTA

SS

QR multi−modeValley lockout &

Valley Switching &VCO management

POReset

126% Vref_CV 1

ICS

VDD

POReset

DbleHiccup

VUVP

OVP_Cmp

UVP_Cmp

LEB2

VCS(Stop )

4 clkCounter

ResetCounter

Note:OVP: Over Voltage ProtectionUVP: Under Voltage ProtectionOCP : Over Current ProtectionSCP: Short Circuit ProtectiontLEB1 > tLEB2

OCP

S

R

Q

Peak currentControl

1/ Kcomp

DbleHiccup

VCC(OVP )

CS pin Open (VCS > 1.2V) & Short (VCS < 50

mV) detection isactivated at each startupICS_EN

ICS_EN

SCP

CS pin Fault

DRV

S

RQ

UVP

Vcc

EN_UVP

EN_UVP

UVP

Zero Crossing &Signal Sampling

CCControl

Sampled Vout

FBFB_CC

FB_CV

Vref_CV1

4 clkCounter

DbleHiccup

Vref_CC

Control Law&

Primary PeakCurrent Control

OVP

SS

VJitter

VDD

SCP

BO/LFF

LineFeedForward

I%VBO

VBO (EN)

BO_OK

High_Line

VBO (ON)

VHL (on)

BO_EN

BO_DIS

Rfa

ult(

cla

mp

)V

fau

lt(c

lam

p)

Fault

I fau

lt(O

TP

)

VDD

VFault (OTP)

Vfault (OVP )

V fault (EN )

SSend

Fault


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Table 1. PIN FUNCTION DESCRIPTION

Pin Name Function

1 Vs/ZCD Connected to the auxiliary winding; this pin senses the voltage output for the primary regula-tion and detects the core reset event for the Quasi−Resonant mode of operation.

2 Comp This is the error amplifier output. The network connected between this pin and the groundadjusts the regulation loop bandwidth.

3 Fault The controller enters in fault mode if the voltage of this pin is pulled above or below the faultthresholds. A precise pullup current allows direct interface with an NTC thermistor. Fault de-tection triggers a latch.

4 CS This pin monitors the primary peak current.

5 DRV The driver’s output to an external MOSFET gate.

6 GND Ground reference.

7 VCC This pin is connected to an external auxiliary voltage and supplies the controller.

8 BO/LFF Detects too low input voltage conditions (Brown−Out). Also voltage pin level is used for build-ing Line FeedForward compensation for improving Constant Current regulation tolerance.

Table 2. MAXIMUM RATINGS (Note 1)

Symbol Rating Value Unit

VCC(MAX)ICC(MAX)

Maximum Power Supply voltage, VCC pin, continuous voltageMaximum current for VCC pin

−0.3 to 28Internally limited

VmA

�VCC/�t Maximum slew rate on VCC pin during start−up phase +0.4 V/�s

Eas Single Pulse Avalanche Rating 120 mJ

VMAXIMAX

Maximum voltage on low power pins (except pins DRV and VCC)Current range for low power pins (except pins DRV and VCC)

−0.3, 5.5−2, +5

VmA

VDRV(MAX)IDRV(MAX)

Maximum driver pin voltage, DRV pin, continuous voltageMaximum current for DRV pin

−0.3, VDRV (Note 2)−300, +500

VmA

RθJ−A Thermal Resistance Junction−to−Air, 2.0 oz Printed Circuit Copper Clad 190 °C/W

TJ(MAX) Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

Human Body Model ESD Capability per JEDEC JESD22−A114F 2 kV

Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C 200 V

Charged−Device Model ESD Capability per JEDEC JESD22−C101E 500 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. This device contains latch−up protection and exceeds 100 mA per AEC−Q100−004 standard (except Comp pin − maximum negative current

80 mA at 125°C).2. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.


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Table 3. ELECTRICAL CHARACTERISTICS (VCC = 12 V, For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Max Tj = 150°C, unless otherwise noted)

Characteristics Condition Symbol Min Typ Max Unit

SUPPLY SECTION AND VCC MANAGEMENT

VCC Level at which Driving Pulsesare Authorized

VCC increasing VCC(on) 16.5 18 19.5 V

VCC Level at which Driving Pulsesare Stopped

VCC decreasing VCC(off) 6.0 6.5 7.0 V

Internal Latch/Logic Reset Level

VCC(reset) − 6.25 − V

Internal Autorecovery Reset Level (Note 4) VCC(reset_auto) 0.6 − − V

Hysteresis above VCC(off) for FastHiccup in Latch Mode

VCC(latch_hyst) − 0.2 − V

Hysteresis below VCC(off) before Latch Reset

VCC(reset_hyst) 0.15 0.30 0.50 V

Over Voltage Protection Over Voltage threshold VCC(OVP) 24 26 28 V

Start−up Supply Current, Controller Disabled or Latched

VCC < VCC(on) & VCC increasing from 0 V

ICC(start) – 4.3 7.0 �A

Internal IC Consumption, SteadyState

FSW = 65 kHzCL = 1 nF

ICC(steady) – 1.6 2.3 mA

Internal IC Consumption in Minimum Frequency Clamp

VCO mode, FSW = fVCO(min),VComp = GND

fVCO(min) = 1 kHzfVCO(min) = 200 HzCL = 1 nF

ICC(VCO)

––

325210

430370

�A

Internal IC Consumption in FaultMode (after a fault when VCC decreasing to VCC(off))

Autorecovery mode ICC(auto) – 2.0 2.2 mA

Internal IC Consumption in FaultMode (after a fault when VCC decreasing to VCC(off))

Latch mode ICC(latch) – 1.0 1.2 mA

CURRENT COMPARATOR

Current Sense Voltage Threshold

VComp = VComp(max), VCS increasing

VILIM 0.76 0.8 0.84 V

Cycle by Cycle Leading EdgeBlanking Duration

tLEB1 250 320 380 ns

Cycle by Cycle Current SensePropagation Delay

VCS > (VILIM + 100 mV) to DRV turn−off

tILIM – 50 110 ns

Timer Delay before Detecting anOverload Condition

When CS pin � VILIM(Note 3)

TOCP 50 70 90 ms

Threshold for Immediate FaultProtection Activation

VCS(stop) 1.10 1.20 1.30 V

Leading Edge Blanking Duration for VCS(stop)

tLEB2 − 120 − ns

Maximum Peak Current Level atwhich VCO Takes Over or FrozenPeak Current

VCS increasing0.6 V < VComp < 1.9 V(other possible options on demand)

VCS(VCO) − 250 − mV

Minimum Peak Current Level VCS increasingVComp < 0.2 V(other possible options on demand)

VCS(STB) − 65 − mV

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions.4. Guaranteed by Design.


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Characteristics UnitMaxTypMinSymbolCondition

REGULATION BLOCK

Internal Voltage Reference forConstant Current Regulation

TJ = 25°C−40°C < TJ < 125°C

Vref_CC 0.980.97

1.001.00

1.021.03

V

Internal Voltage Reference forConstant Voltage Regulation

TJ = 25°C−40°C < TJ < 125°C

Vref_CV1 2.4502.425

2.5002.500

2.5502.575

V

Error Amplifier Current Capability

IEA − ±40 − �A

Error Amplifier Gain GEA 150 200 250 �S

Error Amplifier Output Voltage Internal offset on Comp pin VComp(max)VComp(min)

VComp(offset)

−−−

4.90

1.1

−−−

V

Internal Current Setpoint Division Ratio

KComp − 4 − –

Valley ThresholdsTransition from 1st to 2nd ValleyTransition from 2nd to 3rd ValleyTransition from 3rd to 4th ValleyTransition from 4th Valley to VCOTransition from VCO to 4th ValleyTransition from 4th to 3rd ValleyTransition from 3rd to 2nd ValleyTransition from 2nd to 1st Valley

VComp decreasingVComp decreasingVComp decreasingVComp decreasingVComp increasingVComp increasingVComp increasingVComp increasing

VH2DVH3DVH4D

VHVCODVHVCOI

VH4IVH3IVH2I

−−−−−−−−

2.502.302.101.902.502.702.903.10

−−−−−−−−

V

Minimal Difference between anyTwo Valleys

VComp increasing or VCompdecreasing

�VH 176 − − mV

Internal Dead Time Generation forVCO Mode

Entering in VCO whenVComp is decreasing andcrosses VHVCOD

TDT(start) − 1.15 − �s


Leaving VCO mode whenVComp is increasing andcrosses VHVCOI

TDT(ends) − 650 − ns


When in VCO mode – 1−kHz option

VComp = 1.8 VVComp = 1.4 VVComp = 0.9 VVComp < 0.2 V

TDT

−−−−

1.611110

1000

−−−−

�s

Minimum Switching Frequency inVCO Mode

VComp = GNDOption 1Option 2

(other possible options ondemand)

fVCO(MIN)0.80.16

1.00.200

1.20.24

kHz

Maximum Switching FrequencyOption 1Option 2Option 3Option 4

fMAX−7299127

No Clamp80110140

−88121153

kHz

Maximum On Time Ton(max) 32 36 40 �s

DEMAGNETIZATION INPUT – ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE

VZCD Threshold Voltage VZCD decreasing VZCD(TH) 25 45 70 mV

VZCD Hysteresis VZCD increasing VZCD(HYS) 15 30 45 mV



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DEMAGNETIZATION INPUT – ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE

Threshold Voltage for OutputShort Circuit or Aux. WindingShort Circuit Detection

After tBLANK_ZCD if VZCD < VZCD(short)

VZCD(short) 30 50 75 mV

Delay after On−time that the VS/ZCD is still Pulled to Ground

When VComp > 1.7 VWhen VComp < 1.7 V

tshort_ZCD −−

0.7500.350

−−

�s

Blanking Delay after On−time (VS/ZCD Pin is Disconnected fromthe Internal Circuitry)

When VComp > 1.7 VWhen VComp < 1.7 V

tBLANK_ZCD −−

1.4500.750

−−

�s

Timeout after Last Demagnetization Transition

tout 4.0 4.5 5.0 �s

Input Leakage Current VCC > VCC(on) VZCD = 4 V,DRV is low

IZCD − − 0.1 �A

Delay from Valley Detection to DRV Low

tZCD_delay − 290 − ns

DRIVE OUTPUT − GATE DRIVE

Drive resistance DRV Sink − VCC = 8 VDRV Source − VCC = 8 V

RSNKRSRC

−−

810

−−

�

Rise time CDRV = 1 nF, from 10% to 90% tr − 45 85 ns

Fall time CDRV = 1 nF, from 90% to 10% tf − 30 65 ns

DRV Low voltage VCC = VCC(off) + 0.2 V, CDRV= 220 pF, RDRV = 33 k�

VDRV(low) 6.0 − − V

DRV High voltage VCC = VCC(OVP) − 0.2 V, CDRV= 220 pF, RDRV = 33 k�

VDRV(high) − 12.0 13.0 V

SOFT START

Internal Fixed Soft Start Duration Current Sense peak currentrising from VCS(VCO) to VILIM

tSS 3 4 5 ms

JITTERING

Frequency of the Jittering CS PinSource Current

Option 1(other possible options ondemand)

fjitter 1.2 1.5 1.8 kHz

Peak Jitter Voltage Added toPWM Comparator

Option 1(other possible options ondemand)

Vjittter − 60 − mV

BROWN−OUT & LINE FEED FORWARD

Brown−out Function is Disabledbelow this Level (before the 1st

DRV pulse only)

VBO(en) 80 100 120 mV

Pull−down Current Source on BOPin for Open Detection

IBO − 300 − nA

Brown−out Level at which the Controller Starts Pulsing

VBO(on) 0.75 0.80 0.85 V

Brown−out Level at which the Controller Stops Pulsing

VBO(off) 0.65 0.70 0.75 V

Brown−out Filter Time tBO − 50 − �s



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BROWN−OUT & LINE FEED FORWARD

Line Feed Forward CompensationGain

KLFF 16 20 24 �A/V

FAULT PROTECTION

Controller Thermal Shutdown Device switching (FSW ∼ 65 kHz) – Tj rising

TSHTDN(on) − 150 − °C

Thermal Shutdown Hysteresis Device switching (FSW ∼ 65 kHz) − Tj falling

TSHTDN(off) − 120 − °C

Fault Level Detection for OVP Internal sampled Vout increasingVOVP = Vref_CV1 + 26%

VOVP 2.95 3.15 3.35 V

Fault Level Detection for UVP →Double Hiccup Autorecovery(UVP detection is disabled duringTEN_UVP)

Internal sampled Vout decreasing

VUVP 1.40 1.50 1.60 V

Blanking Time for UVP Detection Starting after the Soft start TEN_UVP − 36 − ms

Pull−up Current Source on CS Pinfor Open or Short Circuit Detec-tion

When VCS > VCS_min ICS − 60 − �A

CS Pin Open Detection CS pin open VCS(open) − 1.2 − V

CS Pin Short Detection VCS_min − 50 75 mV

CS pin Short Detection Timer (Note 4) TCS_short − 3 − �s

Fault Pin is Disabled below thisLevel (before the 1st DRV pulseonly)

VFault(EN) 80 100 120 mV

Overvoltage Protection (OVP)Threshold

VFault increasing VFault(OVP) 2.79 3.00 3.21 V

Overtemperature Protection(OTP) Threshold

VFault decreasing VFault(OTP) 0.38 0.40 0.42 V

OTP Pull−up Current Source VFault = 0 VTj = 25°CTj = 110°C

IFault(OTP)IFault(OTP_110)

42.542.9

45.045.0

47.546.5

�A

Fault Input Clamp Voltage IFault = 0 mA (VFault = open) VFault(clamp)0 1.10 1.35 1.60 V

Fault Input Clamp Voltage IFault = 1 mA VFault(clamp)1 2.2 2.7 3.2 V

Fault Filter Time tFault(filter) − 2 − �s

Number of Drive Cycle beforeLatch Confirmation

VComp = VComp(max), VCS > VCS(stop)or Internal rebuilded Vout > VOVPor 0.40 V < VFault < 3.00 Vor VZCD(short)

tlatch(count) − 4 − −



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TYPICAL CHARACTERISTICS

I CC

(sta

rt)

(�A

)

TEMPERATURE (�C)

VC

C(r

ese

t) (

V)

TEMPERATURE (�C)

VC

C(o

ff)

(V)

TEMPERATURE (�C)

VC

C(o

n)

(V)

TEMPERATURE (�C)

Figure 4. VCC(on) vs. Junction Temperature Figure 5. VCC(off) vs. Junction Temperature

Figure 6. VCC(reset) vs. Junction Temperature Figure 7. ICC(start) vs. Junction Temperature

17.95

17.97

17.99

18.01

18.03

18.05

18.07

18.09

−50 −25 0 25 50 75 100 125

6.56

6.565

6.57

6.575

6.58

6.585

6.59

−50 −25 0 25 50 75 100 125

6.262

6.267

6.272

6.277

6.282

6.287

6.292

−50 −25 0 25 50 75 100 1252.2

2.7

3.2

3.7

4.2

4.7

5.2

−50 −25 0 25 50 75 100 125

t LE

B1 (

ns)

TEMPERATURE (�C)

VIL

IM (

V)

TEMPERATURE (�C)

Figure 8. VILIM vs. Junction Temperature Figure 9. tLEB1 vs. Junction Temperature

312

312.5

313

313.5

314

314.5

315

315.5

316

316.5

−50 −25 0 25 50 75 100 1250.794

0.796

0.798

0.8

0.802

0.804

0.806

0.808

−50 −25 0 25 50 75 100 125


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TYPICAL CHARACTERISTICS (Continued)

VC

S(S

TB

) (m

V )

VC

S(V

CO

) (m

V )

TEMPERATURE (�C)

VC

S(s

top

) (V

)

TEMPERATURE (�C)

t ILI

M (

ns)

TEMPERATURE (�C)

Figure 10. tILIM vs. Junction Temperature Figure 11. VCS(stop) vs. Junction Temperature

Figure 12. VCC(VCO) vs. Junction Temperature Figure 13. VCS(STB) vs. Junction Temperature

1.191

1.193

1.195

1.197

1.199

1.201

1.203

1.205

1.207

1.209

−50 −25 0 25 50 75 100 125

246

247

248

249

250

251

252

253

254

−50 −25 0 25 50 75 100 125

54

59

64

69

74

−50 −25 0 25 50 75 100 125

67

67.5

68

68.5

69

69.5

70

−50 −25 0 25 50 75 100 125

TEMPERATURE (�C)

2.48

2.485

2.49

2.495

2.5

2.505

2.51

−50 −25 0 25 50 75 100 125

Vre

f_C

V1 (

V)

TEMPERATURE (�C)

Vre

f_C

C (

V)

TEMPERATURE (�C)

Figure 14. Vref CC vs. Junction Temperature Figure 15. Vref CV1 vs. Junction Temperature

0.995

0.997

0.999

1.001

1.003

1.005

1.007

1.009

1.011

1.013

−50 −25 0 25 50 75 100 125


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VU

VP (

V)

TEMPERATURE (�C)

VO

VP (

V)

TEMPERATURE (�C)

VZ

CD

(sh

ort

) (m

V)

TEMPERATURE (�C)

VZ

CD

(TH

) (m

V)

TEMPERATURE (�C)

Figure 16. VZCD(TH) vs. Junction Temperature Figure 17. VZCD(short) vs. Junction Temperature

Figure 18. VOVP vs. Junction Temperature Figure 19. VUVP vs. Junction Temperature

43

43.5

44

44.5

45

45.5

46

46.5

47

47.5

48

−50 −25 0 25 50 75 100 12553.2

53.7

54.2

54.7

55.2

55.7

56.2

56.7

57.2

57.7

−50 −25 0 25 50 75 100 125

3.12

3.13

3.14

3.15

3.16

3.17

−50 −25 0 25 50 75 100 1251.54

1.545

1.55

1.555

1.56

-50 -25 0 25 50 75 100 125

VB

O(o

n)

(V)

TEMPERATURE (�C)

TE

N_

UV

P (

ms)

TEMPERATURE (�C)

Figure 20. TEN UVP vs. Junction Temperature Figure 21. VBO(on) vs. Junction Temperature

36.02

36.07

36.12

36.17

36.22

36.27

36.32

−50 −25 0 25 50 75 100 1250.835

0.836

0.837

0.838

0.839

0.84

−50 −25 0 25 50 75 100 125


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VF

au

lt(O

VP

) (V

)

TEMPERATURE (�C)

VF

au

lt(E

N)

(mV

)

TEMPERATURE (�C)

KLF

F (�

A/V

)

TEMPERATURE (�C)

VB

O(o

ff)

(V)

TEMPERATURE (�C)

Figure 22. VBO(off) vs. Junction Temperature Figure 23. KLFF vs. Junction Temperature

Figure 24. VFault(EN) vs. Junction Temperature Figure 25. VFault(OVP) vs. Junction Temperature

0.685

0.687

0.689

0.691

0.693

0.695

−50 −25 0 25 50 75 100 12521.47

21.49

21.51

21.53

21.55

21.57

21.59

21.61

21.63

−50 −25 0 25 50 75 100 125

100.5

101.5

102.5

103.5

104.5

105.5

106.5

-50 -25 0 25 50 75 100 125

2.966

2.971

2.976

2.981

2.986

2.991

2.996

3.001

3.006

3.011

−50 −25 0 25 50 75 100 125

I Fa

ult

(OT

P)

(�A

)

TEMPERATURE (�C)

VF

au

lt(O

TP

) (V

)

TEMPERATURE (�C)

Figure 26. VFault(OTP) vs. Junction Temperature Figure 27. IFault(OTP) vs. Junction Temperature

0.398

0.399

0.4

0.401

0.402

0.403

0.404

0.405

0.406

0.407

−50 −25 0 25 50 75 100 12544.4

44.5

44.6

44.7

44.8

44.9

45

45.1

45.2

45.3

−50 −25 0 25 50 75 100 125


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Table 4. FAULT MODES

Event Timer Protection Next Device Status Release to Normal Operation Mode

OvercurrentVCS > VILIM

OCP Timer Double Hiccup − Resume to normal operation: if 4 pulses fromFB Reset & then Reset timer

− Resume operation after Double Hiccup

Winding ShortVCS > VCS(stop)

4 Consecutive Pulses with VCS > VCS(stop)

Double Hiccup Resume operation after Double Hiccup

CS Pin Fault:Short & Open

Before Start−upImmediate

Double Hiccup Resume operation after Double Hiccup

ZCD ShortVZCD < VZCD(short) after

tBLANK_ZCD time

4 Consecutive Pulses Double Hiccup Resume operation after Double Hiccup

Low SupplyVCC < VCC(off)

10−�s Timer Simple Hiccup Resume operation after Simple Hiccup

High SupplyVCC > VCC(ovp)

10−�s Timer Double Hiccup Resume operation after Double Hiccup

Internal VoutOVP: Vout > 126% Vref_CV1


Internal VoutUVP: Vout < 60% Vref_CV1,

when Vout is Decreasing Only


Internal TSD 10−�s Timer Double Hiccup Resume operation after Double Hiccup & T < (TSHTDN(off))

NOTE: Latching off protection available upon request.


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APPLICATION INFORMATION

The NCV1362 is a flyback power supply controllerproviding a means to implement primary side constant−current regulation and secondary side constant−voltageregulation. NCV1362 implements a current−modearchitecture operating in quasi−resonant mode. Thecontroller prevents valley−jumping instability and steadilylocks out in a selected valley as the power demand goesdown. As long as the controller is able to detect a valley, thenew cycle or the following drive remains in a valley. Thanksto a dedicated valley detection circuitry operating at any lineand load conditions, the power supply efficiency will alwaysbe optimized. In order to prevent any high switchingfrequency two frequency clamp options are available.• Quasi−Resonance Current−mode Operation:

implementing quasi−resonance operation in peakcurrent−mode control optimizes the efficiency byswitching in the valley of the MOSFET drain−sourcevoltage. Thanks to a proprietary circuitry, the controllerlocks−out in a selected valley and remains locked untilthe input voltage significantly changes. Only the fourfirst valleys could be locked out. When the load currentdiminishes, valley switching mode of operation is keptbut without valley lock−out. Valley−switchingoperation across the entire input/output conditionsbrings efficiency improvement and lets the designerbuild higher−density converters.

• Frequency Clamp: As the frequency is not fixed anddependent on the line, load and transformerspecifications, it is important to prevent switchingfrequency runaway for applications requiring maximumswitching frequencies up to 90 kHz or 130 kHz. Threefrequency clamp options at 80 kHz, 110 kHz or140 kHz are available for this purpose. In casefrequency clamp is not needed, a specific version of theNCV1362 exists in which the clamp is deactivated.

• Primary Side Constant Current Regulation: NCV1362controls and regulates the output current at a constantlevel regardless of the input and output voltageconditions. This function offers tight over powerprotection by estimating and limiting the maximumoutput current from the primary side, without anyparticular sensor.

Figure 28. Constant−Voltage & Constant−CurrentMode

CV Mode

CC Mode

IOUTINOM

VOUT

VNOM

0

• Soft−Start: 4−ms internal fixed soft start guaranteesa peak current starting from zero to its nominal valuewith smooth transition in order to prevent anyoverstress on the power components at each startup.

• Cycle−by−Cycle Peak Current Limit: If the max peakcurrent reaches the VILIM level, the over currentprotection timer is enabled and starts counting. If theoverload lasts TOCP delay, then the fault is detected andthe controller stops immediately driving the powerMOSFET. The controller enters in a double hiccupmode before autorecovering with a new startup cycle.

• VCC Over Voltage Protection: If the VCC voltagereaches the VCC(OVP) threshold the controller enters infault mode. Thus it stops driving pulse on DRV pin.The part enters in double hiccup mode before resumingoperation.

• Winding Short−Circuit Protection: An additionalcomparator senses the CS signal and stops thecontroller if VCS reaches VILIM + 50% (after a reducedLEB: tLEB2). Short circuit protection is enabled only if4 consecutive pulses reach SCP level. This smallcounter prevents any false triggering of short circuitprotection during surge test for instance. This fault isdetected and operations will be resumed like in a caseof VCC Over Voltage Protection.

• Vout Over Voltage Protection: if the internally−builtoutput voltage becomes higher than VOVP level(Vref_CV1 + 26%) a fault is detected. This fault isdetected and operations are resumed like in the VCC Over Voltage Protection case.

• Vout Under Voltage Protection: After each circuit poweron sequence, Vout UVP detection is enabled only afterthe startup timer TEN_UVP. This timer ensures that thepower supply is able to fuel the output capacitor beforechecking the output voltage in on target. After thisstartup blanking time, UVP detection is enabled andmonitors the Output voltage level. When the powersupply is running in constant−current mode and whenthe output voltage falls below VUVP level, the controllerstops sending drive pulses and enters a double hiccupmode before resuming operations.

• VS/ZCD Pin Short Protection: at the beginning of eachoff−time period, the VS/ZCD pin is tested to checkwhether it is shorted or left open. In case a fault isdetected, the controller enters in a double hiccup modebefore resuming operations.

• EMI Jittering: a low−frequency triangular voltagewaveform is added to the CS pin. This helps spreadingout energy in conducted noise analysis. Jittering isdisabled in frequency foldback mode.

• Frequency Foldback: In frequency foldback mode, the system reduces the switching frequency by addingsome dead−time after the 4th valley is detected.


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The controller will still run in valley switching modeeven when the FF is enabled.

• Temperature Shutdown: if the junction temperaturereaches the TSHTDN level, the controller stop driving thepower MOSFET until the junction temperaturedecreases to TSHTDN(off), then the operation is resumedafter a double hiccup mode.

• Brown−Out Detection: BO pin monitors bulk voltagelevel via resistive divider and thus assures that theapplication is working only for designed bulk voltages.When BO pin is grounded before start−up (VBO < VBO(en)), Brown−Out, Line FeedForward anddynamic frequency clamp are disabled.

• Line FeedForward: By monitoring the voltageavailable on BO pin it is possible to create a linefeedforward compensation in order to improve theconstant current accuracy.

• Fault Input: the NCV1362 includes a dedicated faultinput. It can be used to sense an overvoltage conditionand latch off the controller by pulling up the pin abovethe upper fault threshold, VFault(OVP), typically 3.0 V.The controller is also disabled if the Fault pin voltage,VFault, is pulled below the lower fault threshold,VFault(OTP), typically 0.4 V. The lower threshold isnormally used for detecting an overtemperature fault(by the means of an NTC). If this pin is groundedbefore start−up, then its associated feature are disabled.


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DETAILED APPLICATION INFORMATION

Start−up SequenceThe NCV1362 start−up voltage is made purposely high to

permit large energy storage in a small VCC capacitor value.This helps operate with a small start−up current which,together with a small VCC capacitor, will not hamper the

start−up time. To further reduce the standby power, thestart−up current of the controller is extremely low (seeICC(start)). The start−up resistor can therefore be connectedto the bulk capacitor or directly to the mains input voltage tofurther reduce the power dissipation.

Figure 29. The Startup Resistor can be Connected to the Input Mains for Further Power Dissipation Reduction

InputMains

Aux.Winding

VCC

RStart−up

CbulkCVCC

The first step starts with the calculation of the needed VCCcapacitor which will supply the controller when it operatesuntil the auxiliary winding takes over. Experience showsthat this time t1 can be between 5 ms and 20 ms. If weconsider we need at least an energy reservoir for a t1 time of10 ms, the VCC capacitor must be larger than:

CVCC�

ICC � t1

VCC(on) � VCC(off)

�1.6 m � 10 m

18 � 6.5� 1.4 �F (eq. 1)

Let us select a 1.5 �F capacitor at first and experiments inthe laboratory will let us know if we were too optimistic forthe time t1. The VCC capacitor being known, we can nowevaluate the charging current we need to bring the VCCvoltage from 0 V to the VCC(on) of the IC. This current hasto be selected to ensure a start−up at the lowest mains (85 Vrms) to be less than 3 s (2.5 s for design margin):

Icharge �VCC(on) � CVcc

tstart−up�

18 � 1.5 �

2.5� 11 �A (eq. 2)

If we account for the ICC(start) = 7.0 �A (maximum) thatwill flow inside the controller, then the total charging currentdelivered by the start−up resistor must be 18 �A. If weconnect the start−up network to the mains (half−waveconnection then), we know that the average current flowinginto this start−up resistor will be the smallest when VCCreaches the VCC(on) of the controller:

ICVcc,min �

Vac,rms 2�

�� VCC(on)

Rstart−up

(eq. 3)

To make sure this current is always greater than 18 �A,then the minimum value for Rstart−up can be extracted:

Rstart−up �

85 2�

�� 18

18 �� 1.13 M� (eq. 4)

This calculation is purely theoretical, consideringa constant charging current. In reality, the take over time canbe shorter (or longer!) and it can lead to a reduction of theVCC capacitor. Thus, a decrease in charging current and anincrease of the start−up resistor can be experimentallytested, for the benefit of standby power. Laboratoryexperiments on the prototype are thus mandatory to fine tunethe converter. If we chose the 1.2−M� resistor as suggestedby Eq. 4, the dissipated power at high line amounts to:

PRstart−up,max�

Vac,peak2

4 � Rstart−up�230 � 2�

2

4 � 1.1 M� 24 mW (eq. 5)

Primary Side Regulation: Constant Current OperationFigure 30 portrays idealized primary and secondary

transformer currents of a flyback converter operating inDiscontinuous Conduction Mode (DCM).


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Figure 30. Primary and Secondary Transformer Current Waveforms

Ip(t)

Is(t), IOUT

IOUT = <Is(t)>

,,

p pks pk

I

ps

IN

=

,pI pk

tdemagtsw

time

timeton

When the primary power MOSFET is turned on, theprimary current is illustrated by the green curve ofFigure 30. When the power MOSFET is turned off theprimary side current drops to zero and the current into thesecondary winding immediately rises to its peak value equalto the primary peak current divided by the primary tosecondary turns ratio. This is an ideal situation in which theleakage inductance action is neglected.

The output current delivered to the load is equal to theaverage value of the secondary winding current, thus we canwrite:

Iout � ⟨isec(t)⟩ �Ip,pk

2Nps�

tdemag

tsw(eq. 6)

Where:• tSW is the switching period

• tdemag is the demagnetizing time of the transformer

• NPS is the secondary to primary turns ratio, where NP & NS are respectively the transformer primary andsecondary turns:

Nps �Ns

Np(eq. 7)

• Ip,pk is the magnetizing peak current sensed across thesense resistor on CS pin:

Ip,pk �VCS

Rsense(eq. 8)

Internal constant current regulation block is building theconstant current feedback information as follow:

VFB_CC � Vref_CC �tSW

tdemag(eq. 9)

As the controller monitors the primary peak current viathe sense resistor and due to the internal current setpointdivider (Kcomp) between the CS pin and the internalfeedback information, the output current could be written asfollow:

Iout �Vref_CC

8Nps � Rsense(eq. 10)

The output current value is set by choosing the senseresistor value:

Rsense �Vref_CC

8Nps � Iout

(eq. 11)

Primary Side Regulation: Constant Voltage OperationIn primary side constant voltage regulation, the output

voltage is sensed via the auxiliary winding. During theon−time period, the energy is stored in the transformer gap.During the off−time this energy stored in the transformer isdelivered to the secondary and auxiliary windings.

As illustrated by Figure 31, when the transformer energyis delivered to the secondary, the auxiliary voltage sums theoutput voltage scaled by the auxiliary and secondary turnsratios and the secondary forward diode voltage. Thissecondary forward diode voltage could be split in twoelements: the first part is the forward voltage of the diode(Vf), and the second is related to the dynamic resistance ofthe diode multiplied by secondary current (RD � IS(t)).Where this second term will be dependant of the load andline conditions.


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Figure 31. Typical Idealized Waveforms of a Flyback Transformer in DCM

0V

p a

IN

N

ps

VN

�

paout

N

ps

VN

VAUX(t) ( )secpa

out f

N

ps

V V IN

+

time

tdemag

tsw

time

time

,,

p pks pk

I

ps

IN

=

,pI pk

ton

Ip(t)

Is(t), IOUT

IOUT = <Is(t)>

To reach an accurate primary−side constant−voltageregulation, the controller detects the end of thedemagnetization time and precisely samples output voltagelevel seen on the auxiliary winding. As this momentcoincides with the secondary−side current equal to zero, thediode forward voltage drop becomes independent from theloading conditions.

Thus when the secondary current Is(t) reaches zeroampere, the auxiliary is sensed:

Vaux � Vout �Npa

Nps(eq. 12)

Where: Npa is the auxiliary to primary turns ratio, where Np& Na are respectively the primary and auxiliary turns:

Npa �Na

Np(eq. 13)

Figure 32 illustrates how the constant voltage feedbackhas been built. The auxiliary winding voltage must be scaleddown via the resistor divider to Vref_CV1 level beforebuilding the constant voltage feedback error.

Vref_CV1 �Rs2

Rs1 � Rs2

� Vaux (eq. 14)

By inserting Eg. 12 into Eq. 14 we obtain the followingequation:

Vref_CV1 �Rs2

Rs1 � Rs2

�Npa

Nps� Vout (eq. 15)

Once the sampled Vout is applied to the negative inputterminal of the operational transconductance amplifier(OTA) and compared to the internal voltage reference anadequate voltage feedback is built. The OTA output beingpinned out, it is possible to compensate the converter andadjust step load response to what the project requires.

Figure 32. Constant Voltage Feedback Arrangement

Vs / ZCDComp

OTA

Zero Crossing &

Signal Sampling

Sampled Vout

FB_CV

Aux

iliar

y R s1

R s2

V ref_CV1

R1

C1C2

tShort_ZCD

t Blank_ZCD


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When the power MOSFET is released at the end of the ontime, because of the transformer leakage inductance and thedrain lumped capacitance some voltage ringing appears onthe drain node. These voltage ringings are also visible on theauxiliary winding and could cheat the controller detectioncircuits. To avoid false detection operations, two protectingcircuits have been implemented on the VS/ZCD pin (seeFigure 33):

1. An internal switch grounds the VS/ZCD pin durington + tshort_ZCD in order to protect the pin fromnegative voltage.

2. In order to prevent any misdetection from the zerocrossing block an internal switch disconnectsVS/ZCD pin until tblank_ZCD time ends.

Figure 33. VS/ZCD Pin Waveforms

Constant−Current and Constant−Voltage OverallRegulation

As already presented in the two previous paragraphs, thecontroller integrates two different feedback loops: the firstone deals with the constant−current regulation scheme whilethe second one builds the constant−voltage regulation. Oneof the two feedback paths sets the primary peak current intothe transformer. During startup phase, however, the peakcurrent is controlled by the softstart.

Zero Current DetectionThe NCV1362 integrates a quasi−resonant (QR) flyback

controller. The power switch turn−off of a QR converter isdetermined by the peak current whose value depends on thefeedback loop. The switch restart event is determined by thetransformer demagnetization end. The demagnetization end

is detected by monitoring the transformer auxiliary windingvoltage. Turning on the power switch once the transformeris demagnetized (or reset) reduces turn−on switching losses.Once the transformer is demagnetized, the drain voltagestarts ringing at a frequency determined by the transformermagnetizing inductance and the drain lumped capacitance,eventually settling at the input voltage value. A QRcontroller takes advantage of the drain voltage ringing andturns on the power switch at the drain voltage minimum or“valley” to reduce turn−on switching losses andelectromagnetic interference (EMI).

As sketched by Figure 34, a valley is detected once theZCD pin voltage falls below the QR flybackdemagnetization threshold, VZCD(TH), typically 45 mV.The controller will switch once the valley is detected orincrement the valley counter depending on FB voltage.

Figure 34. Valley Lockout Detection Circuitry Internal Schematic

Rs1

Rs2

ZCD

Timeout − tout

QR multi−modeValley lockout &

Valley Switching &VCO management

BlankingTblank_ZCD

S

R

Q

DRV(Internal)

VZCD(TH)


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TimeoutThe ZCD block actually detects falling edges of the

auxiliary winding voltage applied to the ZCD pin. Atstart−up or during other transient phases, the ZCDcomparator may be unable to detect such an event. Also, inthe case of extremely damped oscillations, the system maynot succeed in detecting all the valleys required by valleylockout operation (VLO, see next section). In this condition,the NCV1362 ensures continued operation by incorporatinga maximum timeout period that resets itself when ademagnetization phase is properly detected. In case theringing signal is too weak or heavily damped, the timeoutsignal supersedes the ZCD signal for the valley counter.Figure 34 shows the timeout period generator circuitschematic. The timeout duration, tout, is set to 4.5 �s (typ.).

In VLO operation, the timeout occurrences are countedinstead of valleys when the drain−source voltageoscillations are too damped to be detected. For instance,assume the circuit must turn on at the third valley and theZCD ringing only enables the detection of:• Valleys #1 to #2: the circuit generates a DRV pulse tout

(steady−state timeout delay) after valley #2 detection.• Valley #1: the timeout delay must run twice so that the

circuit generates a DRV pulse 9 �s (2 × tout typ.) aftervalley #1 detection.

Valley LockOut (VLO) and Frequency Foldback (FF)The operating frequency of a traditional Quasi−Resonant

(QR) flyback controller is inversely proportional to thesystem load. In other words, a load reduction increases theoperating frequency. A maximum frequency clamp can beuseful to limit the operating frequency range. However,when associated with a valley−switching circuit,instabilities can arise because of the discrete frequencyjumps. The controller tends to hesitate between two valleysand audible noise can be generated

To avoid this issue, the NCV1362 incorporatesa proprietary valley lockout circuitry which preventsso−called valley jumping. Once a valley is selected, thecontroller stays locked in this valley until the input level oroutput power changes significantly. This technique extendsQR operation over a wider output power range whilemaintaining good efficiency and naturally limiting themaximum operating frequency.

The operating valley (from 1st to 4th valley) is determinedby the internal feedback level (Internal FB node onFigure 3). As FB voltage level decreases or increases, thevalley comparators toggle one after another to select theproper valley.The decimal counter increases each time a valley is detected.The activation of an “n” valley comparator blanks the “n−1”or “n+1” valley comparator output depending if VFBdecreases or increases, respectively. Figure 35 showsa typical frequency characteristic obtained at low line ina 10−W charger.

Figure 35. Typical Switching Frequency vs. Output Power Relationship in a 10−W Adapter

0 1 2 3 4 5 6 7 8 9 10

Fsw versus Pout at VINlow

Pout (W)

Fsw

(H

z)

1st2nd3rd4th5th

FrequencyFoldback

Mode

1st2nd3rd4th5th

Frequency FoldbackMode

VLO mode

VLO mode

Fsw vs. Pout, when Pout is �

Fsw vs. Pout, when Pout

0

2.5 × 104

5.0 × 104

7.5 × 104

1.0 × 105

� is

When an “n” valley is asserted by the valley selectioncircuitry, the controller locks in this valley until the FBvoltage decreases to the lower threshold (“n+1” valleyactivates) or increases to the “n valley threshold” + 600 mV(“n−1” valley activates). The regulation loop adjusts the

peak current to deliver the necessary output power at thevalley operating point. Each valley selection comparatorfeatures a 600−mV hysteresis that helps stabilize operationdespite the FB voltage swing produced by the regulationloop.


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Table 5. VALLEY FB THRESHOLD ON CONSTANT VOLTAGE REGULATION

FB Falling FB Rising

1st to 2nd Valley 2.5 V FF Mode to 4th 2.5 V

2nd to 3rd Valley 2.3 V 4th to 3rd Valley 2.7 V

3rd to 4th Valley 2.1 V 3rd to 2nd Valley 2.9 V

4th to FF Mode 1.9 V 2nd to 1st Valley 3.1 V

Frequency Foldback (FF)As the output current decreases (FB voltage decreases),

the valleys are incremented from 1 to 4. In case the fourthvalley is reached, the FB voltage further decreases below1.9 V and the controller enters the frequency foldback mode(FF). The current setpoint being internally forced to remainabove VCS(VCO) (setpoint corresponding to VComp), thecontroller regulates the power delivery by modulating theswitching frequency. When an output current increasecauses FB to exceed the 2.5−V FF upper threshold (600−mVhysteresis), the circuit recovers VLO operation.

In frequency foldback mode, the system reduces theswitching frequency by adding some dead−time after the 4th

valley is detected. However, in order to keep the high

efficiency benefit inherent to the QR operation, thecontroller turns on again with the next valley after the deadtime has ended. As a result, the controller will still run invalley switching mode even when the FF is enabled. Thisdead−time increases when the FB voltage decays. There isno discontinuity when the system transitions from VLO toFF and the frequency smoothly reduces as FB goes below1.9 V.

The dead−time is selected to generate a 1.15−�sdead−time when VComp is decreasing and crossing VHVCOD(1.9 V typ.). At this moment, it can linearly go down to theminimal frequency limit. The generated dead−time is 650 nswhen VComp is increasing and crossing VHVCOI (2.5 V typ.).

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

Figure 36. Valley Lockout Threshold

1.9 2.1 2.3 2.5 2.7 2.9 3.1

Pout decreasing

Pout Increasing

4.3 V

VCO

4th Valley

3rd Valley

2nd Valley

1st Valley

Max PeakCurrent

Clamped toVCS = VILIM

OperatingMode

VComp

Stand−by ModeAn high frozen peak current is necessary to have good

efficiency at 10% of the load. On the other hand, the standbyperformance will not be optimized. Indeed, in no loadcondition, the switching frequency has to be high enough tohave a good transient response and then keep the outputvoltage within the limits. If we set a minimum switchingfrequency, the only parameter that can be adjusted to deliverless power is the primary peak current as shown in Eq. 16.

Pout �12� Ip,pk

2� fSW � � (eq. 16)

The NCV1362 implements a peak control mode when theload is closed to 0. From frozen peak current in FF mode(250 mV here), the maximum voltage threshold on CS pinis reduced to 65 mV when the Comp voltage crossed0.260 V. If the 65−mV threshold is reached in 200 ns forinstance due to small primary inductance, the minimum ONtime will be defined by the 320−ns leading edge blankingduration and the propagation delay (50 ns) so 370 nstypically.


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Figure 37. Frequency Foldback and Standby Mode Behavior with 1−kHz Minimum Frequency Clamp, VCS(VCO) = 250 mV and VCS(STB) = 65 mV

Current SetpointAs explained in this operating description, the current

setpoint is affected by several functions. Figure 38summarizes these interactions. As shown by this figure, thecurrent setpoint is the output of the control law divided byKcomp (4 typ.). This current setpoint is clamped by thesoft−start slope as long as the peak current requested by theFB_CV or FB_CC level are higher. The softstart clamp isstarting from the frozen peak current (VCS(VCO)) to VILIM(0.8 V typ.) within 4 ms (tss).

However, this internal FB value is also limited by thefollowing functions:

• A minimum setpoint is forced that equals VCS(VCO)(250 mV, typ.) when 0.760 V < Vcomp < 1.9 V

• A second minimum setpoint is forced that equalsVCS(STB) (65 mV, typ.) when Vcomp < 0.260 V

• The peak current is linearly reduced between this twoprevious frozen peak current (VCS(VCO) & VCS(STB))

• In addition, a second OCP comparator ensures that inany case the current setpoint is limited to VILIM. Thisensures the MOSFET current setpoint remains limitedto VILIM in a fault condition.

Figure 38. Current Setpoint

FB Reset

Max_Ipk reset

OCPTimer

Count

Reset Timer

LEB1

CS

VILIM

POReset

DbleHiccup

LEB2

VCS(Stop)

4 clkCounter

ResetCounter

OCP

1/Kcomp

SCP

Control LawFor

Primary PeakCurrent Control

SoftStart

FB_CV

FB_CC

PWMLatchReset

PWM Comp

OCPComp

Short CircuitComp

Rsense

RCS

CCS

Peak CurrentControlComp


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A 2nd Over−Current Comparator for AbnormalOvercurrent Fault Detection

A severe fault like a winding short−circuit can cause theswitch current to increase very rapidly during the on−time.The current sense signal significantly exceeds VILIM. But,because the current sense signal is blanked by the LEBcircuit during the switch turn on, the power switch currentcan abnormally increase, possibly causing system damages.The NCV1362 protects against this dangerous mode byadding an additional comparator for abnormal overcurrentfault detection or short−circuit condition. The current sensesignal is blanked with a shorter LEB duration, tLEB2,typically 120 ns, before applying it to the short−circuitcomparator. The voltage threshold of this extra comparator,VCS(stop), is typically 1.2 V, set 50% higher than VILIM. Thisis to avoid interference with normal operation. Four

consecutive abnormal overcurrent faults cause thecontroller to enter in auto−recovery mode. The count to 4provides noise immunity during surge testing. The counteris reset each time a DRV pulse occurs without activating thefault overcurrent comparator or after double hiccupsequence or if the power supply is unplugged with a newstartup sequence after the initial power on reset.

Jittering CapabilityIn order to help meet the EMI requirements, the NCV1362

features the jittering capability to average the spectrum raysover the frequency range. The function consists of adding avoltage ripple to the peak current information in order tochange the operation frequency. The peak−to−peakamplitude of the ripple waveform is 60 mV at 1.5 kHz.

Figure 39. Frequency Jittering

VDD

VJitter

CS

RLFFRSense

To CSComparator

VCS

Time

Fjitter

Vjitter

Fault Mode and Protection• CS Pin: at each startup, a 60−�A (ICS) current source

pulls up the CS pin to disable the controller if the pin isleft open or grounded. Then the controller enters ina double hiccup mode.

• VS/ZCD Pin: after sending the first drive pulse thecontroller checks the correct wiring of VS/ZCD pin:after the ZCD blanking time, if there is an open or shortconditions, the controller enters in double hiccup mode.

Brown−out FunctionThe Brown−out circuitry offers a way to protect the

application from operation under too low input voltage. Thecontroller allows the output pulses, only if the input voltageis above VBO(on) level. An extra comparator detects if the BOpin is grounded for disabling the BO feature. The internalcircuitry, depicted by Figure 40, offers a way to observe thebulk voltage.

Figure 40. Internal Brown−out Configuration

VBO(EN)

BO_OK

VBO(ON)

BO_EN1 �s

Filter

BO_DIS

BO/LFFRupper

RlowerCBO

Vbulk

IBO

Start−up

Sample& Hold

50 �s

Filter

1 �s Filter

STB mode

IBO_en


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The following figures illustrate the behavior of theBrown−out pin:

Figure 41. Brown−out Input Functionality − VCC < VCC(on)

VCC

Time

VCC(on)

VCC(off)

VBO

Time

VBO(on)

VBO(off)

DRV

Time

Figure 42. Brown−out Input Functionality − VCC > VCC(on)

VCC

Time

VCC(on)

VCC(off)

VBO

Time

VBO(on)

VBO(off)

DRV

Time


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Calculation of the resistors divider:

Rlower � Rupper �VBO(on)

Vbulk � VBO(on)

(eq. 17)

If the power supply must start pulsing at Vin = 80 V rms(Vbulk = 113 V) with a selected Rupper = 10 M�:

Rlower � 10 M �0.8

113 � 0.8� 71.2 k� (eq. 18)

With a selected 71.5−k� normalized ±1% resistor forRlower, it is now possible to calculate all the bulk levelsversus the internal voltage references of the BO pin.

Table 6. EXAMPLE OF BROWN−OUT LEVELS WITH Rlower = 71.5 k� & Rupper = 10 M�

Parameters BO Pin Level (V) Bulk Level (V) Vin Level (V rms)

VBO(en) 0.1 14.0 10

VBO(on) 0.8 112.7 79.7

VBO(off) 0.7 98.6 69.7

These resistances have to be adjusted after measurementsaccording to the bulk capacitor ripple and also the capacitorconnected on the BO pin.

There is the possibility for the customer to disable the BOprotection if this function is not needed. To implement thisfeature, the BO pin voltage is checked when VCC crossesVCC(on) threshold. If the BO voltage is still below VBO(EN)after the VCC(on), the BO function is disabled.

Line Feed ForwardSensing input line voltage via BO pin allows to generate

a current to CS pin directly proportional to the input linelevel in order to compensate the over current on CS pin dueto the propagation delay. The resistor in series with the CSpin adjusts the compensation level.

Figure 43. Internal Line Feed Forward Configuration

V BO(on)Rlower

Rupper

C BO

V bulk

BO/LFF+

V

−k LFF *V

RSense

VDD

CS

RLFF

ILFF

Figure 44. Transfer Function of the Line Feed Forward

KLFF = 20 �A/V

ILFF

VBO(on) 3.4 V0 �A

52 �A


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Calculation of the resistor (RLFF) for compensating theoverpower.

Let’s assume the power supply needs to havea compensation of 45 mV (VLFF) at 265 V rms (Vin).

First, it is needed to calculate what is the BO levelcorresponding to the line voltage (here 265 V rms) of thedesired compensation level:

VBO_LFF � Vbulk �Rlower

Rlower � Rupper(eq. 19)

Then, the resistor value to be inserted between the CSresistor and CS pin could be calculated, as illustrated hereafter:

RLFF �VLFF

KLFF � VBO_LFF � VBO(on)

(eq. 20)

Numerical application yields:

VBO_LFF � 265 2� �71.5 k

71.5 k � 10 M� 2.66 V (eq. 21)

RLFF �45 mV

20�AV

� (2.66 V � 0.8 V)� 1.2 k� (eq. 22)

The offset voltage can affect the standby powerperformance by reducing the peak current setpoint inlight−load conditions. For this reason, it is desirable tocancel its action as soon as the VCO mode occurs. A typicalcurve variation is shown in Figure 45. At low power, belowthe VCO mode starting point, the LFF current is linearlyabsorbed and no offset is created through the CS pin whenthe Comp pin voltage is below 1.6 V. When feedbackincreases again and reaches the 1.6−V threshold, OPP startsto build up and reaches its full value at 1.9 V.

Figure 45. The LFF Current is Applied when the Comp Voltage Exceeds 1.6 V. It is 0 below it

max

1.9 V

1.6 V

100

0 t

t

VCompIncreases

VCompDecreases

Fault InputThe NCV1362 includes a dedicated fault input accessible

via the Fault pin. Figure 46 shows the architecture of theFault input. The controller can be latched by pulling up thepin above the upper fault threshold, VFault(OVP), typically3.0 V. An active clamp prevents the Fault pin voltage fromreaching the VFault(OVP) if the pin is open. To reach the upperthreshold, the external pull−up current has to be higher thanthe pull−down capability of the clamp.

VFault(OVP) � VFault(clamp)

RFault(clamp)

�3 V � 1.35 V

1.35 k�,

(eq. 23)

i.e. approximately 1.2 mA.

This function is typically used to detect a VCC or auxiliarywinding overvoltage by means of a Zener diode generally inseries with a small resistor (see Figure 46).

Neglecting the resistor voltage drop, the OVP threshold isthen:

VAUX(OVP) � VZ � VFault(OVP) (eq. 24)

where VZ is the Zener diode voltage.

The controller can also be latched off if the Fault pinvoltage, VFault, is pulled below the lower fault threshold,VFault(OTP), typically 0.4 V. This capability is normally usedfor detecting an overtemperature fault by means of an NTC


NCV1362

www.onsemi.com27

thermistor. A pull up current source IFault(OTP), (typically45 �A) generates a voltage drop across the thermistor. Theresistance of the NTC thermistor decreases at highertemperatures resulting in a lower voltage across thethermistor. The controller detects a fault once the thermistorvoltage drops below VFault(OTP).

The circuit detects an overtemperature situation when:

RNTC � IFault(OVP) � VFault(OVP) (eq. 25)

Hence, the OTP protection trips when

RNTC �VFault(OVP)

IFault(OTP)

(eq. 26)

that is 8.9 k� typically.The controller bias current is reduced during power up by

disabling most of the circuit blocks including IFault(OTP).This current source is enabled once VCC reaches VCC(on).A bypass capacitor is usually connected between the Faultand GND pins. It will take some time for VFault to reach itssteady state value once IFault(OTP) is enabled. Therefore, thelower fault comparator (i.e. overtemperature detection) isignored during soft−start.

Figure 46. Fault Detection Schematic

Rfault(clamp)

Vfault(clam

p)

Fault

Ifault(OT

P)

VDD

VFault(OTP)

VFault(OVP)

VFault(EN)

Clock

FaultNTC

VZ

Vaux

S

RQ

Latch

BO_DISVCC(Reset)

BO_ENBO_NOK

2 �s

Blanking

2 �s

Blanking

SSend

Up Counter

Reset4

OVP/OTP gone

Fault pindisabled

1 �s

Filter

Start−up

Sample& Hold

As a matter of fact, the controller operates normally whilethe Fault pin voltage is maintained within the upper andlower fault thresholds. Upper and lower fault detector haveblanking delays to prevent noise from triggering them. BothOVP and OTP comparator output are validated only if itshigh−state duration lasts a minimum of 2 �s. Below thisvalue, the event is ignored. Then, a counter ensures thatOVP/OTP events occurred for 4 successive drive clockpulses before actually latching the part.

When the part is latched−off, the drive is immediatelyturned off and VCC goes in endless hiccup mode. The powersupply needs to be un−plugged to reset the part as a result ofa BO_NOK (BO fault condition) if Brown−Out feature isenabled otherwise VCC(Reset).

There is the possibility for the customer to disable the faultpin protection if this function is not needed or to reduce theIC consumption in stand−by mode. To implement this

feature, the fault pin voltage is checked when VCC crossesVCC(on) threshold. If the voltage is still below VFault(EN)after the VCC(on), the fault pin is disabled.

Thermal ShutdownAn internal thermal shutdown circuit monitors the

junction temperature of controller die of the IC. Thecontroller is disabled if its junction temperature exceeds thethermal shutdown threshold (TSHDN). A continuous VCChiccup is initiated after a thermal shutdown fault is detected.The controller restarts at the next VCC(on) once the ICtemperature drops below TSHDN reduced by the thermalshutdown hysteresis (TSHDN(off)). The thermal shutdown isalso cleared if VCC drops below VCC(reset). A new power upsequences commences at the next VCC(on) once all the faultsare removed.


NCV1362

www.onsemi.com28

Table 7. ORDERING TABLE OPTION

OPN #NCV1362_ _

Minimum SwitchingFrequency in VCO Mode (kHz) Maximum Switching Frequency (kHz) Jittering Frequency

0.2 1 No 80 110 140 Enable Disable

NCV1362AADR2G x x x

NCV1362ABDR2G x x x

NCV1362ACDR2G x x x

Table 8. ORDERING INFORMATION

Device Device Marking Package Shipping†

NCV1362AADR2G V1362AASOIC−8

(Pb−Free) 2500 / Tape & ReelNCV1362ABDR2G V1362AB

NCV1362ACDR2G V1362AC

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.


SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

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SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

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ncv1362 - automotive primary side flyback controller

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