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NEAR IST-2001-32300

Nanoscale electronic elements and circuits for operation at room temperature

Final Report

Covering period 1.1.2002-31.12.2004

Report Version: Final Report Preparation Date: 26 January 2005 Classification: IST Contract Start Date: 1 January 2002 Project Duration: 36 months Project Coordinator: Professor Lars Samuelson, LU Partners: WU, VTT

Project funded by the European Community under the “Information Society Technologies” Programme

Final Report, NEAR, IST-2001-32300, February 2005, page 2/95

1. Executive summary ..................................................................................... 3 2. NEAR Partners............................................................................................ 5

Overview of the consortium..................................................................................................................5 Description of the participants ..............................................................................................................5 Brief description of the subcontractors................................................................................................6

3. Project management.................................................................................... 7 4. Project objectives ......................................................................................... 8 5. Methodologies ............................................................................................. 9

5.1 Description of device principles......................................................................................................9 Three Terminal Ballistic Junction devices (TBJ) ............................................................................9 The Self Switching Device (SSD) ...................................................................................................11

5.2 Materials and Fabrication Technologies ......................................................................................12 The Three Terminal Ballistic Junction device...............................................................................12 The Self Switching Device ...............................................................................................................12

5.3 Characterization...............................................................................................................................13 5.4 Modeling and Simulations..............................................................................................................13

6. Project results and achievements .............................................................. 14 6.1 Fabrication technology ...................................................................................................................14

GaAs/AlGaAs-based technology ...................................................................................................15 GaInAs/InP-based technology.......................................................................................................20 Atomic force microscope (AFM) based nanolithography ..........................................................29 Fabrication of Si based devices .......................................................................................................34

6.2 Discrete nanodevices ......................................................................................................................39 Enhanced switching gain in a side-gated TBJ ...............................................................................39 Functioning discrete amplifying elements at 300 K.....................................................................43 Multi-terminal ballistic junctions as multi-input AND gates ......................................................44 GaInAs/InP and InGaAs/InAlAs based SSD devices ...............................................................46 Silicon based SSD devices................................................................................................................47 RF response of GaAs based TBJs ..................................................................................................48 HF-measurements of single InGaAs/InAlAs TBJ devices ........................................................52 High-frequency measurements of SSDs ........................................................................................55

6.3 Circuit implementation...................................................................................................................59 Circuits based on SSD devices ........................................................................................................59 Single logic element in Si at 300 K with line widths 50-100 nm ................................................61 Circuits based on TBJ devices and point contacts .......................................................................64 Set-Reset-latch ...................................................................................................................................65 Nanoelectronic Half ADDER and HAST (Half Adder with Schmitt-Trigger outputs) ........67 Concept development for a FULL-ADDER on the basis of a HALF-ADDER and coupled NAND-Gates ....................................................................................................................................72 Full adder functioning at 300 K......................................................................................................77 Integration capability of TBJ and SSD devices.............................................................................80 Proposal for complex circuit design of demonstrator .................................................................85

7. Deliverables ............................................................................................... 88 8. Publications and conferences .................................................................... 89

8.1 Refereed journal papers..................................................................................................................89 8.2 Conference presentations...............................................................................................................90 8.3 Book chapters ..................................................................................................................................94 8.4 Technical reports .............................................................................................................................94

9. Future outlook ........................................................................................... 95


1. Executive summary

The NEAR project was started three years ago with the highly ambitious goals to bring two basic concepts for new devices and circuits from the stage of ideas to: (i) functioning discrete devices, (ii) the demonstration of processing in III-V and Si technology, (iii) room-temperature operation, (iv) assessment of high-frequency opportunities, and (v) the integration of discrete devices into functioning circuits – with one of the primary target to demonstrate a full-adder operating at room temperature. At this stage we are very happy to announce that all these goals are met.

NEAR focuses on room-temperature functional nanoelectronic devices and circuits using two conceptually simple basic structures: three-terminal ballistic junctions (TBJs) and self-switching devices (SSDs). Both approaches have because of their simplicity a high potential for mass fabrication. Being based on ballistic phenomena but not on coherence, they also have the potential to operate at room temperature and are, hence, examples of true nano-based electronics but without the limitation of operation at cryogenic temperatures. Indeed we show that both families of devices and circuits operate very well at room temperature.

We have at the end of the third year the pleasure of being able to deliver the results from a highly successful implementation of all the ambitions and targets as spelled out for NEAR. The over-all targets for the three years of research within NEAR have been:

• to further develop technologies and device concepts related to the TBJ and SSD device

families • to push the technologies from the level of discrete devices to more complex, circuit level

applications, including the development of circuit level modeling • to make full usage of the single-layer lithography character of the devices and circuits,

enabling the use of parallel nanoimprint lithography • to push the operation temperatures from those of cryogenic temperatures to

roomtemperature operation of devices and circuits • to explore and make comparisons between different III-V materials technologies and

opportunities to implement devices and circuits in silicon (SOI) technologies • to realize and demonstrate logic functionality, including the ambition to demonstrate a

monolithic full-adder • to evaluate theoretically as well as by measurements the high-frequency performance of

these devices and circuits.

The primary deliverables for the first year were: (i) fabrication of single logic elements by e-beam lithography, (ii) demonstration of functioning single logic elements at 300 K, and (iii) report on the understanding of the basic physical phenomena. All these were duly met and, simultaneously, considerable progress was made in key technology areas, primarily with the use of nanoimprint technology for realization of TBJ devices and the development of mixing and matching of e-beam writing and UV lithography techniques. During the first year we also established a high-resolution process for fabrication of nanoelectronic devices on substrates with a thin poly-Si or SOI film. The demonstrated success of fabrication of TBJ and SSD devices on Si based substrates is expected to have a significant potential for future applications in nanoelectronic industry. During the first year we also demonstrated a half-adder operating at room temperature and developed the basis for theoretical modeling of discrete devices and we initiated the circuit level modeling of the integration of several discrete TBJ and SSD devices to functional circuits.

The primary deliverables for the second year were: (i) the demonstration of EBL pattern generator at the writing speed of 30 Mhz, (ii) the demonstration of functioning discrete amplifying elements at 300 K, (iii) model extracted from devices in Deliverable No. 2, (iv) report


on possibilities with design of logic building blocks and analogue circuits, (v) report on possibilities with design of complex circuits, (vi) functioning single logic element made by imprint. All the tasks listed above were successfully reached and all the deliverables set for the second year were delivered. Furthermore, we managed during the second year to demonstrate (still at low temperatures) a full adder with the TBJ-related technology in the GaAs system. An important breakthrough within the NEAR project in the second year is that room-temperature functioning TBJ and SSD elements are realized on silicon on insulator (SOI) substrates, which could indicate that the TBJ and SSD concepts are transferable, with necessary modifications, to the future silicon industry. Ballistic transport of electrons at high bias was studied with a multiple-port counterpart to the TBJ device. If a high bias is applied to a device, we found that it is possible to induce long mean free path to the carriers. On the device and gate level, the issues of analog operation, static digital operation, dynamic digital parameters, and layout and area consideration were analyzed. On the system level, issues like static and dynamic power consumptions, supply and signal voltage levels, fan in/out, noise margins, substrates and interconnection were discussed.

The primary deliverables for the third year were: (i) the demonstration of single logic elements in silicon operating at room temperatures, (ii) the demonstration of a complex circuit design based on the NEAR device concepts, (iii) the demonstration of a full adder functioning at room temperature. All these have been successfully reached. The transfer of our NEAR device and integrated circuit concepts developed with III-V heterostructures to silicon-based material is technologically very important and is expected to be important for the future nanoelectronics. In the third year, compound logic devices, such as NAND and NOR gates, were realized on SOI substrates based on NEAR technology. To demonstrate the integration ability of NEAR devices, a compact sequential logic device (or a simple memory cell) was developed based on integrated TBJ NAND logic devices. This work goes even beyond the defined tasks of the NEAR project but is a good demonstrator of the applicability of the NEAR device concepts.

All this has been possible through an optimized sharing of responsibilities among the NEAR partners. Furthermore, we have taken the recommendations obtained in the spring of 2004 from the evaluators seriously, having made it a high-priority effort to perform actual high-frequency measurements. The success of this effort is based on close collaboration between the different partners, via jointly developed device lay-out enabling such measurements, the exchange of samples between the different laboratories and the joint used of equipment. As a consequence of the effort we have been able to demonstrate device operation up to ≈ 100 GHz.

The interactions among the partners of NEAR have been very intense and efficient, in terms of joint studies, of sharing of samples and technologies, and through project meetings. The combination of work planned in the project program with novel initiatives based on insights and experiences gained during the work of NEAR, has also resulted in a high level and quality of publications, with considerable impact on this field of research. Considerable interest from other research laboratories following our efforts, as well as from organizations engaged in the road-map for the semiconductor industry, has been quite satisfying for us to observe.


2. NEAR Partners

Overview of the consortium

Short name

Organization, key proposer

Role Country Function in project

LU The Nanometer Structure Consortium Prof L Samuelson

CO S MOVPE of InP-based material, e-beam lithography, imprint, modeling, medium frequency measurements at a wide range of conditions

WU Technische Physik Prof A Forchel

CR D MBE of GaAs-based material, high speed e-beam lithography, stamp manufacture, imprint, circuit design, high frequency measurements

VTT VTT Dr J Ahopelto

CR FIN Devices in Si, e-beam, imprint, circuit design, issues of Si-CMOS compatibility, measurements of complex circuits

Description of the participants

LU The Nanometer Structure Consortium at the department of Physics at Lund University is a research organization with participants from about ten research groups within physics, chemistry, biology, electronics, and also involving industrial partners. During the last years we have been coordinating the EU projects: Q-SWITCH, NANOTECH, CLUPOS, CHANIL, and NEAR and participated in INTAS 99-864, CHARGE, MICROSYNC, DIAMONDS, PROFILE-QD, PHANTOMS (network), S4P (subcontractor), and NANOMASS. The focus of the research is in the fields of fabrication, characterization, and applications of nanostructures, mostly III-V semiconductors. The research facilities include clean room labs for epitaxy, nanoprocessing and characterization of nanostructures. Well-established technology of epitaxial growth (MOVPE and CBE) contribute to many research projects, including studies of nanowire based structures. High-resolution patterning methods, such as E-beam and Nanoimprint lithography in combination with lift-off and etching techniques allow fabrication of nanostructures with lateral sizes of about a few 10s of nanometers. Different characterization methods, e.g. optical spectroscopy and electron transport at low temperature are used for studies of the semiconductor nanostructures. A cross-disciplinary research in nano-biophysics is established as well. WU The Microstructure Laboratory of Würzburg University and the associated Technische Physik group form a German center for nanofabrication for investigations on novel opto- and nanoelectronic devices as well as for studies of low dimensional effects in optical and transport properties of semiconductors heterostructures. Within a 550 m2 class 10/100 cleanroom key technologies for the development of nanoscale III-V, Si and II-VI devices are well established. Of particular importance for the proposal are molecular beam epitaxy of GaAs/AlGaAs modula-tion doped heterostructures with 4K mobilities in excess of 2 x 106 cm2/Vs. High resolution electron and ion beam systems, dry and wet etching and other techniques required for III-V and Si nanoelectronic device fabrication are well established. The group consists of about 50 persons involved in processing and characterization (optical and electrical analysis, (magneto)transport, X-ray, TEM etc.). The Würzburg group has been involved successfully in a number of ESPRIT projects.


VTT VTT Information Technology is one of the six research units of Technical Research Centre of Finland. The research activities at Information Technology cover the whole value chain of the modern information and communication technology. The seven research fields of VTT Information Technology are Microelectronics, Microsensing, High Frequency Technology, Networks, Human Interaction Technologies, Information Systems and Media (http://www.vtt.fi/tte/indexe.htm). VTT Microelectronics has long experience in silicon technology for microelectronics, including integrated circuit fabrication and design, micromechanics, thin film technology, integrated optics and nanotechnology. The silicon processing facilities of VTT Microelectronics covers 1700 m2 of 10...100 class clean room for the front end and back processing of silicon systems.The Nanoelectronics Group, led by Professor Jouni Ahopelto, is part of Microelectronics. The research topics of the Group include silicon nanoelectronics and photonics, quantum dots, semiconductor-superconductor structures and nanoimprinting. Brief description of the subcontractors

UM Dr. A. M. Song at University of Manchester is a subcontractor to LU. The group's activities within the NEAR project include compound semiconductor growth by MBE, nanolithography, and dc and high-frequency measurements. Self-switching diodes and transistors (SSDs and SSTs) were fabricated by AFM-based nanolithography using nanoindentation and local oxidation approaches and also using different material systems. Integrated parallel SSDs were recently measured up to 110 GHz at UM, which is by far the highest frequency demonstrated in all novel nanoelectronic devices. XENOS The XENOS Semiconductor Technologies GmbH in Germany is a subcontractor to WU and deals with tools, processes and services for semiconductor- and nanotechnology. The subcontractor XENOS Semiconductor Technologies upgraded within the project NEAR the E-beam system in Würzburg. XENOS offers the fastest available pattern generators. For comparison, pattern generators offered by other vendors are typically designed for SEM lithography and allow a maximum exposure clock of 10 MHz, a factor five slower than the XENOS system. Moreover, XENOS has expert knowledge of the E-beam system installed in Würzburg.


3. Project management

The organizational structure of NEAR consists of one coordinator, one scientific coordinator, one administrative team and a Steering Committee. The program is divided into two subprojects with each one project leader, making use of resources divided in three Work Packages with one Work Package leader each. Each Work Package consists of different tasks with Task Leaders. The Steering Committee includes the coordinators, the project leaders, the work package leaders and the task leaders. Four regular meetings were organized each year with about 10-15 participants each time, including the Steering Committee members, other senior staff and students. In addition, we organized a few telephone conferences to discuss the progress of the NEAR project. Structure for project management Coordinator: Prof. Lars Samuelson (LU) Scientific coordinator: Prof. Hongqi Xu (LU) Administrative team: Hongqi Xu/Lars-Åke Ledebo/Anneli Löfgren/Jonas Johansson (LU)

Affiliation Name Subproject leader

Work Package

leader

Task leader Steering committee

LU Lars Samuelson x

LU Hongqi Xu TBJ Task 3.B x

UM* Aimin Song SSD WP2 Task 2.A x

WU Lukas Worschech Task 2.B x

VTT Jouni Ahopelto WP3 x

VTT Markku Åberg Task 3.A x

VTT Mika Prunnila Task 3.C x

WU Martin Kamp Task 1.A x

WU Alfred Forchel WP1 x

LU Ivan Maximov Task 1.B x

*UM (=University of Manchester) is a subcontractor to the NEAR project. Aimin Song moved to UM from LU in March 2002.


4. Project objectives

Future applications in electronics will need devices and circuits with higher performance, with increased level of compactness and complexity and, not the least, with proven fabrication tech-niques that will allow these designs to be realistically fabricated. Furthermore, a major challenge is to choose and develop nanoelectronics devices and circuits that will operate reliably at room temperature. We have offered approaches in NEAR in response to these requests.

Two novel approaches towards the realization of nanoscale electronic elements and circuits were explored and developed for use in room-temperature devices and circuits. In most previous cases explored, nanoelectronic devices and circuits function only poorly at temperatures above cryogenic temperatures, especially at room temperatures. Our approaches were based on novel designs of discrete nanoelectronic devices namely point contact based three terminal ballistic junctions (TBJs) and self switching devices (SSDs). With characteristic feature sizes in the 20 – 80 nm range, these devices should allow to perform logic operations or operate in RF-circuits at room temperature. We planned to develop optimized individual TBJs and SSDs as well as to use them in basic circuits like a half and full adder operating at room temperature.

The two novel device concepts to produce nanoelectronic circuits for room temperature operation have recently been identified and proposed for use by members of NEAR. The functionality for discrete devices has been demonstrated for both approaches, forming the basis for two families of patent filings.

Both concepts use planar active device geometry, with the combination of discrete devices to form circuits by lateral arrangement. For the patterning of the active section of devices and circuits, high-resolution electron beam lithography has been used. In order to remove the low throughput of present e-beam systems, we planned to develop a novel high-speed pattern generator. Furthermore, the simple basic layout of the devices to be investigated in NEAR per-mits the central sections of devices and circuits to be defined by nanoimprint lithography, in combination with less critical contact definition obtainable by UV-lithography. All three partners have been actively involved in programs in nanoimprint, which we used in circuit fabrication. These devices and circuits are thus also suitable as realistic test cases for evaluation and im-provement of the imprint technologies.

Even though the technology of fabrication of the different device families in NEAR is similar in nature, it is interesting to note the fact that the physics and the functionality and use of these devices are vastly different. This illustrates that the approaches chosen offers richness in opportunities. We thus expect that the two types of devices and circuits that we have explored and developed in NEAR will have great impact on future nanoelectronics.


5. Methodologies

5.1 Description of device principles In order to be attractive for future electronic applications, room temperature nanoelectronic devices have to meet a number of criteria. These include:

• shrink circuit dimensions considerably by using nanoelectronics, • allow for reproducible fabrication by low complexity technologies, • include inexpensive mass fabrication processes, • be compatible with/exceed dimensional requirements of ITRS predicted for the next 10 to

20 years. The two technologies are described separately below. Both these device concepts, proven to be feasible for application at room temperature, meet the above criteria.

• The Three Terminal Ballistic Junction device (TBJ) was discovered during a previous MELARI project, and is based on transfer of ballistic electrons with a mean free path of larger than the distance between adjacent point contacts in a conduction layer.

• The Self Switching Device (SSD) is fabricated by etching of trenches in a conducting sheet. The function is based on current induced self-switching by control of a narrow channel.

Three Terminal Ballistic Junction devices (TBJ)

Multi-terminal ballistic devices have recently been discovered, in which three or more point contacts couple via ballistic electron transport. We here develop as a general workhorse the three-terminal ballistic junction (TBJ) device, in which the ballistic nature of electron transport is exploited. This device consists of three point contacts, which are coupled via a ballistic area of extent smaller than the mean free path (see Fig. 1 for a schematic presentation of the TBJ structure). Our simulation based on quantum mesoscopic theory shows that for a TBJ which is symmetric with respect to the central branch contact, having one of the two symmetric branches connected to ground (say Vr = 0), and with a voltage Vl applied to the other branch, the voltage developed at the central branch exhibits a diode-like behavior: The output approximately follows Vl linearly when Vl is negative and saturates at a value close to zero when Vl becomes positive, see Fig 1(b). This simply indicates that the voltage output Vc from the central branch can be at a positive value greater than a positive logic threshold VH only when both Vl and Vr are placed at high enough, positive values. Thus, the simple, extremely compact TBJ device can be used as a logic AND gate, as indicated by the logic truth table shown in Fig. 1(c).


Fig. 1. (a) schematic picture of a symmetric three-terminal ballistic junction device. (b) the calculated output voltage Vc from the central branch as a function of the applied voltage Vl at the left branch, while the right branch is grounded. (c) the symmetric TBJ device can be operated as a logic AND gate. Our theoretical and experimental analyses have also shown that for the symmetric TBJ device, when finite voltages Vl and Vr are applied in a push-pull fashion, with Vl =V and Vr = - V, to the left and right branch, respectively, the voltage output Vc from the central branch will always be negative, in total contrast to a three-terminal junction built from conventional conductors, for which Ohm's law predicts a zero output of the voltage Vc. (see Fig. 2 for a fabricated structure and the measured result). This novel characteristic appears even when the device symmetry is broken, provided that |V| is larger than a threshold.

(a) (b)

-1 0 1

-1

0

Vl = -Vr

T = 300 K

Vl (V)

V s (V)

Fig. 2. (a) an AFM image of a TBJ made from an InGaAs/InP quantum well system. Here, the TBJ is arranged as a T-branch which is basically a sub-100 nm cavity connected in a symmetric way through three point contacts (PCs) with widths about or less than 100 nm to the electron reservoirs. (b) the output voltage from the central branch VC of a GaAs/AlGaAs device measured at room temperature as a function of the applied voltage VL to the left branch when the device is operated in a push-pull fashion with VR = - VL. Our analyses further show that all these novel characteristics occur at both low and room tem-peratures and should be potentially important for future electronic applications. One example is

Input Output Vl Vr

Vc

1 1 1 1 0 0 0 1 0

0 0 0

"AND"

(a) (b) (c)


already given above, where a logic AND gate operation is shown. The device may also operates as a logic OR gate if we take negative voltage as the binary value of 1. Other logic functions, such as inverter (NOT gate), NOR gate, NAND gate, as well as half-adder, can also be designed with the TBJs as building blocks. We have also shown that the TBJ can be used as rectification devices and frequency multipliers and have experimentally demonstrated operation of the devices for frequencies up to 10 GHz at room temperature. Our ultimate objective in NEAR has been the realization of room-temperature functional full adders with the TBJ architecture. The Self Switching Device (SSD)

Fabricating silicon nano-devices as well as nano-circuits by simply writing lines We have demonstrated a "nano-switch" or "nano-diode" as shown in Fig. 3 with full functionality at room temperature. The current-voltage characteristic was just like that of a conventional diode, but the threshold (from 0 V to a few volts) and the current level (from nA to µA) can be tuned by orders of magnitude by simply changing the device geometry, with no need to change the property of the host material by doping, etc.

Fig. 3: (a) SEM image of a SSD device fabricated on InGaAs quantum well material by e-beam lithography. (b) The SSD functions as a diode. (c) The measured I-V characteristics of the SSD. Figure 3(a) shows an SEM image of an SSD. The etched trenches define a nanometer wide chan-nel and break the inversion symmetry along the horizontal channel (or the current) direction. With this design, a certain negative voltage on the right side will electrostatically lift up the con-duction band bottom inside the channel, reduce the channel width, or even pinch off the narrow channel, as schematically shown in Fig. 4(b). A positive voltage on the right side will, as indicated in Fig. 4(c), lower the conduction band bottom inside the channel, widen, and hence open up the channel, leading to increased current. This results in a diode-like functionality, as shown by the experimental I-V characteristic at 240 K in Fig. 3(c).

etched trenches

0

0.5

1

1.5

2

-1 -0.5 0 0.5 1

Cur

rent

(µA

)

240 K

(a) (b) (c)

Voltage (V)


Fig. 4: (a) Schematic picture of a SSD made on a conducting layer. The thick dark lines indicate the etching trenches and the grey regions mark the depletion regions induced by the surface charge of etching trenches. (b) Operation principles of the SSD device at a reverse bias. (c) Operation principles of the SSD device at a forward bias. Operation of this type of nano-switch has been realized at room temperature using InGaAs/InP. Since the working principal requires only a nano-channel around 50 nm wide but not necessarily high electron mobility, it should be possible to readily and reproducibly fabricate this device using silicon. Thus an extensive effort has been made on realization of SSDs in silicon materials in NEAR. Also, integrated circuits have also been fabricated and tested on III-V semiconductor heterostructures and silicon materials. 5.2 Materials and Fabrication Technologies

The Three Terminal Ballistic Junction device

Our first task was to overcome technological challenges in the fabrication of TBJ devices in the device dimension (not only the minimum feature size) of 100-200 nm and to build the first TBJ logic gates, including compound logic gates such as the NAND and Exclusive-OR gates. We planned to finally fabricate full-adders using the TBJ-based logic gates. Our goal is to provide a new family of logic devices, defined as TBJ logic family, to the electronic industry.

It was clear that to test our device principles, matured technology such as electron-beam lithography should be explored from the beginning. However, in order to develop TBJ based logic circuits the consortium has to make large efforts regarding nanoelectronic device technology. Bottlenecks were foreseeable concerning nanolithography, in particular if the processes to be developed have to be scalable to a large number of devices or circuits. Here, the consortium will explore nanoimprint as a fabrication technique allowing for a high degree of parallelism, as well as high-speed electron beam lithography based on a new pattern generator developed by a subcontractor of WU. This has allowed achieving 10 – 20 nm resolution in multilevel processing steps which are essential if the entire circuit dimensions should be as small as possible. In order to minimize fabrication fluctuations, low damage reactive dry etching processes were used in conjunction with wet chemical processes for the definition of the TBJs.

As to materials, we have fabricated most TBJ devices and circuits on III-V semiconductor heterostructures, but the TBJ device concept was also demonstrated in silicon on insulator (SOI) substrates, thus allowing us to transfer III-V TBJ technology to silicon TBJ technology. The Self Switching Device

The self-switching device (SSD) as well as circuits can, as shown below, be fabricated using stan-dard electron-beam lithography or nanoimprint techniques using for example silicon. The new

– +

+ + + + +

+ + + + +Channel more open

–+

– – – – –

– – – – –Channel more closed

depletion

(a) (b) (c)


device has a number of conceptual advantages from device, material, and circuit points of view, which have been explored in the frame of the present project.

Since the working principle does not require high electron mobility, SSDs can be readily made using silicon, or other materials such as Ge, GaAs, InP or InAs. Figure 5 shows schematically some device examples. Dark lines represent, e.g., etched trenches. Fig. 5(a) shows a bridge rectifier, where, by applying an AC voltage to the upper and lower terminals, a DC voltage is generated between the left and right terminals. Fig. 5(b) displays a logic OR, in which, if to any of the left two input terminals is applied a logic high voltage, the output will have a logic high output. In both cases, devices as well as circuits are made by just writing/etching lines in one fabrication step, rather than making dopings or gatings, etc., which in multiple steps would require precise alignments. In much the same way, we can design other logic elements such as AND and NOT. Therefore, a new, complete family of logic elements can be made. Based on these basic logic building blocks, it is in principle possible to construct fully functionable, Si-based, logic circuits like adders. Another noticeable advantage is that the logic voltage level can be tuned to meet the current CMOS logic voltage level.

5.3 Characterization

The electrical properties of fabricated devices and circuits need to be characterized. Both DC measurements and AC measurements with frequencies up to ~100 GHz were conducted for the device characterization. While most measurements were done at room temperature, measurements at low temperatures (down to 300 mK) were also performed throughout the project. Some devices were in addition measured under applied magnetic fields (up to ~10 T).

The purposes of all these measurements were set as: searching for new physical phenomena, confirming device properties predicted by theory and modeling, device optimization, extraction of operation speeds, etc.

5.4 Modeling and Simulations

To guarantee an efficient development of TBJ and SSD logic devices and circuits, we performed simulations and systematical analyses. In particular, issues like power consumption and operation speed of the devices will be addressed theoretically. Based on the result of a comparison of experimental and theoretical results, optimized devices were designed. For single devices, simulations based on mesoscopic transport theory were performed. Simulations based on commercially available software, such as Silvaco’s process simulator ATLAS were also performed. In the circuit level, SPICE and APLAC simulators were employed.

V

–+ output

input

input

Fig 5(a) Bridge rectifier Fig 5(b) Logic OR


6. Project results and achievements

6.1 Fabrication technology

The overall objective concerning fabrication technology is to provide the other areas within this project with room temperature functioning nanoelectronic devices and logic circuit demonstrators based on three terminal ballistic junctions (TBJs) and self-switching devices (SSDs). As the consortium work is aiming on nanoelectronic circuits, a number of key processes like high resolution lithography and etching had to be considerably advanced compared to the state of the art, e.g. regarding dimensional control of different devices in one circuit, minimization of etch damage etc.

Single devices as well as logic circuits based on room temperature capable TBJ devices and SSD devices have been fabricated by combining wet etching with e-beam lithography and nanoimprint-based patterning. In addition a high-speed e-beam pattern generator has been developed, which increased the throughput of e-beam systems by up to an order of magnitude.

During the project fabrication techniques based on electron beam lithography (EBL) and wet etching have been developed for both GaAs/AlGaAs and InP/GaInAs 2DEG material systems. Fabrication in Si was based on the EBL and highly selective plasma etching approach. Nanoimprint lithography (NIL) and atomic force microscope (AFM) lithography have been applied for fabrication of TBJ- and SSD-based circuits and devices. At the final stage of the project, efforts have been directed for optimization of EBL-based technology and fabrication of TBJ and SSD devices for high-frequency measurements. Listed below are the main achievements in WP 1, Fabrication Technologies:

• EBL-based technology of GaAs/AlGaAs TBJ and SSD-structures with feature sizes down to a few 10 nm has been developed. The EBL system has been upgraded to 40 MHz writing speed.

• The processing of GaInAs/InP TBJ-devices using EBL and non-selective wet etching has been optimized for making devices with feature sizes about 100 nm and large mesas in the same EBL-based processing.

• Fabrication technology for arrays of SSDs (up to 100) in GaInAs/InP and InGaAs/InAlAs materials has been developed to perform high-frequency measurements.

• Nanoimprint lithography (NIL) has been applied for fabrication of both TBJ- and SSD-devices in GaInAs/InP material. Room temperature functionality of NIL-made TBJ- and SSD-structures has been demonstrated.

• Nanoimprinted TBJ-based circuits showed “inverter”, “AND” and “NAND” logic functions at room temperature.

• AFM-based lithographic technique has been applied to produce functioning InGaAs/InAlAs and GaAs/AlGaAs SSD-structures using local anodic oxidation (LAO) approach.

• Si-technology based on EBL and highly selective plasma etching has been developed for making SSDs and TBJs. High selectivity and anisotropy of etching allowed fabrication of trenches in Si down to 16 nm wide.

• Self-aligning Si fabrication process based on different segregation coefficients of dopants in silicon has been proposed and demonstrated.


GaAs/AlGaAs-based technology

Fabrication of GaAs/AlGaAs TBJ-devices Thin and highly mobile electron gases (2DEGs) in GaAs based heterostructures in close proximity to the sample surface represent the basis of the studies reported in the following section. We have realized 2DEGs by molecular beam epitaxy in modulation doped AlGaAs/GaAs heterostructures with free mean paths of electrons exceeding 10 µm for 2DEGs as close as 50 nm to the surface at 4.2 K. The samples were further processed to realize Hall bars, contacts and interconnects by UV lithography.

High-resolution electron beam lithography with 100 kV acceleration voltage in combination with etching techniques were used for definition of different and complex shaped nanostructures with feature sizes down to a few 10 nm. In order to increase the writing speed of our electron beam system first tests with a new pattern generator and deflection system are currently carried out, which allows to write nanoelectronic patterns at writing speeds of 40 MHz and higher.

In Figure 6, a scanning electron microscope (SEM) image of a side-gate controlled TBJ device (bright contrast) made by e-beam lithography on an AlGaAs/GaAs heterostructure is presented. This TBJ structure has a minimal width at the branches of 50 nm. The trenches (dark contrasts) isolate the stem as well as the branches from the outer electron reservoirs. These reservoirs serve as side-gates and thus allow the switching of electrons into either of the branches by a lateral electric field.

In Figure 7, an SEM image of a processed logic AND/NAND-device is shown. The device consists of two building blocks: a TBJ serves as compact AND gate and a side-gate controlled TBJ acts as buffering device. From the left side a TBJ discharges with its stem in an internal gate. This TBJ provides the AND-functionality due to the rectification effect in ballistic three terminal junctions (TBJ): the voltage at the stem of a TBJ tends towards the lower voltage applied to the branches serving as inputs X and Y of the logic device. The stem of the first Y-branch ends up in the left side-gate of a TBJ working as amplifier with Schmitt-Trigger characteristic. The TBJ has two output signals: the logic signal C = X NAND Y and C = X AND Y at the left and right branch, respectively.

Fig. 6: SEM image of a TBJ controlled by lateral side-gates. The minimal geometrical width of each branch is 50 nm.


1 mµ

Fig. 7: SEM image of a logic AND/NAND-gate consisting of two Y-branches.

Technology of asymmetric TBJ-devices in GaAs/AlGaAs Fabrication technology based on electron-beam lithography was developed for realizing single and integrated TBJ and SSD devices on III-V semiconductor heterostructures, and was described in details in the first year report. In the second year, this EBL-based fabrication technology has been applied to realize different versions of the TBJ- and SSD-structures for detailed electrical characterization of the devices, and for realization of newly developed complex circuits. Here, as an example, we will only report on the fabrication of asymmetric TBJs as discrete amplifying elements at 300 K using EBL-based technology. For information on the fabrication of other devices with EBL technology we refer to our publications and reports (see Volume 2). The results of the fabrication of integrated devices, such as full adders, with EBL technology, will be given in Chapter WP3, together with the concept development.

As an example of the use of EBL technology in NEAR, here we present the realization of asymmetric TBJs as discrete amplifying elements at 300 K. In order to study asymmetric TBJs we have fabricated TBJs with specially designed gate geometries to increase the possibilities to control the left and the right branch. In Figure 8 (left part) an electron microscope image of a TBJ controlled by 4 independent side-gates is shown. The upper 2 side-gates allow an efficient control of the branches and the lower side-gates are used to tune the stem current. An asymmetric operation of the device can be reached by driving one branch close to pinch-off, due to a negative voltage applied to the near side-gate, with an open channel between the other branch and the stem. In addition we have realized geometrically asymmetric TBJs. An example is depicted in the center part of Figure 8. Here an asymmetry is introduced by a monolithic feedback electrode by which one branch influences the other. Very compact asymmetric TBJs were also realized with a constriction in one branch close to the branching section. An SEM image of the central part of such a device is shown in the right part of Figure 8. As will be demonstrated in WP2, the constriction leads to a drastic enhanced capacitive coupling between the branches reported in the first year report.


Fig. 8: Electron microscope images of TBJ structures with gate geometries to control electrically the symmetry of the device (left part) or by feeding back monolithically one branch to the other (central part) with 90 nm wide branches. Right part: Compact asymmetric TBJ with a constriction close to the branching section. We have been able to observe an intrinsic switching bistability of asymmetric TBJs, see Figure 8(b). Depending on the external electric field the TBJ can be tuned from amplificaion to a switching bistability. It is interesting to note that the asymmetric TBJs allow us to observe subthreshold swings smaller than the classical kT-limit.

Fig. 9: Left part: Voltage-voltage characteristics of an asymmetric TBJ. Right part: Scheme of several input voltage swings to observe a bistable switching.

The intrinsic switching bistability allows the realization of a Schmitt-Trigger without any external feedback. Several configurations to observe a bistable switching are presented in Figure 9. By controlling the TBJ by the left side-gate it is possible to realize voltage swings of the same range at the in- and output (the center graph of Figure 9).


Full adder based on multi-terminal junctions We demonstrated a full-adder based on branched multi-terminal junctions (MTJs) functioning at room temperature. Our MTJ structures were made on modulation-doped GaAs/AlGaAs heterostructures with a two-dimensional electron gas (2DEG) located 90 nm below the surface.

Electron-beam lithography and wet chemical etching were respectively used to define the devices and to produce trenches 100 nm deep in the wafer. For this purpose, several new masks were defined exploiting our new pattern generator (XENOS software) with the possibility to reach 50 MHz writing speeds. As shown in Figure 10 the complex mask designs thus demonstrate the high performance of the writing system.

The full-adder is composed of three interconnected MTJs. Seven interconnects are used as loads and the input signals are applied to 18 gates. Besides the high functionality of the layout, one additional advantage is that the carry function can be controlled independently of the sum function and vice versa. This feature is an important degree of freedom, as often only one of the two full-adder functions needs to be computed. The samples were mounted on a 32-contact chip carrier and bonded via gold wires to the contact pads. A magnified image of the central structure of the full adder is presented in Figure 10. The three MTJs can be identified: The left MTJ performs the carry function, while the middle and the right MTJs are exploited for the sum operation.

Fig. 10: Magnified views of the central structure of the full-adder. Three side-gate controlled multi-terminal junctions (MTJs), each controlled by 3 pairs of side-gates, are integrated. The distance between monolithic interconnects (pitch) is 1 µm. The central branching section of the left carry bit MTJ and the middle XOR MTJ are separated by 7 µm.


Report on E-beam system upgrade: E-beam writing at 40 MHz demonstrated The upgrade of the E-beam lithography system in Würzburg University used for GaAs/AlGaAs processing was a part of technology development during the 2-nd year of the project. In order to achieve a deflection speed of up to 40 MHz and higher, several components of the E-beam system were upgraded. One component is a new pattern generator, which allows the generation of digital pattern signals with writing frequencies of up to 60 MHz. Another major part of the upgrade is the change of the deflection system. The former deflection system used only a single deflector unit, which required the use of high voltages on the order of 300 V in order to deflect the beam over the entire exposure field range (200 * 200 µm). Therefore the slew rate of the deflection amplifier was limited to a maximum speed of 4 MHz. The upgraded system uses a two-stage deflector, as shown in Figure 11(a). The beam is positioned in the exposure field by the main-field deflector and fast pattern writing is carried out with the sub-field deflector.

The main field DAC has been upgraded from 16 to 18 bit accuracy, allowing a 1 nm pixel spacing in a 200 µm field. The second deflector has a deflection range of 5 µm, 14 bit accuracy, 0.5 nm pixel spacing and operates at lower voltages of 15 V and 50 MHz maximum speed. Figure 11(b) shows some specifications of the two deflector units. Patterns are automatically fractured by the control software into subfields. Figure 12 shows the results of exposure tests in ZEP 520 resist using the new system. All exposures were carried out at 1 nA beam current and 40 MHz deflection speed.

(a)

(b) Fig. 11: (a) Schematic of upgraded deflection system. (b) Specifications of main- and subfield deflector. The resolution of the upgraded system was tested by exposing single pixel lines and a subsequent lift-off process. A 100 nm thick layer of ZEP 520 resist was used for the exposures. The beam current was 1 nA. After development of the resist, 3 nm Cr and 10 nm Au were evaporated on the sample. The remaining resist was removed in Pyrrolidone. Figure 12(c) shows an electron micrograph of 20 nm wide, continuous lines after lift-off. This result is comparable to tests performed before the upgrade, indicating that there is no loss of resolution at higher deflection speeds.


(a) (b)

(c) Fig. 12: (a) Lines with 150 nm spacing, (b) dot array with 300 nm period, and (c) 20 nm wide Cr/Au lines with 150 nm period fabricated by lift-off.

GaInAs/InP-based technology

Epitaxy of GaInAs/InP 2DEG structures High mobility Ga0.25In0.75As/InP 2-dimensional electron gas (2DEG) structures were produced by metal organic vapor phase epitaxy (MOVPE). Optimization of the 2DEG structures was done in order to obtain maximum electron mean free path at room temperature, with the 2DEG positioned only 40 nm from the surface. In order for the TBJ-devices to work, the electron mean free path must be comparable to the characteristic size of the devices. The minimal feature size, which can be obtained in lateral direction in GaInAs/InP is about 100-150 nm, i.e. the electron mean free path must be at least 100 nm. Due to the necessity of an extended repair of Lund’s MOVPE equipment we have transferred the growth process for the 2DEG wafers to the group of H. Hardtdegen, Forschungszentrum Jülich, Germany. Since theirs reactor design is different, the results were also different and some optimization runs had to be done. A reproduction of exactly the same structure as we have used so far resulted in samples with a too low 2DEG electron mean free path, as is visible in Figure 13 (Series 4029-4056). After increasing the doping layer thickness to 2 nm (instead of 1), and the In composition to 77 % (instead of 75 %), samples with a mean free path of 150 nm at room temperature could be obtained (sample series 4113).


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InP NID spacer 200 Å

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GaInAs QW 90 Å

InP NID 500 Å buffer

InP: Fe substrate

Fig. 13: Dependence of electron mean free path (293K) in GaInAs /InP 2DEG structure vs MOVPE growth temperature.

Electron beam lithography and wet etching The Ga0.25In0.75As/InP 2DEG samples were processed using our well-established technology, which includes the following steps:

• Optical lithography and wet etching for definition of mesas • High resolution electron beam lithography (EBL) • Non-selective wet etching • Formation of gates and contacts

The TBJ and SSD structures are formed using EBL operating at 35 keV and probe current of 20 pA. A high resolution positive tone resist ZEP520A7 is used in EBL. After a post-development baking at 120°C of the resist, the GaInAs /InP structures are etched in a HBr-based solution to a depth of >100 nm to isolate side gates from the active devices. Typical etching rates of GaInAs/InP are about 1 to 2 nm/s with high reproducibility. An example of a TBJ-device coupled to an electron waveguide is shown in Figure 14. Some limitations of this technology include serial writing method of electron beam lithography (slow writing) and isotropic character of wet etching, which make it very difficult to create deep narrow

Fig. 14: An AFM image of EBL-defined and wet etched TBJ-device (A) coupled electrostatically to an electron waveguide (B).

A B


trenches for electrical isolation needed, for example, for the SSD structures. Optimization of processing of GaInAs/InP TBJ-devices Mass production is important to industrialize device fabrication and reduce cost. For this purpose UV-lithography and nanoimprint has shown very promising results. But for device concept development and device structure optimization, the flexibility and possibility of changing device layout are essential.

It is very common that a three-step lithography method is used for device fabrication: (1) fabrication of mesa-structure, (2) lift-off process for creating ohmic contacts and (3) fabrication of fine-structure. The first two steps are traditionally made with UV-lithography, with a rather time consuming mask fabrication step. After the mask is produced it is easy and fast to fabricate a large batch of samples. The layout for mesa and contact structures should therefore be rather universal and should work for most common device setups. But for certain applications, e.g. nanoscale high-frequency devices, it is more convenient and sometimes also necessary to use an optimized mesa structure, depending on the fine-structure of the actual device. For this we have developed a method to do all fabrication steps of a GaInAs/InP TBJ-type device with electron beam lithography (EBL).

To simplify the fabrication, we want to use the same resist for the two etching steps to create mesa structure and fine structure. The choice was the positive resist ZEP520A7, span at 9000 rpm for 60 sec and pre-baked 10 min at 160°C. After exposure with EBL it was developed in o-xylene for 5 min and was post-baked for 2 min at 120°C.

For creating deep-etched mesa structure, we used HCl:HNO3 1:4 mixture as etchant. This is a very aggressive etchant (≈ 200nm/s) and 2-3 sec is well enough to etch the sample deep into the substrate. Etching time longer than 7 sec should be avoided, since defects on the resist have been observed after etching for longer than that time. The sample was rinsed in DI water and resist was stripped with tri-chloroethylene (TRI). Structures with the size down to ~10 µm are easily fabricated with this method.

For creating shallow-etched fine structure we used the reported Saturated Bromine Water (SBW) recipe. The mixture, SBW:HBr:HNO3:H2O 0.3:5:5:40, gave an etching speed of ≈2 nm/s. Etching of 40 sec gave deep trenches trough the 2DEG, which was down to the substrate and thus form an isolating region. The sample was rinsed in DI water and resist was stripped with TRI.

200nm200nm

Fig. 15. A 10x10 µm2 deep etched mesa-structure made with EBL. Three contacts, also made with EBL are aligned to the mesa. The fine-structure is to be exposed in the central area of the mesa. The right picture shows a SEM image of the TBJ-device in GaInAs/InP.


Ohmic contacts were made with a double PMMA lift-off technique. The PMMA200-A5.5 resist was span at 6000 rpm for 30 sec and was baked for 10 min at 160°C. The second layer of resist was PMMA950-A6, which was also span at 6000 rpm for 30 sec and was baked for 10 min at 160°C. After exposure with EBL the sample was developed in MIBK:IPA 1:3 for 90 sec and rinsed in IPA. Au-Ge-Au contacts were evaporated, and lift-off was carried out in acetone. Finally, a fast thermal annealing procedure (60 sec at 200°C and then 120 sec at 390°C) was employed to make the contacts ohmic. Figure 15 shows an example of the device made using this approach. Fabrication of parallel SSDs for high-frequency experiments High-frequency characterizations of SSDs have been pointed out by the Reviewers to be a key issue to address during the 2nd year review of the NEAR project. For the high-frequency experiments on SSDs, all four groups in the NEAR project have worked together.

Fig. 16. High-frequency mesa A, which could be used for a four-terminal device. For SSD measurements, two of the terminals of the cross were insulated by wet etching wide trenches.

Fig. 17. High-frequency mesa B, which is specifically designed for two-terminal devices.

Two different mesa designs were adopted, as shown in Figures 16 and 17. High-frequency

mesa A was previous used for a four-terminal ballistic rectifying device. For the two-terminal SSDs, two of the terminals of the cross were insulated by etching wide trenches. High-frequency mesa B was specifically designed for two-terminal devices, such as SSD.

Both GaInAs/InP and InGaAs/InAlAs high-mobility 2DEG samples were used for fabrication of arrays of the SSDs for high-frequency measurements. After formation of high-frequency mesas by UV-lithography, wet etching and lift-off, the active SSD structures were produced by electron beam lithography operating at 35 kV. Positive resist ZEP520A7 was used as etching mask for pattern transfer using the SBW recipe.

In order to reduce the impedance, we have put many (from 7 up to 100) SSDs in parallel. The devices shown in Figures 13(a) and (b) were made at Lund University as part of a collaboration work between the University of Manchester and Lund University. The fact that these 45 SSDs in Figure 18(a) or 100 SSDs in Figure 18(b) can be conveniently connected in parallel, in three or fives columns, is a significant advantage over normal diodes of vertical structures. It is possible to fabricate more columns, and indeed arbitrary number of SSDs in parallel, in order to match standard high-frequency impedance, 50 Ω.


Fig. 18. 45 SSDs in parallel fabricated on high-frequency mesa A. (a) SEM image showing also the ohmic contacts and insulating trenches. (b) A zoomed image of a different device showing how 100 SSDs could be connected in parallel.

Nanomprint Lithography (NIL) for fabrication of TBJ-devices Nanoimprint lithography (NIL), which is a high throughput and a high-resolution (<10 nm) method, is used for fabrication of both single TBJ-devices and complex circuits. This technology was developed at Lund University in cooperation with CHANIL group (EU-project IST-1999-13415). The NIL includes the following process steps:

• Fabrication of SiO2/Si stamp • Imprint into a polymer (resist) • Oxygen plasma ashing to remove polymer residues • Wet etching of GaInAs/InP • Removal of polymer • UV-lithography to create contact pads

Stamps were fabricated on 1 inch SiO2/Si wafer using EBL in a double-layer resist system (ZEP520A7 and PMMA 950K), thermal evaporation of Cr, lift-off and reactive ion etching (RIE) of SiO2. The 30 nm thick Cr was used as dry etching mask to etch silicon dioxide to a depth of 100 nm. After RIE, the Cr mask was removed by wet etching and the stamp was treated by tridecafluoro (1,1,2,2-) tetrahydrooctyl trichlososilane (F13-TCS) to prevent sticking of resist to the stamp.

Imprint was done in a 120 nm thick ZEP520A7 resist at a pressure (Pi) of 40-50 bar and imprint temperature (Ti) of about 200 °C. Imprint time of 40 s was found to be the best for the above mentioned NIL conditions. The NIL optimization (Ti, Pi, imprint time) was required in order to avoid pattern shift and resist sticking, Table 1.

UV-lithography was used to create contacts after alignment with NIL-made devices. Mesas and ohmic contacts were formed by wet etching, evaporation of Ni/Au/Ge and annealing.

Electrical characterization of the NIL-made TBJ-device demonstrated non-linear characteristics at room temperature, indicating full functionality of the device. Comparison of EBL-and NIL-made devices showed identical behavior (see Figure 19). This indicates the absence of electrically active damage in the GaInAs/InP 2DEG structure after the NIL. Figure 20 shows both SiO2 stamp and GaInAs/InP structures after NIL, wet etching and resist removal.


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Fig. 19: Electrical characterization of GaInAs/InP TBJ structures made with NIL- and EBL-techniques. The curves are similar, indicating the absence of process-induced damages by NIL.

Fig. 20: SEM top view of the stamp (left) and imprinted and etched GaInAs/InP structure (right). Both electron waveguide (A) and TBJ-device are formed using NIL. Electrodes (1) and (3) are side gates to electron waveguide and TBJ-device. Table 1. Optimization results of NIL using ZEP520A7 resist and SiO2 stamp. Evaluation was made using optical and scanning electron microscopy. NIL Ti, °C Pressure, bar Resist after NIL Pattern transfer Comments 220 50 Uneven resist Good OK 200 40 Even resist Good Best result 200 30 Even resist Relatively good “Brain” pattern200 70 Sticks to stamp Poor Not suitable 240 40 Removed Unsuccessful Not suitable NIL-based fabrication of TBJ-based logic circuits During the second year, we concentrated on development of fabrication technology based on nanoimprint lithography (NIL). The NIL-based technology was used mostly for making TBJ- and SSD-based circuits on high mobility GaInAs/InP 2DEG structures. We have demonstrated that it is possible to produce several devices of different types (e.g. TBJ, QPC and SSD) in one NIL processing step. Room temperature measurements of a combined TBJ/QPC circuit showed reliable “NAND” and “Inverter” functionality of the nanoimprinted circuit.


The NIL technology includes the following main steps: (a) fabrication of NIL stamp, (b) nanoimprint and removal of resist residues, (c) wet etching of GaInAs/InP, and (d) formation of ohmic contacts.

Nanoimprint and wet etching were optimized in order to find reproducible conditions to print and etch complex TBJ- and SSD-based circuits. Unlike the initial experiments, where ZEP520A7 resist was used, 120 nm thick PMMA with molecular weight of 50K has been used with typical imprint pressure (Pi) of 40 bar and imprint temperature (Ti) of 200 °C. The imprint time of 40 s was found to be the best for the above mentioned NIL conditions. PMMA resist was found to be sufficiently stable to act as wet etching mask in a standard wet etch solution of saturated bromine water (SBW) and HBr/HNO3. Etching depth was about 100 nm, deep enough to isolate side gates from the devices.

In the second year, the nanoimprint lithography technology has been used for fabrication of the following logic circuits:

• Inverter • “AND” gate • “NAND” gate

d=100 nm TBJ

Gate

Gate QPC

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Fig. 21: SEM image of the SiO2/Si stamp with “NAND” TBJ/QPC structures (left) and corresponding circuit in GaInAs/InP high mobility material after NIL and wet etching (right). Distance d between the TBJ- and the QPC-structures determines the coupling efficiency of the central electrode to control the QPC. The NIL technique allows reproducible fabrication of circuits with d=100 nm.

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Fig. 22: SEM image of NIL-made QPC in GaInAs/InP and electrical measurement diagram for the realization of the inverter function (left) and room temperature measurement results of the inverter (right). The width of the QPC on the left is about 200 nm.


Electrical characterization of these NIL-made TBJ devices and circuits was carried out and demonstrated that these devices and circuits are of high quality and work at room temperature. Figure 21 illustrates both SiO2 stamp and TBJ-based “NAND” circuit made in GaInAs/InP material using NIL and wet etching. The TBJ-device itself can be used as an “AND” gate, while QPC has built-in inverter functionality. A combination of TBJ and QPC gives “NAND” function.

Figure 22 shows an SEM image and electrical measurement results of the inverter circuit made using nanoimprint technology and wet etching. The side gate to the QPC was used as an input electrode, while the output signal was measured as a voltage drop on the QPC. A high input voltage of 2 V results in low output voltage of about 0.8 V, whereas a low input voltage of 1 V gives a high output voltage of about 2.6 V. A NIL-made “NAND” circuit and its experimental truth table are shown in Figure 23 and in Table 2. Here the TBJ-device is electrostatically coupled to a QPC, which is used as an inverter. Two branches of the TBJ-structure serve as inputs of the “NAND” circuit and the central electrode (stem) controls the QPC device by opening or closing it. Since the TBJ-device works as “AND” gate, this combination of TBJ and QPC devices gives the “NAND” functionality. Table 2 illustrates performance of the “NAND” circuit at room temperature.

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Fig. 23: Nanoimprinted “NAND” circuit based on TBJ coupled to QPC and its measurement set-up. The inputs are left and right branches of the TBJ and marked “Vin1” and “Vin2”, while output is connected to QPC and marked with Vout.

1 µm

Table 2: Experimental truth table for the nanoimprinted TBJ-based “NAND” circuit as measured at room temperature.


The nanoimprint technology has also been applied to the fabrication of SSD devices in

GaInAs/InP 2DEG material. For this purpose, a specially designed stamp has been fabricated using the technique described above. Figure 24 demonstrates some first results of the application of nanoimprint for making combined SSD/QPC circuits in GaInAs/InP 2DEG.

Nanoimprint fabrication of SSDs in GaInAs/InP During the third year, we continued the development of fabrication technology of three-terminal ballistic junction (TBJ) and self-switching devices (SSD) based on nanoimprint lithography (NIL). We focused mainly of NIL-fabrication of the SSD structure and their electrical characterization. The technology includes fabrication of the NIL stamp, pattern transfer via NIL and wet etching and formation of ohmic contacts by optical lithography and lift-off. Since the SSD structures are very sensitive to width of the channel, we made a NIL stamp with 200, 300, 400 and 500 nm channel width, see Figure 25. The length of the channels was 1.2 µm in all cases. Apart from the test SSD structures, there were also sets of a combined SSD/QPC circuits. Totally 24 structures were made on a single NIL stamp, see Figure 25.

The NIL process was performed using PMMA 50K as imprintable polymer at T=200 °C. After plasma ashing of the resist residues, the SSD pattern was transferred into the GaInAs/InP high mobility substrate using a wet etching.

The reproducibility and quality of the imprint and etching processes was found to be fairly good, see Figure 26 (left), but electrical measurements of the SSD structures indicated that most of the test devices were either closed or opened due to non-optimal channel width. The room temperature current-voltage characteristics of one of the functioning SSD structures with as-designed channel width of 300 nm is shown in Figure 26 (right).

Fig. 24: Electron microscope image of the NIL stamp for a combined SSD/QPC circuit, consisting of 2 SSDs and 1 QPC (left) and the circuit etched out in GaInAs/InP material (right). Pattern transfer of the devices is very accurate. 50 K PMMA was used in the NIL process.

SSD

QPC

SSD SSD SSD

QPC


Atomic force microscope (AFM) based nanolithography

The SPM (AFM)-based lithography consists two approaches, mechanical and electrochemical. The mechanical approach is either to use the probe to plough or to perform probe indentation (tip oscillating) on the surface of a thin layer of resist (sometime metal layer too) on a semiconductor sample or even directly on the semiconductor surface, in a very accurate and well-controllable manner. If the scratching is performed on a thin resist layer, subsequent etch or metal evaporation plus lift-off will be carried out. The feasibility of direct patterning of semiconductor surfaces has been has been demonstrated for various materials like GaSb, InAs

Fig. 25. Schematic of the NIL stamp (left) and SEM image of the stamp area with test SSD devices (right). The width of the SSD channels was 200, 300, 400 and 500 nm.

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Fig. 26. Two test GaInAs/InP SSD structures made using NIL and wet etching (left). Room temperature current-voltage curve of 300 nm wide (as-designed) SSD structure (right). The SSDs with channel width of 200 nm were completely closed, while 400 nm wide devices were open.


and GaAs, which nevertheless requires either special diamond probes or so-called electron-beam-deposited (EBD) probes.

The electrochemical approach regards mainly the technique of local anodic oxidation (LAO), which has become the most popular method of SPM-based lithography for the fabrication of nanodevices. In a local anodic oxidation experiment, a thin water film covering the sample surface under humidity of normally over 30% serves like an electrolyte between a sample (anode) and the tip (cathode). The negatively biased tip imposes an external electric field which dissociates water molecules into oxidising species, presumably OH–. The field further enhances vertical drift of these species away from the tip towards the surface where they react with underlying atoms to form a localized oxide beneath the tip. The field strength decays across the growing oxide film and the oxide growth process self terminates at/below the critical electric field of the order of 109 V/m. The oxidized areas typically have an increased volume, and hence can be imaged conveniently using the AFM immediately after the oxidation. Local anodic oxidation experiments For local anodic oxidation experiments, the sample to be fabricated must be conducting. Initial tests were therefore carried out on n+ silicon substrates, immediately following an etching step in buffered HF to remove the native oxide. Below (Figures 27 and 28) are two typical images taken after surface oxidation.

To carry out LAO experiments on III-V heterostructures, of which the substrate is not conducting, ohmic contacts had to be made to allow the 2DEG to be electrically contacted so as to serve as the ground for the bias voltage to the AFM probe. Furthermore, the bond pads of the Hall bar sample had to be arranged to one side of the Hall bar rather than surrounding it, so that when the AFM probe moved on to the Hall bar to perform nanolithography and take images, the

Fig. 27: A typical pattern of lithography after local anodic oxidation on n+ silicon substrate.

Fig. 28: A pattern of SSD formed on n+ silicon substrate after local anodic oxidation at -10V applied to the AFM probe.


bond wires would not obstruct the probe. The modified mask set is shown in Figure 29, where green areas represent the bond pads.

After finishing the mask set and setting up the box connectors, our initial tests of local anodic oxidation have shown that LAO is so far not sufficient to fully deplete the 2DEG under the oxidized areas. To overcome the problem, further experiments are undertaken to oxidize a thin layer of titanium on the sample surface, followed by a selective wet etch to remove titanium oxide. We use a very thin layer of titanium (3-7 nm), so as to completely oxidize and remove the desired oxidized areas and to expose the semiconductor surface beneath. A wet etch is then carried out to etch the semiconductor in the exposed areas using the un-oxidized titanium as an etch mask. Nanoindentation and nanoplough experiments Both nanoplough and nanoindentation lithography have also been carried out to pattern a thin photoresist (S1805 highly diluted by EC solvent) on 2DEG samples, following by standard wet etch to form insulating trenches for SSDs. Figure 30 shows images of two typical SSDs fabricated by this method. Although the images look rather satisfactory, so far the lithography is not reproducible. The possible reason that we have recently identified might be that the finite height

of the Hall bar may lead to false reference points for the nanolithography, since the AFM was not programmed to following the topography. We are currently trying to move the AFM probe to always go back to certain reference positions after each part of the lithography and hope this will solve the problem. SSD-structures made using AFM-lithography In Year Two of the NEAR project, the group at the University of Manchester started developing scanning probe microscope (SPM)-based nanotechnology, which could offer not only a convenient and simple way to fabricate nanodevices but also in situ control of relevant sample

Fig. 29: New mask set for LAO experiments. Green areas are the bond pads.

Fig. 30: AFM images of the SSDs after patterning and wet etching.


parameters during the lithography process. Initial work was focused on the mechanical approach, using a sharp SPM probe to scratch a thin layer of the photoresist on top of the sample.

To achieve more reproducible nanolithography, in Year Three we moved to the electrochemical approach, namely the technique of local anodic oxidation (LAO). In a local anodic oxidation experiment, a thin water film covering the sample surface under humidity of normally over 40% serves like an electrolyte between a sample (anode) and the tip (cathode). The negatively biased tip imposes an external electric field which dissociates water molecules into oxidizing species, presumably OH–. The field further enhances vertical drift of these species away from the tip towards the surface where they react with underlying atoms to form a localized oxide beneath the tip. The oxidized areas have an increased volume (typically by around 100%), and hence can be imaged conveniently using AFM immediately after the oxidation. Figure 31 is a 3D AFM image of a thin oxidation line created by LAO.

Fig. 31. A typical oxide line created by local anodic oxidation on an InGaAs-InAlAs heterostructure. The height of the line, 10-15 nm, is a good measure of the oxide depth because of the ~100% increase in volume after the oxidation.

Fig. 32. I-V characteristic of an SSD made by thelocal anodic oxidation nanolithography on an InGaAs-InAlAs heterostructure after removing the InGaAs cap layer.

LAO nanolithography was performed on two material systems. When an InGaAs-InAlAs

heterostructure was used, wet chemical etching was followed to remove the oxide and then a selective etching in HCl:H2O = 1:2 was used to selective remove the InAlAs barrier without attacking InGaAs. This requires the InGaAs cap layer to have little Al mixture during growth, which however turned out to not be the case in our wafer because it is rather difficult. Nevertheless, we have made some SSDs successfully, and Figure 32 shows a typical I-V characteristic of an InGaAs-InAlAs SSD.

The reason that a selective etching was needed for an InGaAs-InAlAs heterostructure is the low density of surface states and hence a small depletion depth. This is not the case for GaAs-AlGaAs heterostructures. It was expected that even a 10 nm deep trench would be sufficient to deplete the 2DEG beneath in a shallow 2DEG heterostructure. Actually, the large depletion depth in a narrow GaAs 2DEG channel allows designs of SSDs with a very large channel width, allowing a large forward current.

Figure 33 shows the I-V characteristic of a typical GaAs-AlGaAs SSD made by the local anodic oxidation nanolithography, without any wet chemical etching, measured at 75K. At room temperature, the I-V curve is still nonlinear, but considerable leakage current arises, because a relatively deep (about 50 nm) 2DEG wafer was used. Figure 34 shows the I-V curve of another SSD made from the same GaAs-AlGaAs heterostructure but with a slightly wider channel, leading to a zero-threshold voltage. Although the current under reverse bias is not zero, the


device, if used for high-frequency microwave detection will not need any DC bias. For both devices, the forward current is about 30 to 50 times higher than earlier SSDs made from InGaAs-InAlAs or InGaAs-InP heterostructures. This is certainly a very good property for high-frequency performance since the impedance and therefore the RC time constant is low.

Fig. 33. The I-V curve of a typical GaAs-AlGaAs SSD made by the local anodic oxidation nanolithography, without any wet chemical etching, measured at 75K and110K, respectively. At room temperature, the I-V curve is still nonlinear, but considerable leakage current arises, becausea relatively deep (about 50 nm) 2DEG wafer was used.

Fig. 34. Another SSD made from a GaAs-AlGaAs heterostructure but with a slightly wide channel, leading to a zero-threshold voltage. Although the current under reverse bias is not zero, the device, if used for high-frequency microwave detection will not need any DC bias.

The scanning probe microscope-based nanolithography was also used to fabricate self-switching transistors (SSTs), which are essential for active logic gates. Figure 35(a) shows an atomic force microscope image of a typical self-switching transistor, fabricated on a GaAs-AlGaAs heterostructure by scanning probed based nanolithography following by removing the oxide in the trenches in diluted HCl. The depth of the trenches is about 15nm, sufficient to deplete the 2DEG beneath at temperatures below 150K. The transistor behavior, measured at 150K, is shown in Figure 35(b). Progresses to incorporate the SSTs with SSDs for logic gates, particularly inverters, are being made.


Fig. 35. (a) An atomic force microscope image of a self-switching transistor, fabricated by scanning probed based nanolithography following by selective etching. (b) Transistor behavior of the SST shown on the left at 150 K.

Fabrication of Si based devices

High resolution lithography The Si devices were patterned by mixing and matching UV lithography, and by e-beam lithography. The mesas for the devices, including the alignment marks, were patterned by UV lithography. The smallest details of the devices were defined by electron beam lithography (EBL). Moving from one device site to another was automatic. The exact location for the device was found by scanning small areas around four alignment marks positioned 140 um apart. We have used a 120 nm thick layer of PMMA as EBL resist. After exposure, the PMMA was developed in IPA with ultrasonic agitation. Pattern transfer During the experiments, it was found that PMMA mask is not resistant enough for dry etching the structures. The edges of the windows opened in PMMA by e-beam lithography weared and rounded during dry etching of silicon and, consequently, the walls became tilted. For the fabrication of the SSD and TJB devices we had to develop a new patterning and etching process. This process is based on etching selectivity between Si and SiO2. A thin layer of SiO2, about 30 nm, is formed by thermal oxidation on top of the Si layer. The SiO2 film is first patterned in CHF3 / CF4 plasma using a 120 nm thick PMMA mask. The silicon film is then etched in Cl/He plasma using the oxide film as a hard mask. The selectivity between SiO2 and Si in CHF3 / CF4 plasma is 10 and between Si and SiO2 in Cl/He plasma is about 25. Figure 36 shows etched trenches in polysilicon using the process described above. The oxide mask was 30 nm thick and the poly-Si layer 180 nm thick. The narrowest trench is 16 nm wide. The walls are vertical and the resulting aspect ratio is more than 10.

S

D

Gate


Fig. 36: SEM images of trenches dry etched in poly-Si. The etching was done through a 30 nm thick oxide mask. The oxide mask was patterned using e-beam lithography and dry etching. The narrowest trenches are 16 nm wide and 180 nm deep.

The actual devices were processed by combining e-beam lithography and standard CMOS processing steps. First the SOI (here abbreviation SOI refers also to poly-Si on insulator) wafer was implanted with phosphorous to obtain highly doped contacts. Photoresist served as an implantation mask that protected the active area of the devices. Then the large scale mesas were patterned using UV-lithography and plasma etching. The e-beam lithography/oxide hard mask procedure described above was utilized in small scale device patterning. This was followed by thermal oxidation which further reduced the device dimensions and annealed the damage introduced by the Cl/He plasma. The TBJ devices also require a top gate. We used a LPCVD p-Si gate that was highly doped by implantation and patterned by UV-lithography.

Fig. 37: SEM image of a poly-SOI SSD (48 nm wide and 320 nm long channel) and drain-source current as a function of applied drain-source voltage at different substrate biases.

Figure 37 shows an SEM image and drain-source current-voltage characteristics of a poly-SOI SSD at different substrate biases. The diode like behavior of SSD is not observed and the characteristics are more or less symmetric. Similar device fabricated on a (single crystalline) SOI wafer shows nearly the same behavior (Figure 38). To test the concept of SSD we made a SSD


with a side gate (Figure 39). When the side gate is shorted with the drain we can observe an asymmetric diode like behavior.

Fig. 38: SEM image of a SOI SSD (86 nm wide and 200 nm long channel) and drain-source current as a function of applied drain-source voltage at different substrate biases.

Fig. 39: SEM image of a SOI SSD with a side gate (91 nm wide and 200 nm long channel) and drain-source current as a function of applied drain-source voltage. The side gate is shorted with the drain and substrate is grounded.

In diode logic amplifying elements are needed between consecutive stages. We have fabricated side gated FETs and side gated SSDs which behave as FETs. Figure 40 shows an SEM image of a side gated FET and the corresponding I-V curves at various gate voltages. It can be seen that the side gate clearly controls the channel. The transconductance is relatively small but it can be improved by reducing the thickness of the trenches.

In addition of SOI SSDs, SOI TBJs were processed on the wafers. Figure 41 shows SEM micrographs of different SOI TBJ devices.


Fig. 40: SEM image of a sidegated FET and the I-V curves measured from the device. The measurements were performed at RT at various substrate biases and gate voltages.

Fig. 41: SEM pictures of SOI TBJs after e-beam lithography, oxide hard mask etching and SOI etching. Fabrication of Si TBJ- and SSD-structures The Si devices were patterned by mixing & matching UV lithography and e-beam lithography. The mesas for the devices, including the alignment marks, were patterned by UV lithography. The smallest details of the devices were defined by electron beam lithography (EBL). Moving from one device site to another was automatic. The exact location for the device was found by scanning small areas around four alignment marks positioned 140 µm apart. We have used a 120 nm thick layer of PMMA as EBL resist. After exposure, the PMMA was developed in IPA with ultrasonic agitation.

For dry etching of the devices, we use a hard SiO2 mask which was first patterned using PMMA mask. Here we utilize the etching selectivity between Si and SiO2. The details of the processing steps are described above. In Figure 42 SEM images of an SSD, side gated FET and TBJ are shown. The trenches are typically 30 nm or 50 nm wide. The nominal channel length was varied between 500 and 1000 nm and the width from 50 to 100 nm. The final dimensions are slightly smaller than the nominal ones due to the second oxidation step after the etching of the trenches. The final thickness of the SOI film is about 150 nm.


Fig. 42: SEM images of a SOI SSD (left), SOI sidegated FET (middle) and SOI TBJ (right).

With the exception of e-beam lithography, standard CMOS processing steps are used in the fabrication. First, the SOI wafer was implanted to obtain highly doped contacts. Photoresist serves as an implantation mask that protects the active area of the devices. A second, in some case also third (see below), implantation step was used to tune the channel conductivity. The TBJ devices also require a top gate. We used a LPCVD p-Si gate that was highly doped by implantation and patterned by UV-lithography. Finally, aluminum leads were defined by UV lithography and wet etching. Self-aligning fabrication process During the first year of the project, it was found that n-type silicon SSD devices do not function properly. The I-V curves of n-type devices tend to be more or less symmetric. For an SSD there are two opposing demands: The series resistances should be as low as possible and, on the other hand, the doping level in the channel should be low. Technologically it is very difficult to achieve this by lithographical means because of the small dimensions and the very high precision of the alignment required for the mask for implantation. To circumvent this problem, we developed a self-aligning process for the control of the doping level in the channel. The method is based on the different segregation coefficients of p-type and n-type dopants in silicon. The devices are first implanted with boron, followed by compensating implantation with phosphorus. During thermal oxidation of compensated silicon, boron tends to enrich in oxide while phosphorus tends to enrich in silicon. When the surface-to-volume ratio in the channel is larger than in the leads, a large change in the compensation ratio is seen in the channel, leading to an increase in the resistivity in the channel. Also, in uncompensated p-type devices the channel doping decreases during oxidation, but the effect on device properties is not as large as in compensated devices. We have filed an announcement of innovation of this self-aligning process and will later apply for a patent. Results of electrical measurements for the new p-type SSDs and FETs and n-typeTBJs are given in the next section, 6.2 Discrete nanodevices.


6.2 Discrete nanodevices

In this section we report on selected experimental studies performed with discrete NEAR devices, i.e. the three terminal ballistic (TBJ) junction and the self-switching device SSD. The samples under study were realized in three different material systems based on GaAs, InP and Si substrates. It is one of the major goals that NEAR devices can be monolithically integrated for the realization of logic gates and adders with an enhanced functionality. Consequently, discrete switching elements are required for amplification and buffering. These important switching properties have been observed and studied for a large variation of parameters, e.g. feature size, device geometry etc., and are presented in this chapter. The new transport properties of single TBJs and SSDs reflect the advancement of the project. The measurements with discrete devices allow us to extract important switching parameters, e.g. cut off frequencies and gain.

This part of the report starts with a description of the experiments, which allowed us to observe a coupling between the branches of side-gate controlled TBJs. We have exploited this branch-coupling for an enhanced switching efficiency. Device optimizations with respect to geometrical variations lead to the observation of transistor performance at room temperature in discrete, monolithic three terminal junction. This section is followed by a short review on the rectification properties of a multi-terminal junction with four inputs. Here the AND gate is clearly demonstrated. Pronounced rectification in SSDs at room temperature is recapitulated for devices fabricated in GaInAs/InP and InGaAs/InAlAs as well as for Si SSDs. The last section deals with the high frequency response of TBJs and SSDs culimates with the highlight that rectification function of an SSD was still observed at a frequency higher than 100 GHz. Enhanced switching gain in a side-gated TBJ

We have observed an enhanced switching effect in side-gate controlled TBJs in the nonlinear transport regime. It is found that voltage sweeps applied to the side-gates of the TBJ lead to pronounced voltage differences between the branches resulting in gain. The switching gain increases super-linearly with the bias voltage between the source and the drains, which is interpreted in terms of a capacitive coupling of the branches.

A scanning electron microscope graph of a TBJ with a length of the branching section of 70 nm is shown in Fig. 43. 180 nm wide and 90 nm deep trenches define the TBJ as well as two lateral side-gates further used to control the switching of electrons into either of the branches.


Rs

Vs

Vgl Vgr

Vbias

Rb Rb

Vbl Vbr

stem

leftbranch

rightbranch

leftgate

rightgate

l = 70 nm

Fig. 43: SEM image of a side-gate controlled TBJ in differential amplifier configuration.

Switching characteristics of the TBJ were analyzed using the setup schematically sketched in Fig. 43. The bias voltage Vbias was applied between the source and the drains in series with resistors Rb = 10 MΩ. High impedance voltmeters were used to detect the voltages Vbl and Vbr at the reservoirs of the left branch and the right branch, respectively. The stem reservoir was connected to ground via a resistor Rs = 120 kΩ. The measurements made to reveal the physical origin of the capacitive coupling have been performed at 4.2 K by immersing the samples in liquid helium. All other measurements were conducted at room temperature.

In order to investigate switching of electrons in the TBJ we have detected the voltage differences Vbl - Vbr for voltage sweeps at the side-gates in push-pull fashion, i.e., ∆Vgl = -∆Vgr, with voltages Vgl and Vgr applied to the left and right side-gate, respectively. In Figure 44(a) Vbl and Vbr are plotted versus ∆Vg = Vgl-Vgr+Vg,asym for different bias voltages. For the sake of clarity we have shifted the gate voltage difference by Vg,asym = -0.38 V, which we relate to an unintended asymmetry of the TBJ. For ∆Vg < -0.2 V and Vbias = 1.75 V electrons are directed effectively into the right branch and the current into the left branch vanishes. Thus the voltage Vbr = Vbias - Ir Rb. In contrast, the voltage at the left branch Vbl = Vbias - Il Rb tends towards Vbias as Il is negligible small. With increasing ∆Vg the current through the right branch Ir decreases and Il simultaneously increases. For ∆Vg > 0.2 V the right branch is pinched off (Vbr ≈ Vbias). As one can see in Fig. 44(a) the described switching behavior is in fact similar for Vbias = 1.00 V and 0.50 V. However, the voltages Vbl and Vbr do not reach the applied bias voltage for |∆Vg| < 0.2 V, indicating that for smaller Vbias the switching of electrons is less efficient.


-0.2 -0.1 0.0 0.1 0.20.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0a) Vbias=

1.75 V 1.00 V 0.50 V

Vbr (V

)

Vbl (V

)

∆Vg (V)-0.2 -0.1 0.0 0.1 0.2

-2

-1

0

1

2

3

0.0 0.8 1.650

100150200250300

∆Vg (V)

∆Vb (V

)

Vbias

= 1.75 V experiment theory

b)

Vg,

min (m

V)

Vbias (V)

Fig. 44: (a) Voltage Vbl,r detected at the left and right branch reservoir vs the voltage difference ∆Vg = Vgl - Vgr + Vg,asym varied in push-pull fashion, i.e. ∆Vgl = - ∆Vgr. (b) Voltage difference ∆Vb = Vbl-Vbr at the branches versus ∆Vg and the gate voltage range ∆Vg,min needed to switch from ∆Vb = 0.5 Vbias to ∆Vb = -0.5 Vbias as a function of Vbias (inset). The calculated curve corresponds to ηg/Vs = 10.0/V, ηb/Vs = -0.36/V, G = 1.16 x 10-6 1/Ω and Vwp = 0.1 V.

We have been able to observe voltage gain for the present TBJ. As depicted in Fig. 44(b), for |∆Vg| < 0.1 V and Vbias = 1.75 V, changes in the voltage difference Vbl - Vbr exceed by far the gate voltage variation. In order to demonstrate that the switching efficiency of the TBJ depends on the applied bias voltage we have plotted in the inset of Fig. 44(b) the minimum voltage sweep Vg,min required for switching ∆Vb from 0.5 Vbias to -0.5 Vbias versus bias voltages ranging from Vbias = 0.1 V to 1.75 V. Vg,min decreases with increasing Vbias reflecting the enhanced switching properties for higher bias voltages, e.g., Vg,min = 65 mV for Vbias = 1.75 V whereas Vg,min = 225 mV is required in the case of Vbias = 0.5 V. Thus, the switching is demonstrated to depend sensitively on the bias voltage Vbias.

In order to describe the observed switching we introduce two switching parameters γl and γr. Using these parameters the currents Il and Ir through the left and right branch can then be described by the voltage differences between the left branch and the stem and the right branch and the stem:

)()1(21

slll VVGI −+= γ , )()1(21

srrr VVGI −−= γ , (1) with G a constant, which corresponds to the maximum conductance of the TBJ for a given working point. From the observed switching behavior it is clear that the switching field increases with the applied bias voltage and thus γl and γr are functions not only of the gate voltage differences ∆Vg, but also of the voltage difference between the branches ∆Vb. Very good fitting to the experimental data was possible using the following analytic expressions for the switching parameters:

( )[ ]sbbwpggl VVVV /))(tanh ∆+−∆= ηηγ , ( )[ ]sbbwpggr VVVV /))(tanh ∆++∆= ηηγ (2)


with ηg and ηb referred to as the gate efficiencies of the side-gate and the branches, respectively. Taking into account that the voltage at the stem can be expressed by Vst = (Il + Ir) Rs with Il,r = (Vbias-Vbl,r)/Rb, Equation (1) can be rewritten in the form:

⎥⎦

⎤⎢⎣

⎡−−−

+=−

b

sbrblbiasbl

lbblbias R

RVVVVGRVV )2(

21

/)(γ

(3)

⎥⎦

⎤⎢⎣

⎡−−−

+=−

b

sbrblbiasbr

rbbrbias R

RVVVVGRVV )2(

21/)( γ

(4)

We have solved these coupled equations [Eqs. (3) and (4)] iteratively. In Fig. 2(b), a

calculated ∆Vb versus ∆Vg characteristic is shown for Vbias = 1.75 V with ηg/Vs = 10.0/V, ηb/Vs = -0.36/V, G = 1.16 10-6 1/ and Vwp = 0.1 V. It can be seen that the calculated ∆Vb(∆Vg) trace fits very well to the experimentally observed curve. This result indicates that the voltage differences between the branches influences the effective switching voltage.

0.0 0.5 1.0 1.5

0

-10

-20

-30

-40

exp. data ηb/Vs= -0.50/V ηb/Vs= -0.38/V ηb/Vs= -0.25/V η

b/V

s= 0

g max

Vbias

(V)

Fig. 45: Maximal differential voltage gain gmax as a function of the bias voltage Vbias. The data extracted from the experiment () is plotted together with curves calculated for different gating efficiencies ηb/Vs. For ηb/Vs = 0 (no bias induced gating) gmax is increasing linearly with Vbias. However, a nonlinear behaviour was found for finite selfgating efficiencies (ηb/Vs < 0) in agreement with the experimental data.

To clarify the role of the intrinsic switching field on the TBJ gain characteristic we have experimentally analyzed the maximum gain for different bias voltages and compared it to the calculated values extracted from Eqs. (3) and (4). In Fig. 45 this values are plotted versus Vbias. For bias voltages up to 0.5 V gmax increases almost linearly with Vbias reflecting a linear response of the gain to side-gate induced voltage changes. Here the side-gate controlled switching dominates. With increasing Vbias > 0.5 V gmax increases super-linearly indicating that voltage differences between the branches have a significant influence on the effective switching field. Our observations show that the branches have gate functionality similar to the side-gates, e.g., a more positive voltage at one branch relative to the other branch increases the conductance of the latter. This can be explained in terms of a capacitive coupling between the left and right branch.


This newfound nanoelectronic capacitance may be used to increase the functionality for a given number of basic switching units. Functioning discrete amplifying elements at 300 K

We have succeeded to demonstrate discrete amplifying elements on the basis of asymmetric TBJs. The nanoelectronic amplifiers were fabricated on the basis of high mobility GaAs/AlGaAs HEMT structures with a 2DEG 50 nm below the surface. At 4.2 K the mobility is 1 x 106 cm2/Vs. The working principle of the amplifiers utilizes one branch of the TBJ itself as monolithic and short gate exploiting the capacitive coupling between the branches in the non linear transport regime.

It has been found that coupling between the branches is enhanced by breaking the specular symmetry of the TBJ with respect to the stem axis. As one can see in Fig. 46 the branch which was found to serve as gate shows a constriction close to the intersection, at which the gate branch is connected to the TBJ junction. In order to demonstrate an inverter like function with gain the stem and the other branch were used as source and drain, respectively. It is demonstrated, that the channel can be efficiently controlled by the right gate.

Fig. 46: Schematic circuit of the inverter-like layout used to characterize the voltage gain of an asymmetric Y-branch switch. The inset shows an SEM image of the TBJ branching section. The right branch is narrowed down to a width of 70 nm at the intersection. This branch was used as controlling gate. Room temperature amplification of 8 is demonstrated using the tiny, monolithic branch gate.

Voltage-voltage characteristics of the asymmetric TBJ junctions at 4.2 K are depicted in Fig. 47 With increasing source to drain bias voltage the decrease of the voltage detected at the left branch for increasing right gate voltage is enhanced drastically. The voltage gain defined as g=|dVbl/dVbias,r| reaches maximal values of 580 for the present structure.


-0,3 -0,2 -0,1

0,5

1,0

1,5

2,0gmax = 580

Vbias,l

Vbl (V

)

Vbias,r (V)

Fig. 47: Voltage-voltage characteristic of the inverter as presented in Fig. 463. The measurements were carried out at 4.2 K. Maximal gain values of 580 are observed in the measurements.

0 100 200 300

10

100

|gm

ax|

T (K)

Fig. 48: Maximal voltage gain versus temperature. The inset shows the Vbl (Vbias,r) characteristic at room temperature.

The temperature dependence of the maximum voltage gain extracted by numerical differentiation of the Vbl – Vbias,r relation was determined for temperatures ranging between 4.2 and 300 K. The results are presented in Fig. 48. The voltage gain decreases with increasing temperature, reaching a value of 8, when combined with inversion, at room temperature. These results demonstrate that nanoelectronic TBJ junctions can be used as inverter-like amplifiers with gain at room temperature. Multi-terminal ballistic junctions as multi-input AND gates

In analogy to three terminal ballistic junctions a multi terminal ballistic junction can be introduced. The main part of Fig. 49(a) shows a scanning electron microscope (SEM) image of an example of such a multi- (in this case five-) terminal junction fabricated in the InGaAs system. One of the difficulties during the fabrication of such a device is that the middle part of the junction is getting larger than 100 nm. This is because each channel joining the middle part of the


junction has finite width and having five of them joining together makes the middle part larger than in the TBJ case. For the presented device the width of the channels is ~150 nm and the size of the middle part of the junction is ~500 nm in diameter. Here we should note that these sizes are larger than the value of the electron mean free path at room temperature, lmfp ~ 150 nm, extracted from Hall effect and longitudinal resistance measurements. Nevertheless, this five-terminal junction exhibits nonlinear electrical properties which are expected to be observed for a ballistic junction (similar to TBJs) and which are not observed in the conventional diffusive multi-terminal junctions. Fig. 49(b) shows functionality of the five terminal junction as an AND gate at room temperature. As can be seen from the table, if a negative voltage is applied to one (or more) of the contacts while the other contacts are grounded, then the voltage at the probe which is floating and serves as an output will be close to the applied negative voltage. The effect is basically the same as in TBJs, however, the voltages applied to the device are higher than previously for TBJs. This experiment shows that the extension from three to multi terminal ballistic junction is valid and that these multi-terminal ballistic junctions can function as multi-terminal logic gates.

Fig. 49: (a) SEM image of the central part of the five-terminal junction. The schematics show the measurement circuit used for demonstration of multi-terminal AND logic gate. (b) Experimental AND truth table obtained from (a).


Fig. 50: Current-voltage characteristic of three SSD devices fabricated from the GaInAs/InP heterostructures with different channel widths, measured at room temperature.

GaInAs/InP and InGaAs/InAlAs based SSD devices

Systematic studies on the dependence of the device characteristics on the device geometrical parameters (such as length, width, shape, etc) as well as under different physical conditions (such as temperature, illumination, DC/AC bias, etc) have been carried for SSD devices made from GaInAs/InP materials. A series of optimized device parameters have been obtained. Here we show in Fig. 50 that the dependence of the characteristics of the SSD devices on the width of channel. Clear evidence of the rectifying effect is seen in the measured I-V characteristics of the three SSD devices. In addition, it is seen that as the width of the channel of the SSD device increases, the current level at a given forward bias voltage increases. This is a behavior as we expected for the SSD devices. The measurements also show that at a large channel width, W=100nm, the SSD devices exhibit a current leakage in the reverse bias condition, and the overall I-V curve tends to show the behavior of a conventional. A further study is needed to understand better the origin of the current leakage of the SSD devices in the reverse bias condition.

We have also fabricated SSD devices on In0.53Ga0.47As/In0.53Al0.47As heterostructures grown at UMIST. Experiments performed for SSD devices made from In0.53Ga0.47As/In0.53Al0.47As heterostructures have shown differences in device performance from Ga0.25 In0.75As/InP based SSD devices fabricated previously in Lund. Fig. 51 shows a typical current-voltage curve of a device fabricated from the In0.53Ga0.47As/In0.53Al0.47As heterostructures. No obvious leakage current was found, as was expected from the higher conduction band-offset in this material compared to the Ga0.25In0.75As/InP system.

The large band-offset also allows for stronger confinement of the two-dimensional electron gas in the heterostructure. Hence, we expect the devices made from the In0.53Ga0.47As/In0.53Al0.47As wafers should be able to function under the condition of large bias, which is useful for logic or switching applications. Experimentally, SSDs have been shown to work at biases up to ±16 V.


-0.5

0

0.5

1

1.5

2

2.5

3

-4 -3 -2 -1 0 1 2 3 4I (

uA)

V (V)

Room temperature

Fig. 51: Current-voltage characteristic of a SSD device fabricated from the In0.53Ga0.47As/In0.53Al0.47As heterostructures measured at room temperature. Silicon based SSD devices

We have been able to realize SSD devices in Si using the process described in WP1. Devices on two wafers with different compensation ratio were fabricated. For comparison, only half of both of the wafers was compensated, i.e., was implanted with both boron and phosphorus, the other half was implanted only with boron. For the wafer W1 the total doses were 2.4E13 cm-2 and 3E12 cm-2 for boron and phosphorus, respectively. For the wafer W2 the values were 5E13 cm-2 and 5E12 cm-2. These doses resulted in net carrier concentrations of ~ 4E17 cm-3 and ~3E17 cm-

3 on wafer W1 and 9E17 cm-3 and 5E17 on wafer W2. SSDs were fabricated on both of the wafers, FETs only on wafer W2. The thickness of the final devices is about 140 nm. In the following we use the abbreviations P and P/N for the uncompensated and partially compensated devices.

The nominal dimensions of the devices on wafer W1 were width 50 nm, 100 nm or 200 nm and length 500 nm, 700 nm or 1000 nm. By nominal dimensions we mean here the dimensions of the design of the etching mask defined by e-beam lithography. On wafer W2 the nominal widths were 50 nm, 70 nm and 100 nm. The actual channel width is about 20 nm smaller than the one measured from the SEM images because of the thermal oxide grown to passivate the silicon surface. The width of the etched trenches was 30-40 nm on W1 and 50 nm on W2. An SEM image of a Si SSD is shown in Fig. 52.

Fig. 52: SEM image of a Si SSD. The nominal dimensions of the device, measured from the image, are: channel width 57 nm, channel length 1020 nm and trench width 43 nm. The corners of the trenches are rounded to improve the control of the self-gating effect.

Fig. 53 shows the effect of the partially compensating implantation. The curves with open symbols are measured from devices located on the uncompensated half of the wafer W1. The curves are not completely symmetric but the devices start to conduct at 0.5 V to 1.0 V at positive and negative bias. On the other hand the partially compensated devices show asymmetric I-V


-4,0 -3,5 -3,0 -2,5 -2,0 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0-2,5

-2,0

-1,5

-1,0

-0,5

0,0

0,5

1,0

1,5

2,0

2,5

(a)

P, W = 50 nm L = 715 nm P, W = 57 nm L = 1024 nm PN, W = 57 nm L = 725 nm PN, W = 57 nm L = 1020 nm

Wafer W1

Cur

rent

[µA

]

Voltage [V]

Fig. 53: I-V curves measured from SSDs fabricated on both compensated (filled symbols) and uncompensated (open symbols) halves of the wafer W1. The improvement in the diode like behavior is obvious.

curves and the behavior is like that of a diode. The nominal channel width of the devices is 50-60 nm. The effect of the length of the channel is clearly seen in the characteristics.

Figure 54 shows the effect of the compensation on the threshold voltage. The measurements were carried out by connecting the anode to ground and sweeping the cathode voltage and the other way around. In both biasing directions the devices show diode behavior.

Fig. 54: I-V curves measured from partially compensated SSDs by grounding first the anode and sweeping the cathode voltage from -4 V to 4 V, and then with the cathode grounded and sweeping the anode voltage. (a) An SSD fabricated on the wafer W1. The threshold voltage is about 1.7 V. (b) An SSD fabricated on the wafer W2. The threshold voltage is about 2.7 V. RF response of GaAs based TBJs

We have investigated room temperature direct current (DC) and alternating current (AC) characteristics of monolithic three terminal AlGaAs/GaAs devices with the aim to realize

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transistor functionality. We have been able to observe differential average voltage gain dVout/dVg larger than -10 in a range of 700 mV. Furthermore branch-gate functionality was observed up to high frequencies although no FET gate with a gate isolation is needed for this transistor type. Depending on the working-point cut-off frequency in the order of several GHz were found.

The samples were fabricated by high resolution electron beam lithography and wet etching of GaAs/AlGaAs modulation doped heterostructures with a two dimensional electron gas located 80 nm below the surface. By removing 100 nm of the upper surface layers, three large electron reservoirs were connected by a nanoelectronic GaAs/AlGaAs TBJ. Fig. 55 (right part) displays a scanning electron micrograph of the sample and the experimental setup. The dimensions of the constriction area and of the gate-branch are 200 nm. The left contact of the structure is connected to the gate voltage source while the upper and lower contacts are used as source and drain, respectively.

The gate voltage (Vg) is applied at the branch-gate and the bias voltage (Vds) is applied between the drain and the source of the channel. These voltage sources are used to determine the input- and output- characteristics of the TBJ transistor. Furthermore, they were tuned to define the working points for higher frequencies. The resistors Rg and R define the specific working point of the sample.

To contact the sample we used two PicoProbe® probe tips, each consisting of three pins which fit to HF contact pads (Fig. 55, left part). The two external ones are used as ground and the internal one is exploited as the signal pin. The distance between the pins is approximately 150 µm. Before the HF measurements the system was accurately calibrated with a calibration device as reference.

Fig. 55: Left part: Optical microscope image of the whole sample. The design of the gold contacts was optimized to fit to pico probes of an HP network analyzer. A TBJ sits in the center of the device shown as inset in the right part by an SEM image. Right part: Electrical circuit of the experimental setup.

In the last few years three terminal devices provided several possibilities to solve complex, electronic multi-device problems using only one structure or a combination of a few. For example the usage of Y-branch switches (Y-shaped TBJ) as a self-gating electron wave guide, a Schmitt-Trigger, or a part of ballistic half-adder was demonstrated and reported in multiple publications. Although the achievements of the TBJ are remarkable, there have been no measurements providing high frequency functionality at room temperature. Fig. 56 (left) shows the electrical circuit of the measuring setup.

For the measurements we used a 10 Ohm resistor as Rg and a 30 MOhm resistor as R. The right part of Fig. 56 shows the Vout(Vg)-characteristic for different forward bias voltages. There are three typical regions in the Vout(Vg)-characteristic to be distinguished:


• Gate voltages smaller than the threshold voltage Vth, i.e. the voltage closing the channel completely (Fig. 56 right; area I), cause leakage current via the gating-branch into the channel.

• For Vth < Vg < Vinjection (Fig.56 right; area II) the drain current is controlled by the gating of electrons from the charges accumulated in the gating-branch.

• Gate voltages larger than Vinjection (Fig. 56 right; area III) create a breakthrough of the gating branch into the channel.

Referring to Fig. 56 (right) we can estimate the threshold voltage Vth = -0.3 V, the injection

voltage Vinjection = -2 V and the breakthrough voltage Vbreak > 2 V. Without a bias voltage the concentration of charges in the channel is negligible, so the dependency of Vout versus Vg should be comparable to a classical voltage divider. The potential barrier in the gating-branch vanishes for Vg < 0 and the current increases almost linearly in this region.

If Vds > 0, charges move through the channel and the gating-modulation of the conductance in the channel is detected via variations of Vout. Vds = 1 V leads to a maximum Vout of 0.75 V before the injection of electrons into the channel occurs. We emphasize that the maximum differential gain is still larger than -10 at room temperature.

Fig. 56: Left part: Electrical circuit for the characteristic-measurements. Right part: Vout(Vg)-characteristic for different bias voltages.

Fig. 57 shows the setup for the HF-measurement with an HP 8510C Network Analyzer. The equivalent circuit diagram consists of an HF-source, a capacitor and an inductor. The capacitor decouples the DC-signal from the AC-signal and the inductor serves as filter for the AC-signal then decoupled from the DC-signal.

To measure the rectification we swept the input power Pin from 0 dBm up to 18 dBm by varying the frequency f from 500 MHz up to 18 GHz.


Fig. 57: Scheme of the electrical setup used for the HF-measurements.

We have performed HF-measurement for 3 different working points of TBJs with respect

to three different areas I, II and III of the Vout(Vg)-characteristic referring to Fig. 56. The left hand side of Fig. 58 displays the variations of Vout versus the input power of the AC voltage at a fixed frequency of f = 500 MHz and at different Vds. Interestingly, the sign of ∆Vout(Pin) depends on Vg. These experiments demonstrate that TBJs allow to control via a tuning of the working point the sign of the output signal. Evidently, the rectification is closely correlated to the bending of the Vout(Vg)-characteristic. In the gating regime the output voltage change is positive. In contrast for the injection regime the corresponding output is negative. For Vds = -1V and any voltage Vg in the zone I the output voltage ∆Vout(Pin) is always negative and lowers rapidly till about 16 dBm. For larger power values ∆Vout approximates to a saturation value of about -1.5 V. With a bias voltage of Vds = 1 V, when Vg is in the range of area II ∆Vout(Pin) shows a similar behaviour, of course with a smaller amplitude. For voltages Vg in area III ∆Vout approximately increases constantly because of the large voltage distance with respect to the peak observed in the V-V characteristic, which marks the threshold of electron injection.

Fig. 58: Left part: ∆Vout(Pin) at a bias voltage of 1 V. Right part: ∆Vout(Pin) at a bias voltage of -1 V.

Fig. 59 shows the frequency dependence of ∆Vout /∆Vout, max for the different working

points and a constant input power Pin = 12 dBm. For all three working points we analyzed the


results in the frame of first order low-pass filter. The Fourier transform function of a RC low-pass filter is defined by:

RCjjH

ωω

+=

11)( .

Consequently, we fitted the output voltage to a fit function:

211

12

PP

H LP ++

=ω

,

with proper fitting parameters P1 and P2. The fit was analyzed to extract the cut-off frequency of the system.

The left hand side of Fig. 59 shows a Bode diagram for Vds = 1 V and Vg taken for area I, i.e. gate voltages smaller then the threshold voltage Vth. ∆Vnorm is the normalized ∆Vout relative to ∆Vout,max, which is expected to be the maximum ∆Vout at f = 500 MHz. ∆Vnorm decreases constantly. To extract the cut-off frequency fg we displayed the -3dB-level in the same diagram. The cut-off frequency fg therefore, was found to be larger than 1.5 GHz. For Vg in area III, i.e. gate voltages larger than Vbreak, ∆Vnorm is almost constant up 1.5 GHz and decreases for higher frequencies. Furthermore the cut-off frequency fg is now larger than 6 GHz. The centre picture of Fig. 59 displays the frequency dependence of ∆Vnorm for Vds = 0 and Vg in area II. It shows a similar behaviour. It is nearly constant up to a frequency of 0.5 GHz and decreases for higher frequencies. The cut-off frequency was found to be almost 5 GHz. On the right hand side of Fig. 59 a Bode diagram for Vds = -1 V and Vg in areas I and III is shown. For positive Vg (area III) the constant region is terminated at a frequency of 1 GHz. For higher frequencies, ∆Vnorm decreases. The cut-off frequency is larger than 3.5 GHz. When Vg is in area II, ∆Vnorm is nearly constant up to 3.55 GHz. The cut-off frequency for this combination of Vds and Vg is larger than 10 GHz. All characteristics show a peak at about f ~ 4.0 GHz. We refer this peak to a resonance in the TBJ-contact system.

Fig. 59: Frequency dependence of ∆Vout /∆Vout, max. Left part: Working point Vds = 1 V. Middle part: Working point Vds = 0. Right part: Working point Vds = -1 V. HF-measurements of single InGaAs/InAlAs TBJ devices

The goal of the high frequency (HF) measurements of single TBJ devices is to determine the speed of the devices. Our approach is to use the TBJ voltage rectification behavior, observed when the device is connected as in Fig. 60. The devices are made with the IEMN


InGaAs/InAlAs material. In the measurements, the central branch is grounded, while a voltage, VAPP, is applied to the right branch, and the voltage, VOUT, of the third branch is measured. Fig. 61 shows typical I-V and V-V characteristics of the device under this setup. Switching contacts does not affect the main rectification behavior of the device significantly; it only causes a slight change in the voltage saturation level at large positive applied voltages. The parameter which has a large effect on the voltage rectification behavior of the device is the device size. A small device with narrow, but electrically opened, channels is desired in these measurements.

The HF measurement setup is the same as shown in Fig. 60, where an ac voltage obtained from a signal generator is applied between two branches, while the out voltage is probed at the third branch. The output voltage is still measured with a standard DC voltage multimeter, and thus an averaged rectified ac signal is actually measured. We expect the voltage VOUT to be negative for the input signal with sufficiently large amplitude. Due to the narrow confinement of the TBJ device, the device has a high resistance, which is typically around 10 kΩ, and is clearly not matched with the 50 Ω probe station. We have so far not done any optimization for impedance matching.

From the DC measurements we note that for small voltages the measured V-V curve is almost linear. The rectification behavior of the TBJ devices is observed at higher applied voltages. In HF measurements, this means that for small applied signal amplitudes we expect only small or no rectified signal, i.e. VOUT = 0. At higher applied amplitudes the rectification should become stronger and VOUT should become large negative.

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app (V)

Fig. 60. SEM image of a TBJ device with measurement circuit setup. A voltage is applied between two branches, and the DC output voltage is measured at the remaining branch.

Fig. 61. Measured I-V and V-V DC-characteristics of the TBJ device with the setup as shown in Fig. 60. The voltage VOUT shows a clear rectification behavior.

First measurements were done with our standard mesa with the sample mounted and

bonded to a calibration board. Fig. 62 shows the frequency measurements. By fitting to a first order low pass filter, a large capacitance can be noted. The cut-off frequency at -3dB in this case was 3GHz. We assign this capacitance to the large mesa structure which is not optimized for high frequency measurements. To reach higher frequencies a new mesa was needed, designed to minimize the 2DEG area and get the contacts closer to the active device.

VAPP200nm

VOUT


Fig. 62: Frequency measurement for TBJ on standard mesa, measured on a calibration board. A first order low pass filter is fitted, giving a cut-off frequency (-3dB) of 3GHz.

The new mesa design is shown in Fig. 63. Each mesa is a 10x10µm2 2DEG area with three contacts. The contact layout is made to fit two ground-signal-ground probes used at standard probe stations. The active TBJ device is then fabricated in the center of the mesa. On the sample a matrix of 6x6 mesa structures are created. This makes it possible to produce 36 devices on one sample with small differences in size, allowing us to find an optimal one for the HF measurements.

Fig. 63: Left: Each sample consists of a matrix of 36 mesa structures. Right: Optical images show contacts and a single mesa before fabrication of a fine structure at the center of the mesa.

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Frequency measurements of a TBJ-device on HF-mesa are shown in Fig. 64. The observed resonances are highly reproducible and device independent, and therefore arise from the measurement setup. Note that for higher input powers the rectification gets stronger. This is also seen in Fig. 64b where the rectification is plotted against the input amplitude. From the dc characteristics it is possible to determine an expected VOUT, by looking at the response of the device to applied ac signal in one sinus period. The average value of this signal is the expected rectification output. Good agreement between measurements and calculated rectification is found. Up to 6 GHz we see no decay of the signal.

a)

b)

Fig. 64: (a) Frequency measurement for TBJ on HF-mesa. No cut-off can be seen up to 6 GHz. (b) Rectification strength for different input signal amplitudes at different frequencies. The solid curve shows the expected value calculated from the dc characteristics.

High-frequency measurements of SSDs

High-frequency characterisations of SSDs have been one of the key issues that the NEAR project addressed in the 3rd year. For the high-frequency experiments on SSDs, all four groups in the NEAR project have worked together. The following high-frequency measurements were performed in the Electromagnetics Centre for Microwave & Millimetre-wave Design and Applications, at the University of Manchester, where it is possible to measure devices up to 110 GHz at variable temperatures.

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Standard DC characterizations were carried out before high-frequency measurements. Fig. 65 shows the I-V curve of about six SSDs in parallel on a type B mesa, measured at room temperature under room light (due to the narrow channel, the devices are very light sensitive).

The microwave measurement setup is shown in the Fig. 66, which is the standard setup for characterizations of microwave diode detectors. The microwave was fed to the device via a modulator and a bias T network. It allowed us to feed the output signal from the SSDs into a preamplifier, which is AC coupled to the device, in order to achieve better signal to noise ratio. It also allowed an easy reading and monitoring from an oscilloscope. Most importantly, it enabled us to get rid of any thermal drift, and any offset voltage (due to light and temperature effects of the device and the DC meters). With the bias T network, we can measure the device performances at optimum DC bias currents when the IV trace showed the strongest non-linearity. The loss due to cables and connectors was taken in account and compensated in the following experiments unless stated otherwise. The 10 MΩ resistor is much larger than the sample resistance at optimum biases. The DC voltage drop over the resistor gives a good measure of the DC bias current.

Fig. 67 shows the output DC voltage versus frequency, from 50 MHz to 4 GHz, with the device biased at 500 nA. The microwave power applied was 0 dBm (1 mW). The peak and dip around 1GHz were most likely due to standing waves in the long rf cable used. Overall, the device shows no obvious decrease in the output in this frequency range. In these experiments, the rf power loses due to cables, probes and connectors can be neglected.

For experiments up to 20 GHz, the rf power loses in different parts of the setup must be

taken into account. The overall loses were measured using a rf power meter and the results are shown in Fig. 68. The output DC voltage as a function of frequency, with the device biased at 1.3 uA, is shown in Fig. 69. The nominal microwave power applied was kept at -5 dBm (0.316 mW), with the loses at different frequency points being compensated by tuning up the output of the rf power source. The result shows no obvious decrease in the output up to at least 20 GHz.

Fig. 66: Schematics of the microwave measurement setup.

Microwave generator modulator Bias network

GND GND

SSD array

pre

oscilloscope

10 MΏ


Fig. 68: The rf power loses as a function if frequency.

We have finally performed experiments up to 110 GHz. Due to the absence of a suitable modulator at such high frequencies, the noise level in the measurements increased dramatically. A lot of work was carried out to lower the noise, by increasing the integration time of the DC meter and averaging the output. Fig. 70 shows the frequency response at 100 nA DC bias up to 110 GHz.

Very short cables were used in the setup to reduce resonances at certain frequencies. The losses at different frequencies were compensated by the computer by adjusting the rf power at each point. As shown in Fig. 70, the output is fairly stable up to about 20 GHz. Above that, we see a decrease in the output, but from 100 MHz till 110 GHz, the output is reduced only by a factor of 3 or 4, meaning that the SSDs have a very good frequency response compared with normal diodes.

Fig. 67: Output DC voltage versus frequency with the device biased at 500 nA. The nominal microwave power applied was 0 dBm (1 mW).

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Fig. 69: Output DC voltage versus frequency with the device biased at 1.3 uA . The nominal microwave power applied was -5 dBm (0.316 mW).

Fig. 70: The frequency response at 100 nA DC bias up to 110 GHz.

This result is, to the best of our knowledge, the highest frequency performance that has

been demonstrated so far for a novel nanoelectronic device. With suitable design and optimizations, the device might well function in the THz regime, allowing many potential applications. This is promising also because the planar device structure allows for the detection of microwaves coming from the normal directions of the device surface, which is not possible for a normal detection diode. Moreover, our high-frequency measurements agree well with the device modeling performed on SSDs in the EU project NANOTERA. There it was predicted by means of Monte Carlo simulations that SSDs can operate well at THz frequencies.

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6.3 Circuit implementation

In this part of the report the applicability of TBJs (Three-terminal Ballistic Junctions) and SSDs (Self Switching Devices) to small-scale integration has been investigated. Simple logic ports and/or RF-circuitry will be designed and realized by integration of a few SSDs or TBJs. The design of circuits will be based on SPICE or Aplac simulations using a model for the nanodevice extracted from DC and AC measurements. Simple circuits containing a few nanodevice elements has been fabricated and characterized. The actual properties of the circuits has been compared with the simulation results to verify the model behavior. These models can be used in the future to design more complex circuits. We have also studied different ways to buffer individual nanodevices in order to study the cascade ability of these devices for circuit implementation.

This chapter is organised so that first a short summary of the work carried out in the WP 3 during the project years is given. Then the developed circuits classified according to the technolofies: SSD, TBJ, are given. The main emphasis in this section is in the circuit and electrical design and performance. The processing and device technology aspects are dealt in WP 2. Finally Aspects concerning higher integration levels are discussed, including a proposal for a more complex demonstrator.

In the first year report, basic building blocks, such as TBJ wire NAND, TBJ NMOS-type NAND, SSD DTL type OR, and TBJ half adder core, were demonstrated.

The work on Task 3 in the second year has concentrated on the medium and high level integration possibilities of the devices developed within the project. During the second year a concept and technology for construction of a TBJ full adder has been developed. It combines the half adder core with a number of wire NANDs. An SSD based half adder has been simulated. A scalable SPICE or APLAC compatible SSD model has been developed for both III-V and Si SSDs. Also a SPICE or APLAC compatible side gated transistor model has been developed based on 2D simulations.

The work in WP 3 in the third year has concentrated on realisation of Si single logic elements, compound semiconductor latches and full adders, all operating at 300 K. In addition, we have investigated the possibility to design complex circuits based on the logic elements demonstrated in the project. Si single logic elements were realised in 150 nm thick SOI substrate using side gate FETs and SSDs.. A proposal for complex circuit design of demonstrator was developed. The operation of a memory element, a Set-Reset-latch, was verified. Finally, the final goal in the project, the full adder operating at 300 K was demonstrated.

Circuits based on SSD devices

Single logic element in III-V heterostructures at 300 K with line widths 50-100 nm The diode behaviour can be used to design various logic circuits. The simplest form is the DDL (Diode-Diode Logic) where diodes act as input switches. Figure 71 shows a scanning electron micrograph of a DDL OR gate, which consists of two SSDs. The two inputs terminals are connected to the upper-left and lower-left corners, while the output is connected on the right side. The experimental result performed at room temperature, shown in Fig. 72, demonstrated an input-output voltage transfer rate of about 80%.


Fig. 71: A scanning electron micrograph of a logic OR gate, which consists of two SSDs. The two inputs terminals are connected to the upper-left and lower-left corners, while the output is connected on the right side.

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time_OR1_293K_light_auto.txt -----20010720

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Fig. 72: The experimental result performed at room temperature on a logic OR gate as shown in Fig. 71, which demonstrates an input-output voltage transfer rate of about 80%.

Since the SSDs essentially act as passive diode devices, to cascade a large number of logic

gates, buffering is required at some points in the circuits. We have fabricated amplifying elements of the same complexity as the fabrication of SSDs. The same approach as for TBJ circuits, i.e. using a side-gated FET, was planned for buffering of SSD circuits. Figure 73 shows a scanning electron micrograph of a side-gated FET, fabricated from an In0.53Ga0.47As/In0.53Al0.47As heterostructure. In this device, the left and right terminals serve as source and drain, and the upper and lower contacts can be used as gates to influence the channel conductance and therefore the source-drain current.


Fig. 73: A scanning electron micrograph of a side-gated FET, fabricated from an In0.53Ga0.47As/In0.53Al0.47As heterostructure.

Single logic element in Si at 300 K with line widths 50-100 nm

Here we demonstrate a single silicon logic element operating at room temperature. As the elements we chose NAND and NOR gates realized using "PMOS-type" logic, which is a PMOS version of “NMOS-type” logic. In “NMOS-type” logic the switchs is realized with a NMOS-transistor common-source connection whereas the pull-up operation is realized using diode connected NMOS or an NMOS device connected as an active load. The devices were fabricated on silicon on insulator (SOI) substrates and the choice of the layout and dimensions was based on the characteristics measured from individual self switching devices (SSDs) and sidegate FETs (SG-FET). Simulations and device design PMOS-type logic was preferred to diode transistor logic (DTL). The reason is the lower power requirement as the input in PMOS logic is capacitive.

The design was started with a simple inverter simulation to evaluate the possible logic voltage levels available when using the characterized sidegate FET models. The inverter study was used as a basis for NAND and NOR gate design to estimate the required device dimensions. A basic input-output DC voltage characteristics from the first process run is shown in Fig. 74. With a -15 V supply voltage the output voltage range is quite limited as the output voltage does not reach - 8 V. This is due to the high threshold voltages of the sidegate FETs, in particular of the active M1 device. Another effect restricting the output swing is the parasitic resistances in parallel with the MOS channel resulting into voltage division at the output node. Due to the narrow widths of the devices the voltage amplification is quite small (~2 in the example of Fig. 1) which can be seen as the slope between – 10 V and – 8 V of the input voltage.


In Fig. 75 are shown SEM images of NAND and NOR gates. Results Two runs with slightly different designs were done. Measurements were performed as input-output voltage characteristics both of NAND and NOR gates. The output swing and amplification were of most interest. The first run gave functionally proper operation for both NAND and NOR but with very high operating voltage (-30…-40 V), threhold voltages Vth ~-7 V and rather poor transfer curves. The second run gave much more acceptable operating voltage

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DC-sweep of an SG-inverterAPLAC 7.80 User: VTT Tietotekniikka Mon Jun 28 2004

VoutV

Vin/V

Vout

Fig. 74: Simulated inverter input-output DC characteristics based on extracted SG-FET parameters.

InA

InB

InA ZH

Out InB

InA

Fig 75. SEM images of a) NAND and b) NOR gates (second design and run).


(-8 V), Vth -2…-3 V and good transfer curve for NOR but poor tranfer curve for NAND because of leaky switches. NOR gate The PMOS-type NOR gate (shown in Fig. 76) behaves like the inverter when the other input is connected to the ground. The measured curve is shown in Fig. 77 when the supply voltage is – 8 V (second design and run). The low level is close to 0 V, as it should be. The high level is –4.2 V, a little bit lover than the threshold voltage of ~6 V would give. The reason is the off-state leakage. The measured voltage gain 1.8.

Fig. 77: Input-output voltage characteristic curve of a NOR gate having a – 8 V negative supply voltage.

Device sizes of the active FET switches in these examples shown here were the same: channel width in horizontal direction is 60 nm as the length is 500 nm. In all the load FETs the channel width was 100 nm and the length 1200 nm.

NAND gate In a PMOS-type NAND as shown in Fig. 78 the output should resemble the inverter curve of Fig. 74 when the other input is connected to the negative supply voltage. A measured curve is shown in Fig. 79 for a NAND gate with a – 40 V supply voltage (first design and run). The

Fig. 76: NOR gate using PMOS-type logic.


behavior is functionally correct. The lowest – 24 V level is limited by the resistive voltage division caused by the leakage current through sidegate devices. The cause for the voltage upper limit being as low as - 17 V is due to the low amplification in the cascated SGTs and leakage of the SSD.

Fig. 79: Input-output voltage curve of a NAND gate with a - 40 V supply voltage.

As a conclusion we have demonstrated basic logic elements on Si operating at 300 K. We have also demonstrated that with process and device design optimization it is possible to reach practical performance level in supply and threshold voltage.

Circuits based on TBJ devices and point contacts

Various logic element circuits were designed based on integration of TBJ devices and point contacts. The functionality of the TBJ devices shows that various logic gates can be constructed from the TBJ devices. However, the TBJ devices alone do not give amplification. Thus, to make

Fig. 78: A PMOS-type NAND gate.

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Vin/V

Vout


the TBJ devices suitable for large-scale integration, amplification elements are needed in circuit design and implementation. To maintain the advantage of single-step lithography of the device layout, we have chosen to use in-plane gated quantum point contacts as amplification units. Fig. 80 shows the symbol of the TBJ unit we have used to in circuit designs. We have designed several circuits for logic gate elements. Fig. 81 gives a few examples. Some of them have been realized and characterized.

Fig. 80: Symbol for the TBJ unit. Input ports are labeled with letters A and B, while the out port is labeled with letter C. The output port can be used as an input for another nanoelectronic element.

(a) (b)

(c) (d) Fig. 81: Designed circuits for AND, NAND and Inverter logic elements. All these logic gates give amplification and can be fabricated by one-step lithography process using, e.g., nanoimprint technique. Here the symbol “PC” means lateral point contact. Set-Reset-latch

One of the simplest integrated circuit is the Set-Reset-latch (SR-latch), consisting of only two NAND gates. It is a compact memory cell, with two input signals, set (S) and reset (R), and two output signals, Q and it’s complement Q’. Q’ is the complement to Q or the Q-inverse. The state of the latch is determined by the output signal Q, having a high signal when the latch is active


and 0 when its not. Fig. 82(a) shows the circuit diagram of a SR-latch with two NAND gates. The corresponding truth table is given in Fig. 82(b). a)

b)

Fig. 82: a) Circuit layout for an in-plane SR-latch made of two NAND gates. b) Truth-table for the layout in a). Q0 is the current state and Q+ is the state the latch will change to. When both S and R signal is low the output is undefined (forbidden combination).

The realization of the SR-latch is made with two TBJ-based ANDs. Initially the device was operated based on the novel TBJ properties. However, due to impedance problems between the two inputs of the TBJs the device does not function properly. Instead the same device was operated based on the WNAND (wire-NAND) functionality. Characterization of the TBJ device as a WNAND gate is shown in Fig. 83. It is seen that as expected, it is easy to close the channel with negative gate voltages, but difficult to make it more open with positive gate voltages.

The problem of the fabrication of a SR-latch arises when trying to find two WNAND gates that have the same input and output levels. Since a feedback is used in a SR-latch it is essential that the levels are similar. If the levels are not defined similarly the latch will fall into a more stable state. Fig. 84(a) shows the SR-latch measurement setup. The sample contains two TBJ WNAND gates separated from each other by 175 µm. They are made in the same lithography step and just

separated with a large area of 2DEG. This was made to make sure that the two gates are totally independent and do not affect each other. The distance could be decreased to make the effective device size smaller.

Operation of the latch is shown in Fig. 84(b). After a short set signal, the Q-bit is set to high state and keeps at this high state until a reset signal deactivates it and switches it to low state. The same switching operation goes for the Q´-bit: a short reset signal set Q´-bit to high state and a set signal switches the Q´-bit back to low state. The input levels are set to 0V and -0.4V for

a)

0

1 10-5

2 10-5

3 10-5

4 10-5

5 10-5

0 0,5 1 1,5

Isd

Vsd

#Sample 040426

dVg= 0.5V

Vg= 0V

b)

Fig. 83: a) Setup for a WNAND characterization of the TBJ device. (b) Typical I-V characteristics for of the device. The different curves are measurement for different values of Vin2 with Vin1=0V.

S S R Q Q´ 1 1 Q Q´ 0 1 1 0 1 0 0 1 0 0 1 1


high and low signals. The low level is stronger than what is needed to switch the Q-bit and the Q´-bit, but gives a strong feedback signal to guarantee the switch of the states.

Nanoelectronic Half ADDER and HAST (Half Adder with Schmitt-Trigger outputs)

In this chapter we demonstrate a prototype of a compact logic half adder circuit (HA) based on a single TBJ structure exploiting a self-switching effect from a transport regime where ballistic injection of electrons dominates the transport across a central constriction to an internal gating regime, which allows a suppression of electron transport. The self-switching manifests itself in negative differential conductance. Thereby it is possible to simultaneously demonstrate logic-AND as well as logic-XOR gates without using external gates or any interconnects. The HA was realized by tailoring a single conducing layer. Principally a HA has two binary input variables X and Y and two output variables Z (sum) and C (carry) for basic binary computation. From the truth table of a HA presented in Table 1 it can be seen that the sum-bit is high (H) only for different binary levels of X and Y otherwise it is low (L). The corresponding logic functionality is fulfilled by a XOR gate. The second output which corresponds to the carry-bit of the binary addition is H only for both inputs being H, i.e. C = X AND Y. Therefore a HA allows the demonstration not only of single logic elements but also of a combination of elementary building blocks as depicted schematically in Fig. 85. In conventional CMOS technology an AND gate is build up of 4 transistors and 8 transistors are used for an XOR gate leading to a minimum number of 12 transistors needed for a HA. We demonstrate that nanoelectronic effects like ballistic rectification and selfgating allow the reduction of the number of single elements for a given functionality.

Q’

+V

Q

+V

S

R

Q’

a)

b)

0 80 160 240 320 400

R (V

)

Time (arb. units)

0

1

0

1

2

0

0

-0.5

-0.5S (V

)Q

(V)

Q’(

V)

Fig. 84: (a) Measurement setup for SR-latch. The sick-sack line indicates that the two TBJ WNANDs are separated with 175 µm. The applied input voltage is 10V and the resistance of the external resistors is 700 kΩ. (b) Demonstration of the latch operation. Logical high and low levels are 0V and -0.4V, respectively, for the input signals, and are 1V and 0.5V, respectively, for the output signals.


Table 1: Truth table of a HA. Fig. 85: Realization of a HA using AND and XOR gates.

We have developed an in-plane HA circuit. In our approach the HA consists of a multiterminal junction (MTJ) in combination with a constriction as shown in Fig. 86. The contacts labeled x and y form two branches and are used as input terminals. These branches lead into a stem, which splits into three branches. The upper one ends up in an internal gate, the lower one located opposite to the gate entrance is used as output port c, whereas the middle branch represents the constriction k. On the other side of the constriction, the output port z is connected to port s via a narrow channel which is controlled by the internal gate1. The design of current channels in the half adder circuit as sketched schematically in Fig. 86 allows the use of internal gating effects for the operation of the device. Here, the upper branch adjacent to port c is used to gate the device section connecting port s with port z. Depending on the voltage at port c the internal gate controls the current from s to z efficiently.

x

y

gate

c z

k100 nmv s

Fig. 86: SEM image of a lateral GaAs/AlGaAs half adder structure after etching and prior to contact formation. Two branches x and y approaching from the left serve as inputs of the half adder. At their intersection they split into an internal gate, a narrow constriction k with a width of 100 nm and the outlet c. Directly The outlet z located directly at the right hand side of k is connected via a quantum wire to port s. The branch v in between x and y as well as the electrode w are used as control terminals.

In particular, internal gating allows a complete suppression of electron transport when the voltage at the internal gate respectively the voltage at port c falls below the threshold voltage Vc,th of the current channel. The constriction k which suppresses electron flow up to a critical voltage difference ∆Vcz between port c and port z. Whereby ∆Vcz depends on the height of the conduction band barrier at k and increases with decreasing width of the constriction.

A corresponding circuit diagram is depicted in the right part of Fig. 87. When selfgating takes place, the upper switch is closed and the lower switch is open, which corresponds to the switches represented by solid lines in the left part of Fig. 87. In the other case, when the switch

1 The probes w and v are used to measure the conductivity of the channels. They are not required for the half adder functionality of the device.


connecting the gate with port c is open and the switch representing the constriction k is closed (dotted lines) no gating takes place. In this situation electron transport occurs from c to z or vice versa, depending on the voltage difference between c and z.

y

x

c

gate

z

I

y

x

z

Vx

VzVc Vd

VsVyR

II

csk

Fig. 87: Schematic circuit diagram. When electrons are blocked by a barrier at k selfswitching dominates the switching, as sketched in the left part by open (dotted lines) and closed switches (solid lines). As indicated by two diodes the Y-junction in section II is used to rectify the input voltages Vx and Vx applied to the branches x and y.

Fig. 88: Internal-gating effects in the variation of the voltage Vz versus Vc. For |Vc| < 0.1 V with Vd = 0.1 V and Vs = 0.1 transport through the constriction k is blocked. In contrast for |Vc| > 0.2 V electrons pass k and Vz follows Vc. N-shaped negative differential conductance is observed for Vs =-0.1, -0.2 and -0.3 V. This effect allows to enhance the functionality of ballistic multi-terminal junctions.

As a first step we demonstrate that the above described functionality of switching between

the internal gating of the device and the injection of electrons into z via the constriction can be fully controlled by the voltage difference between port c and z. I.e., there is no need to vary the voltage at any other port. In Fig. 88 the dependence of the voltage at z versus voltage changes at c is plotted for voltages of Vs = 0.1 V to –0.3 V varied in steps of 0.1 V.

As a further step we have realized a half-adder (HA) circuit based on ballistic Y-branch junctions with voltage gain. The half-adder consists of two Y-branched junctions of narrow current channels coupled to each other by an internal gate and a tunnel barrier. Feedback coupled


TBJs were used as extremely compact Schmitt-Triggers (ST) for logic level restoration exploiting a switching bistablility. An SEM image of the HA-structure is shown in Fig. 89. The inputs x and y approach from the left hand side and split into an internal gate g and the carry-output c. The internal gate controls a wire section, which is connected via a small constriction k to the branching section. The control-terminal v is not used for HA-operation.

The HA-functionality of the device is due to a combination of a ballistic rectification effect of Y-branched nanojunctions and a selfgating effect. The input signals of the HA are applied to x and y, respectively. Due to the rectification in ballistic Y-branches the output signal Vc,HA as well as the voltage at the internal gate g tends to the lower of the two input voltages . Identifying the input signals with logic variables X and Y this leads to CHA = X AND Y which corresponds to the CARRY-bit of a HA. The second output of a HA, the SUM-bit ZHA, is related to the inputs by ZHA = X XOR Y, i.e. that ZHA is H only when different logic signals are applied to the inputs (otherwise ZHA = L). This logic operation, which in conventional electronics is realized by connecting several elementary logic gates, is reduced to the interplay of selfgating and blocking of electrons by the barrier k as described before. The outputs of the HA are each connected to one side-gate of a feedback coupled TBJ. Feedback is realized by connecting one branch with the opposing side-gate. Selfgating between the branches closes the feedback-loop and leads to bistable switching with hysteresis.

Vbias

R=10MΩ

Vz,ST

Vx

Vy

Vc,HA

Vd

Vs

R=10MΩ

Vc,ST

Vz,HA

Vbias

500 nm

x

yv

gk

c zs

Fig. 89: SEM image of HA circuit in combination with a schematic view of TBJs working as output stages with Schmitt-Trigger characteristic.

Fig. 90: CARRY-output Vc,ST of the TBJ based Schmitt-Trigger vs the voltage Vx applied to the x-input of the HA. Inset: CARRY-output of the HA versus Vx. The dotted (straight) line corresponds to Vy = 0.1 V (Vy = -0.6 V) applied to the y-input of the HA.


HA-operation is demonstrated with the test setup depicted in Fig. 89. The input signals of the HA (Vx and Vy) are applied to terminals x and y. A supply voltage Vd= -0.05 V is applied via resistor Rs =10 MΩ to the SUM-output ZHA. The voltage at port s is Vs = -0.35 V. The SUM-output as well as the CARRY-output at c are connected to the input of TBJ-based ST. As shown in Fig. 89 feedback coupling needed for ST-operation is realized by connecting one branch to the opposite side-gate and controlling the TBJ with the second side-gate. The bias voltage Vbias = 1.5 V is applied via serial resistors Rb = 10 MΩ to the branches of the TBJ with the stem connected to ground.

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.10.0

0.5

1.0

1.5

-0.6 -0.4 -0.2 0.0-0.15

-0.10

-0.05

Vz,

ST (V

)

Vx (V)

Input Y = H Input Y = L

Vz,

HA (V

)

Vx (V)

Fig. 91: SUM-output Vz,ST after the ST vs the voltage Vx applied to port x of the HA. Inset: SUM-output of the HA vs Vx. The open (closed) circle corresponds to Vy = 0.1V (Vy = -0.6 V) applied to the Y-input of the HA.

In order to investigate the response of our device on changes of the input signals, the

output voltages of the HA and the STs were measured with high impedance voltmeters for varying Vx and different logic levels at Y. Fig. 90 shows the voltage Vc,ST at the ST as well as at the CARRY-output Vc,HA (inset) vs Vx for input X being H (Vy = 0.1 V) and L (Vy = -0.6 V), respectively. The dependence of the signal at the SUM-output of both the ST and the HA (inset) on Vx is illustrated in Fig. 91.

Half-adder functionality is demonstrated in Fig. 92 verifying the truth table of a HA. The input signals which are regarded as logic high for Vx, Vy = 0.1 V and logic low for Vx, Vy = -0.6 V are depicted in part (c) for all combinations of the logic input levels. The center part shows the SUM- and the CARRY-output of the HA vs. the logic input levels. For (X Y) = (H H) the signal Vc,HA at the CARRY-output of the HA is higher than the upper threshold of the ST whereas Vz,HA does not reach the lower threshold. Thus, the ST connected to the CARRY-output is in high state while a low signal is detected at the ST associated with the SUM-output. In case (X Y) = (L H) or (X Y) = (H L), Vz,HA exceeds the upper threshold of the respective ST whereas Vc,HA falls below the lower threshold leading to CST = L and ZST = H. Finally CST as well as ZST are L for (X Y) = (L L) since both output signals of the HA are below the lower threshold of the ST. Thus, ZST = X XOR Y and CST = X AND Y as required for a HA.

The presented half-adder structure demonstrates that an integration of logic functionality is feasible by exploiting nanoelectronic effects like ballistic rectification in nanojunctions. Selfgating between the branches of a TBJ allow the realization of a compact nanoelectronic Schmitt-Trigger further used to amplify the output signals of the half-adder structure. Due to a pronounced bistability the application of the ST led to well defined logic output levels with high noise margin.


Fig. 92: Demonstration of half-adder functionality versus all combinations of the logic input levels X and Y. (a) Output of the ST with the SUM-output Vz,ST and the CARRY-output Vc,ST of the HA coupled to the input, respectively. (b) SUM-output Vz,HA and CARRY-output Vc,HA of the HA-structure. (c) Voltages Vx and Vy applied to the inputs of the HA.

Concept development for a FULL-ADDER on the basis of a HALF-ADDER and coupled NAND-Gates

We have developed and realized a concept for a FULL-ADDER on the basis of the monolithic HALF-ADDER. For a further processing of the output signals of the HALF-ADDER we utilize a gating anisotropy observed during the second year of NEAR as an intrinsic and robust property of narrow (quantum) wire transistors. This gating anisotropy is demonstrated to be the basis for an extremely compact NAND gate. A short description of the narrow-wire NAND (WNAND) is given in the section below. Then we show that cascading of these devices allows us to realize a FULL-ADDER.

We begin by describing a compact, monolithic logic NAND-gate based on an in-plane narrow-wire transistor as shown in Fig. 93. The narrow-wire transistor is controlled by two lateral gates which serve as input terminals of the NAND-gate. It is found that the channel is controlled most efficiently by the side-gates near pinch-off. This non-linear gate-efficiency allows one to control the state (conductance) of the wire by the lower input signal (applied to the left and right side-gate). The compact logic NAND-gate features high input impedance, voltage gain and operates at room temperature.

In-plane gated narrow-wire transistors based on modulation doped GaAs/AlGaAs heterostructures show electrical characteristics similar to n-channel field-effect-transistors, i.e., the conductance of the channel between source and drain increases with increasing gate voltage. Gate voltage sweeps applied equally to the left and the right side-gates of a narrow-wire transistor lead to an inverter like output characteristic in source-configuration. However, an in-plane gated narrow-wire transistor can also be operated asymmetrically with voltage differences applied between the left and the right side-gates. We found that in this mode of operation the conductance of the narrow-wire is controlled more efficiently by the gate with the lower voltage. This observation is interpreted in terms of a voltage dependent gating-efficiency and is further exploited for the realization of a compact logic NAND-gate based on a single in-plane gated narrow-wire transistor (WNAND).


(a)

100 nm

Drain

Source

linkesGate

rechtesGate

(b)

V (X)gl

V (Y)gr

Vbias

V (X NAND Y)d

R=10 MΩ

(c) Fig. 93: (a) Electron microscope image of a narrow-wire transistor with a geometrical channel width of 100 nm. (b) Schematic for the measurement circuit. (c) NAND truth table (for the experimental verification see Fig. 82).

The narrow-wire transistors were realized on a modulation doped GaAs/AlGaAs heterostructure. Narrow-wire transistors were investigated for temperatures ranging from 4.2 K up to 300 K with the measurement setup sketched in Fig. 93(b). The bias voltage Vbias was applied via a resistor R = 10 MΩ to the drain of the transistor with the source defining the ground. The input voltages Vgl and Vgr were applied to the left and right side-gate while the output voltage Vd was detected at the drain.

In order to study the dependence of the gating-efficiency on the applied gate voltage we have performed gate voltage sweeps in push-pull configuration with ∆Vgl =-∆Vgr and Vgl + Vgr = const. The measurement shown in Fig. 94 was performed for Vbias = 0.7 V and different working points defined by Vgl + Vgr (T = 4.2 K). Assuming that the gating-efficiency is independent on the applied gate-voltage it is clear that the output voltage should depend only on the sum of the gate voltages. However, it has been found that for quantum-wire transistors Vd depends sensitively on ∆Vgate which is demonstrated in Fig. 94(a). This characteristic variation clearly reflects the voltage dependent gating-efficiency which increases for decreasing gate voltage.

-2 -1 0 1 20.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-2 -1 0 1 20.0

0.1

0.2

0.3

0.4

0.5

0.6

0.70.85 V

0.95 V

1.05 V

1.15 V

1.25 V

Vd (

V)

∆Vgate (V)

1.35 V

(Vgl +Vgr) = (b)

Vwp= 1.7 V

Vd (V

)

∆Vgate (V)

Vwp= -0.1 V ∆Vwp= 0.2 V(a)

Fig. 94: Demonstration of the voltage dependent gating-efficiency in push-pull-mode. (a) Experimental output characteristic for several working points. (b) Calculated output characteristic for voltages Vwp ranging from -0.1 V to 1.7 V.


In order to analyze theoretically the observed voltage dependent gating asymmetry we take into account an approach used for the description of switching properties of electron waveguides. In addition we introduce and distinguish between the gate efficiencies ηl und ηr. Then the conductance Gwire of the quantum wire can be described by

( ) ( ) [ ][ ]sthgrrthgllwire VVVVVGG /tanh121

0 −+−+= ηη , (Eq.1)

with 0G the maximal conductance of the wire, the threshold voltage Vth and the switching voltage Vs. For an ideal quantum-wire transistor with specular symmetry the gating efficiencies ηl und ηr are equal. In order to describe the experimentally observed asymmetric gating properties, which are reflected in the increase of Vd with increasing ∆Vg, we assume that the gating efficiency is larger when the quantum wire is operated close to the threshold voltage Vth. We therefore relate the gating efficiency to the gate voltage in the following way:

( )./ lim,*,, VV rglrlrl −=ηη (Eq.2)

Here Vlim is a fitting parameter with Vlim < Vth and determines the slope of the Vd(Vgl,r)-trace above threshold. According to Eq. 2 the gating efficiency increases with decreasing Vgl,r – Vlim. The output voltage Vd is finally given by

( )wirebiasd GRVV += 1/ . (Eq.3)

Using Eqs. 1-3 the output characteristic of the quantum-wire transistor in push-pull-mode can be modeled. Fig. 94 (b) shows the calculated Vd(∆Vgate)-traces which are qualitatively in very good agreement with the experimental data presented in Fig. 2(a). For ∆Vgate = 0 a minimum can be observed for all traces with a value which decreases for increasing Vwp. Furthermore, the traces are symmetric with respect to ∆Vgate= 0 and Vd increases due to the voltage dependent gating efficiency with increasing voltage difference |∆Vgate| > 0. We relate this gating asymmetry to the mesoscopic capacitance of the quantum wire transistors, which plays a dominant role in small structures. We have utilized this gating anisotropy to realize nanoelectronic gates.

In particular, the intrinsic gating asymmetry of the side-gates can be exploited to realize a compact logic NAND-gate with a single quantum-wire transistor.

0.0

0.7

0.0

0.7(b)

T = 4.2 K

Vd (V

)

T = 300 K

(a)

logic input level (X Y)(LL)(HL)(HH) (LH)

Vd (V

)

Fig. 95: Demonstration of the logic NAND-functionality of the quantum-wire transistor for T = 300 K and T = 4.2 K.


The proposed NAND-functionality of the quantum-wire transistor is demonstrated in Fig.

95, where the output characteristic is presented for 4 configurations of input signals. For each trace one gate voltage was kept fixed at 0 (L) or 0.7 V (H) while the second gate voltage was varied from 0 to 0.7 V. The differential gain larger than unity allows one to cascade the NAND-gate to complex circuits.

Measured and calculated dependences of the output voltage VD are plotted for Vth = 0.675 V and Vth = 0.760 V in Fig. 96 for Vy (Vx) = 0.7 V and 0V. Hereby the theoretical data was calculated using the aforementioned model with the following parameters: RG0 = 100,

1** 3.3// −== VVV slsr ηη , Vwp= 1.9 V, Vlim =-0.3 V and Vbias = 0.7 V. While the curve corresponding to Vth = 0.675 V describes approximately the center of gravity of the experimental Vd (Vx,y)-traces, the curve corresponding to Vth = 0.760 V shows the optimal characteristic for a given set of parameters as Vd (Vx=0.7 V, Vy =0.35 V) = Vbias/2, which is an ideal result with respect to signal restoration.

Apart from the transient output characteristic the output signal of the quantum-wire based NAND-gate was investigated as a function of all combinations of the binary input signals for temperatures up to 300 K. Fig. 95 shows the corresponding output signals for T = 4.2 K and T = 300 K. Hereby the logic input levels were defined by Vx,y = 0 L≡ and Vx,y = 0.7 V H≡ for T = 4.2 K and Vx,y = -0.2 V L≡ as well as Vx,y = 0.4 V H≡ for T = 300 K. In agreement with the truth table of the NAND the output signal is low only for both input signals being high. Otherwise L-signal at one of the inputs leads to H-signal at the output.

Fig. 96: Output characteristics of the quantum-wire transistor in push-fix-mode (T = 4.2 K).

We have realized WNANDs and tested their cascade ability. In a first step we have coupled 2 WNANDS to realize the function W2 = (X1 ∧ Y1) ∨ X2 with the enable input X2. The observed output signal W2 is plotted for several combinations of input signals in the right part of Fig. 97.


(a) (b)

0

1

0

1

0

1

0

10

1

VW

1(V)

VW

2(V)

VX2

V)

VX

1V)

t (a .u .)

VY1

(V)

Fig. 97: (a) Setup layout to test the cascadability (of 2 coupled) WNANDs. (b) Outputs W1 and W2 for several possible input signals. X2 operates as enable input (of the AND-gate).

Fig. 98: Circuit diagram representing the core structure of a FULL-ADDER based on a single HALF-ADDER, a TBJ Schmitt-trigger and 4 WNANDs.

0,00,20,40,6

0,0

0,80,0

0,8

0,0

0,8

0,0

0,8

VST,!Z

VST,Z

VST

(V)

VW

2(V

)

VFA

,Z(V

)

VW

1(V

)

VC (V

)

t (a.u.)

0,20,40,60,8

0,0

0,80,0

0,8

0,0

0,8

0,0

0,8

VST,!Z

VST,Z

VST

(V)

VW

2(V)

VFA

,Z(V

)

VW

1(V)

VC (V

)

t (a.u.)

Fig. 99: Demonstration of the sum-output functionality of a FULL-ADDER based on the combination of 4 WNANDs, a nanoelectronic Schmitt-Trigger and an in-plane HALF-ADDER.

ZHA = L ZHA = H


The above described coupling is utilized to realize the sum output of a FULL-ADDER on

the basis of WNANDS, a Schmitt-Trigger and a HALF-ADDER as shown in Fig. 98. We have investigated the FULL ADDER functionality at low temperature (4.2 K). Results

for varying output of the sum bit of the initial HALF-ADDER are shown in Fig. 99. The top trace in the right and left parts of fig. 7 shows the variation of the FULL-ADDER sum output for different combinations of input levels. For the left part of Fig. 99 the HALF-ADDER sum output is chosen to be L, for the right part it is H.

In the truth table combinations with ZHA=L are highlighted in blue and with ZHA=H in green. The experimental results demonstrate that our FULL-ADDER concept is working and the WNANDs allow that the amplitudes of output signals are equal to the input signals. Full adder functioning at 300 K

In this chapter we demonstrate a new design of the full adder based on branched multi-terminal junctions (MTJs) functioning at room temperature. Logic gates based on cascaded MTJs are described, leading to carry and sum bit outputs. Integrated designs are proposed and are found to also demonstrate simultaneous switching with common threshold. The potential of using monolithic MTJs in integrated nanoelectronics operating at room temperature are investigated. The NEAR full adder concept reflects the enhanced functionality of nanoelectronic devices.

The new design of the full adder concept represents an extension of the half adder device present after the first year of NEAR: Integration of several branches by a junction leads to a carry bit function. As the half adder function was based on the integration of just two inputs realized by two branches of a TBJ for the full adder three inputs: A, B and Cin are necessary. Therefore we made following extension to the layout: First, the three inputs of a full adder require a third input. Consequently, we have added a third branch monolithically connected to an output stem serving as full adder carry bit. Second, the inputs are used to apply different voltages to side-gates controlling the branches of the MTJ. This allows a sensitive tuning of the working point of the complex full adder layout to have a common threshold.

Fig. 100 shows a scheme of three MTJs coupled together forming the NEAR full-adder concept: three input signals (A, B, and Cin) along with up to seven bias voltages Vbias,1 to Vbias,7 coupled to series input and parallel output resistances indicated by the rectangular boxes. In our full-adder concept we used only 3 MTJs that include 18 gates. A smart alignment of the MTJs allows to control the 18 gates by 7 interconnects only.

Fig. 100: Full adder concept: Scheme of the inputs A, B, and Cin connected to the outputs Cout and SUM via three side-gate controlled multi terminal junctions (MTJs). The carry bit layout is shown on the left side of the dotted line, while the sum bit layout is shown on the right hand side.


For the carry bit, shown in Fig. 100 (left), three side-gate controlled branches are cascaded

together. The output Cout is realized by the fourth branch (stem) of a MTJ. In this configuration, the output signal Cout tends towards the branch bias voltage provided that the two input voltages associated with the side-gates of a particular branch are both high. In other words, the output signal Cout tends towards the bias voltage provided that at least two of the inputs are high. If all of the inputs are low then the branches will all be non-conductive and the output carry bit will tend to ground.

Fig. 101: Mask layouts fabricated for the full adder including the levels: mesa, contacts and central structure with monolithic interconnects.

We have also demonstrated that output levels of cascaded devices can be used to drive another device. The sum bit as shown in Fig. 100 (right) consists of two cascaded XOR operations. The full adder is composed by three interconnected MTJs. Seven interconnects are used as loads. The input signals are applied to 18 gates in the manner sketched in Fig.30. It is pointed out that beside the high functionality of the layout, one additional advantage is that the Carry function can be controlled independently on the functioning of the SUM and vice versa. This feature is an important degree of freedom as often only one of the functions for computing is needed. In Fig. 102 microscope images of a full adder structure are shown. In the left part one can see the ohmic contacts realized by Au/Ge/Ni. GaAs/AlGaAs interconnects discharge into the central structure. A magnified image is presented in the right part of Fig. 102. One can identify the three MTJs. The left MTJ performs the CARRY function. The middle and the right MTJs are exploited for the SUM.


Fig. 102: Left: Microscope image of the monolithic full-adder layout. Outer bright contrasts represent 28 Au/Ge/Ni contact pads bonded via gold wires to external loads and detection systems. Seven contacts serve as load inputs, 3 as ground, 12 as inputs, 3 as outputs and 3 as voltage probes used for device characterizations only. From the gold contacts GaAs/AlGaAs monolithic interconnects lead to the central structure. Right: Magnified views of the central structure: Three side-gate controlled MTJs are integrated each controlled by 3 pairs of side-gates. The distance between monolithic interconnects (pitch) is 1 µm. The central branching section of the left CARRY MTJ and the middle XOR MTJ are separated by 7 µm.

Fig. 103: Left: Out voltages at the full adder for several distinguishable logic inputs at A, B and Cin. According to a common threshold of 0.3 V the output voltages fulfill the full adder truth presented in the right truth table. Results The function of the full adder was tested at room temperature (300 K): The output voltages of each device were measured while step functions corresponding to logic low and high levels were applied at the inputs. The MTJ device can be configured to provide a CARRY output as well as the SUM output as shown in left part of Fig. 103, red and green circles, respectively. Different load voltages were applied according to the sketch presented in Fig.30 in the order from left to right: 1.33V, 3V, 5.72V, 4.0V, 4.0V, 7.8V, and 1.3V to ensure an equal threshold voltage above (below) which signals are regarded as logic high (low). Logic low levels of -0.9V and high levels


of 4.0V were applied at the gates. As such, by cascading MTJs we have successfully realized our NEAR full-adder. One can see that performing all distinguishable input signals to the full adder the logic outputs fulfill the truth presented in the right part of Fig. 103. Integration capability of TBJ and SSD devices

TBJ noise margins The voltage transfer curve as shown in Fig. 26 indicate that the WNAND logic gate as shown in Fig. 23 shows very good noise margins of NML 0.1 ~ 0.2 V and NMH 0.25 ~0.35 V with VCC and voltage swing at 0.7 V. The ideal value is 0.35 V.

The NMOS type NAND realized with T-type TBJ, has a 10 MΩ resistive load and thereafter low noise margins. Also considerable improvement could be achieved by changing the resistive load into an active load. In the absence of p-type side gated transistors the solution is a depletion load structure. If only enhancement FETs are available, an enhancement load (or SSD diode load!) would have some improvement, too. As a summary, there are no fundamental restrictions to make regenerative gates with acceptable noise margins with both ECL (differential output) –type and NMOS-type TBJ based logic gates. SSD noise margins One can make SSD based logic devices either in DTL style, using SSDs as switch diodes at the input, or in NMOS type by using side gated transistors as switches and SSDs only as loads. On both cases the output is like an enhancement load NMOS, see Fig. 104, with its noise margin problems. For good noise margin (and signal swing) the on-resistance of the diode connected FET should be much larger than the on-resistance of the switch FET. But too large resistance would lead to high output resistance in general. A rule-of-thumb is that the resistance ratio should be 1:3 ~ 1:5.

Fig. 104: NMOS inverter with enhancement NMOS load

We have simulated voltage transfer curves for SSD based inverters with Silvac Atlas® 2D-

simulator. The simulated voltage transfer curve gives an almost non-existent NML, and the gate is also hardly regenerative. NMH is also small; it is 0.3 V with VCC at 4 V and output swing at 2.5 V. The hitherto measured results on SOI-SSDs have given, for both SSD and side gated transistor devices, better performance: much lower leakage currents and better defined threshold voltage than simulations. We have measured both depletion and enhancement type transistors. The devices can operate properly in spite of narrow margins in ideal conditions, that is that the supply and ground lines are enough noise-free.


Fan-in and Fan-out Depending on the types of sources, different definitions of the fan-in and fan-out exist. Here fan-in is related to the loading on previous stages by the gate, and fan-out is related to the driving capacity of the gate. TBJ TBJ type gates have either a TBJ Y- or T-branch as an input. A TBJ is basically a two-input gate, although more inputs are possible, like in the TBJ half adder. The Y- or T-branch is connected in a way the branches x and y are inputs and the stem C is floating, forming the side gate for the output stage. When the inputs are at the same potential, the impedance is very high, >10 GΩ, and the input takes no current. On the other hand, when the branches are on different potentials, a dc current flows through the branches. This current is in the order of 10 nA ~ 1 µA, corresponding a resistance of 1 to 100 MΩ. The input capacitance is very low; the intrinsic capacitance is about 40 ~ 100 aF, and “necessary” parasitics are in values of about 2 ~ 3 times the value of the intrinsic capacitance. Fan-in is thus limited by the input current.

Both TBJ prototype versions have resistor loads at their outputs, in the order of 1 … 10 MΩ that limit the fan-out to very low. Differential pairs are also well known for their high output impedance. The standard solution in ECL logic is to use a common collector (emitter follower) buffer to decrease the output impedance. This of course increases the static current, because a new parallel current path is formed, but it allows high resistance – and low current – in the differential pair. Also the differential Y-branch output stage could be buffered with a common drain (source follower) connected side gated FET. In common source configuration Rout ≈ 1/gm, that yields with gm =10 µS Rout = 100 kΩ, two decades lower than the load resistor.

A considerable reduction of output impedance in NMOS type outputs could be achieved by using an active load, for instance a diode (SSD) as presented in Fig. 104 or a biased transistor. Here also a source follower buffer could be used. However, it would result in additional static current. SSD NMOS type SSD logic is better than DTL type for large scale integration, because NMOS type logics have inputs connected directly to switch FET gates and no static current flows at any switching state. Therefore the circuit has very high fan-in. The fan-in of NMOS logic is better than the fan-in of CMOS with the same line width, because in NMOS inputs are connected to only one transistor gate, whereas in CMOS inputs are connected to two transistor gates.

SSD logic output is of the same NMOS driver type as in the design used with T-branch based logic previously. Here an SSD is the output load, corresponding to an enhancement type FET. As a conclusion, with proper dimensioning one can achieve a relatively good fan-out. Y- and T-branch TBJs have a reasonable fan-in even at worst case (logic [1,0], [0,1]), provided that the output impedance of the previous stages is low enough. NMOS-type SSDs have an excellent fan-in due to very high input impedance and low input capacitance. Fan-out is limited by the output impedance. The load resistance can be decreased to 100 kΩ by either buffering or by active loading.

Cascading blocks The conditions for easy cascading are: regenerative gates, single polarity operation, same output and input swings and levels, i.e. no level shifters are needed, and adequate input and output impedance relations. Cascading TBJ Y-type TBJs with differential output stages fulfill the above conditions. In some cases like the half-adder Schmitt trigger or other level restorers are needed. On the other hand, the half-adder


proposed is in fact an analog circuit doing a half-adder like function, and the device count is so low that extra level restorers are fully acceptable.

The differential structures presented here allow almost rail-to-rail operation, with the cost of speed. The regenerative characteristics are demonstrated in Fig. 105 that displays the signals after the half-adder core structure, after Schmitt-trigger and after a chain of NANDs. The voltage curves in Fig. 105 are measured ones, which show the real static operation of the circuit.

The full-adder as shown in Fig. 28 and also in the left part of Fig. 28 is realized with the analog half-adder, level restoring Schmitt-trigger, one inverter and three NAND gates. The “transistor count” corresponds approximately 20 transistor equivalents (Y-branches as one, differential pairs as two and half adder core as four) compared to the about 28 transistors of the standard CMOS static adder solution. The full adder could also in principle be constructed by cascading two half adders.

Cascading SSD So far we have only simulated larger SSD structures than single NANDs, NORs or ORs. These simulations, however, are performed based on IV-curves measured on real components and SPICE type circuit models developed from these measurements. Therefore the simulations can realistically estimate the performance of real larger circuits. We have simulated two half adder circuit architectures: DTL-type and NMOS-type depicted in Fig. 106. Both circuits are done in a standard logic way by cascading NAND, NOR and inverter gates for the desired logic function. Thus a success in simulations demonstrates also, in principle, the cascading ability of the gates.

Fig. 105: Signal levels and logic operation of the full-adder in Fig. 28. Notice the regenerative character of the structure.

As stated above, one can make SSD gates with some noise margins and transient region voltage amplification larger than one. That is enough for regenerative gates. Simulations show that both the DTL and NMOS types give acceptable performance. However, the output swing


and the speed were better in the NMOS type solution. The simulated output swing of this type with VCC at 4 V is about 3.5 V. The simulations simulate also the dynamic performance. The rise time is about 3 ns and the fall time 1 ns, allowing 200 MHz signal frequency. The rise time is determined by the load diode, the resistance of which must be about 3~5 times of the on-state resistance of the switch transistor, as one can see from the relation of the rise and fall times. The simulation shows that there is no fundamental restrictions in cascading SSD based gates.

Fig. 106: Two different realizations of SSD half adders: (a) DTL-ype and (b) NMOS-type

Delays and speed The delay of the gate consists of three parts: (1) loading input capacitance, (2) turn on/off the switches and (3) loading load capacitance. The intrinsic switching speed, related to ft, is in the realized structures 10 ~ 30 GHz. Thus the limiting factor is the loading, with reasonable static current consumption. Time delay is specified as the time from input 50% level to output 50% level. Here the time delay is approximately the RC-time constant of the structures.

TBJs have a T- or Y-branch at the input. It has resistance that affects the switching time and cause a delay. The worst case is logic [1,0] or [0,1] where a part of the current flows to ground or VCC and a part of current goes to load the input capacitor. Since the branches are not linear resistors, calculation of the exact input loading time is difficult. We can approximate the input as a resistor of 1 ~ 10 MΩ. After the resistance we have practically only the intrinsic input capacitance to consider. If the intrinsic input capacitance is 40 aF, we have an input delay of 40 ~ 400 ps. The switching speed of the side gated transistor is typically faster. At output, high-to-low transient depends on the side gated transistor resistance, which has been in the test structures about 1 MΩ. The load resistance in test structures has been 10 MΩ. Thus the low-to-high transient time, determined by the load resistor, dominates. With an 100 aF load the time constant is 1 ns ~ 10 ns. The total time delay is from 1 to 10.5 ns allowing maximum data rates of 50 to 500 MHz. By buffering the output the output delay drops to about 100 ps and the total delay is now 150 ~ 500 ps allowing 1 ~ 3 GHz maximum data rate with fan-out of one.

SSDs have no problems in input capacitance loading because in NMOS-type logic the resistive part of input impedance is very small and even in the DTL case the on-resistance of the diodes can be made small. The high-to-low transient depends on the switch side gated transistor resistance, which has been in the test structures some hundreds of kilo Ohms. The load diode resistance should be 3 ~ 5 times with a minimum of 1 MΩ for the present transistors. The load diode determines the low-to-high transient time. Thus this parameter is the critical one. With 1 MΩ resistor and 100 aF capacitance the time constant is100 ps allowing a few GHz maximum data rate with fan-out of one.

To speed up the operation one should decrease load resistors and increase switch transistor transconductance to increase both ft and on-state conductance. These of course increase also power consumption.


Power consumption All technologies presented can operate with a single polarity voltage supply. TBJs need also a bias voltage for the Y- or T-branches, but this can be the same as VCC. An optimised performance may however need a separate bias level. Proper operation has been demonstrated with as low VCC as 0.7 V, but most of the prototypes presented have needed operation voltage in the order of 3 ~ 5 V. The main technological (not fundamental) problem with low supply voltage is the poor control of the threshold voltage of side gated transistors. When the processing of these devices becomes more mature, this parameter will most probably also be better controlled.

The differential pair of the Y-branch TBJ based logic takes constant static current independent of switching state, in the order of 100 nA with 10 MΩ load resistors. The current is in this case solely defined with the load resistors. Increasing the resistors would worsen the fan-out. By biasing the pair with a constant current source less than 100 nA would keep the output resistance constant but would reduce the swing. It also makes the circuit more complicated. A source follower buffer would take the same order of current at output high state.

A static current flows through a NMOS logic switch only during output low (switch gate high) state. It is defined by the load resistance again. And again there is a trade-off between current consumption and switching speed.

We can make an order-of-magnitude estimate for 5 GHz operation and 100 ps delay for the average power consumption of two input gates, NAND and NOR gates. The supply voltage is 1 V (not yet achieved with the prototypes of T-branch and SSD gates). The estimated values are: Differential TBJ 3.5 µW, NMOS TBJ 1.5 µW and SSD-NMOS 1.0 µW. Dynamic consumption would be 0.5 µW. As a comparison, CMOS would have only dynamic consumption and bipolar ECL (that hardly operates with VCC 1V) with 100 ps delay would have >100 µW static power consumption. The dynamic consumption of CMOS is doubled compared to NMOS with same transistor size, because in CMOS one has to load two transistors and in NMOS only one. With TBJs there is also the Y- or T-branch bias gate capacitance in addition to the switch gate capacitance. One must notice that these figures are only for a very low fan-out of 1 ~ 2 gates.

Power consumption is reasonable compared with CMOS. The calculations are based on the assumption that all logic states have equal probability. Only some logic states consume static power at input, output or both. By designing the logic so that these states are less probable than the others, power consumption can still be reduced. Interconnects and substrate effects All the structures are manufactures either on insulating or semi-insulating substrata or on thick 400 nm ~ 3µm oxide. Therefore substrate coupling and crosstalk effects, which are a problem in fast CMOS, should be absent. Also the interconnect-substrate parasitic capacitance is small. Thus the technologies presented here are more SOI-CMOS than bulk CMOS like by their substrate effects.

Most of the basic gates presented here can be made on semiconductor only without metallization cross-over or intermediate connects. The differential Schmitt trigger stages need one cross-over, but on the other hand the half-adder core can be made totally without cross-over. No body or substrate contacts like in CMOS are needed, but on the other hand in TBJs the Y- or T-branch side gates must be biased and contacted. A side gated transistor can work with a gate on one side only, but a greater transconductance can be achieved if the transistor is gated double sided. This demands usually one cross-over.

Integration possibilities with standard electronics The biggest problem in the devices hithero produced is their low driving capability. In standard IC electronics the driving capability can be increased by increasing certain dimensions, like channel width W in CMOS. This is not possible with the devices produced in this project. The only way to increase the drive capability is putting devices in parallel, that takes area and increases


the interconnect complexity. Therefore a practical industrial process would be a hybrid one in the BiCMOS style, in which standard electronics devices, CMOS in Si and MESFET in III-V compounds, would do the driving tasks and nano devices the fast low power small area operations.

This approach needs the possibility of monolithic integration of nano devices developed in this project with standard electronics devices. In BiCMOS there is usually a CMOS platform in which the bipolar part is added as a plug-in process module. In our case propably the nano device substrate should be the platform on which the SOI-CMOS or MESFET etc. module is added. There are no fundamental obstacles in this approach. The processes should in principle be compatible.

The main problem is the electronic compability. Modern CMOS operates with 1.6 V (Lmin >100 nm) or 0.9 V (Lmin <100 nm) supply voltage and 0.5…0.7 V threhold voltage. The Si SSDs and SGTs hithero manufactured have had minimum 2 V threshold voltage. However there are no physical limitations to lover Vth and supply voltage. The problem is only a technical one: to get the threshold adjustment into a better control in this new type of devices. The WNAND structures have already demonstrated as low as 0.7 V threshold. With these the compability doesn’t need so much process control development as with the Si devices.

Another problem has been the loading of the circuits. Most of the test structures have used external resistive loads in the order of 10 MΩ. In practical circuits this is not possible because of speed and area reasons. However, we have already demonstrated the use of active loads: SSDs as in Figs 6. And 8. So also this problem is solvable. Thus in principle there are no fundamental limitations in integrating SSD, SGT and TBJ based circuit blocks with standard (SOI) CMOS or III-V (GaAs etc.) electronics.

Conclusions All the technologies studied have proven capability to static digital logic operation. All the devices can be operated with a single one polarity power supply. All the technologies use static power at least in some logic states. A relatively fast operation up to a few GHz can be achieved with a reasonable power consumption. Regenerative gates with positive noise margins can be made with all technologies presented, thus allowing easy cascading of the stages.

The devices presented can be integrated easily with high area efficiency. All basic gates can be made with a single connection (metallization) layer, and many of them with just internal (semiconductor) intra-cell connections. In principle two metallization layers are sufficient for any circuit with these technologies.

As a final conclusion, there are no fundamental restrictions for making at least medium size logic with these technologies. In very large designs the static power consumption will be the limiting factor and the way of solving this problem needs to be developed. Proposal for complex circuit design of demonstrator

In this sections we investigate the possibility to realize a complex circuit design of a possible demonstrator, utilizing the logic elements manufactured and demonstrated during the project.

A typical digital processor is built up basically from the following main blocks: the data path, the control module, the memory module, the interconnection (data bus) and the input-output circuitry. The data path is the core of the processor. A typical data path consists of an interconnection of basic combinational functions, such as logic or arithmetic operators (addition, multiplication, comparison, and shift). The control module determines the actions in the processor at any time. It consists of registers and logic units, and hence is a sequential circuit. The memory module serves as centralized data storage. The interconnect and input-output circuitry – the interconnect network (data bus) connects the different processor modules to one another as well as to the peripheral devices.


The Multiplier A multiplier is proposed as a complex circuit design demonstrator. It is a central functional component of the data path that in turn is the core module of a processor. It consists only of blocks we have already demonstrated: full and half adders and AND gates. It is certainly more complex than an adder, having adders as sub-blocks. It can be made arbitrary large depending on the bit size of the numbers to be multiplied.

A N × M multiplier in its basic form needs N × M two-input AND gates, (N - 1 × M - 1) -1 full adders and N + 1 half adders. Minimum two metal layers are needed for global X and Y wirings.

Fig. 107: A 4 × 4 bit array-multiplier for unsigned numbers-composition. FA stands for a full adder and HA stands for a half adder. The hardware for the generation and addition of one partial product is shaded in gray. 4x4 Multiplier area comparison In this section we compare the estimated area of a NEAR nanotechnology multiplier to a multipier realized with conventional state-of-the art CMOS technology. The nanotechnology circuit taken into comparison is a full adder based on branched multi-terminal junctions (MJTs), Fig. 32. The CMOS technology we have used in the comparison is a state-of-the-art 90 nm digital process.

The area estimate of the CMOS realisation is based on the minimum size standard library cells of the process. So the multiplier is not the fastest one possible with that process, but the fan-out of the cells is high enough to make a functionin block with reasonable speed. The area estimate of the MJT based multiplier is based on the full adder design in Fig 32, with the following additional assumptions:

The interconnect and supply line pitches are the same as in the 90 nm CMOS process and the circuit size is interconnect limited and not by the device size.

With the assumptions mentioned this structure can be packed into an area of 4.8 µm x 2.9 µm, approximately 14 µm2. A half adder is estimated to be a half of this area, 7 µm2, and a two-input OR or AND 2 µm2. An CMOS Full Adder (FA) can be realized for instance with two Half Adder (HA) and one OR-gate, Figure 5. A Half Adder can be realized with one XOR and one AND gate. The gate cell sizes are given for the 90 nm CMOS process in Table 2.


Gate Area (µm2)

AND2 3.75

XOR2 12

OR2 4.25

Table 2. Gate areas in the 90 nm CMOS procsess

Now we can calculate estimates for the 4x4 Multiplier in both technologies, Table 3:

Area (µm2) Block Gates

90 nmCMOS Nano MJT

HA AND2 + XOR2 15.75 7 FA 2 * HA + OR 35.75 14

4*4 Multiplier 8 * FA + 4 * HA + 16 * AND2 409 172

Table 3. The areas of the adders and the multiplier

We can see that the MJT realization takes much less area than the CMOS realization with

the same interconnect pitch. This is mainly due to the very compact size of the MJT XOR gate compared to the standard CMOS solution. One must notice that this comparison is very heavily technology and process dependent, therefore no general conclusions can be drawn.


7. Deliverables

The following table lists the deliverables of the NEAR project, with comments and notes on compliance given in the last column. Delive-rable

No

Deliverable title Type Classification

Due date Compliance/

Delivery date

1 Fabrication of single logic element by e-beam lithography

D Pub M6 Yes/M6

2 Functioning single logic elements at 300 K D Pub M12 Yes/M12

3 Report on the understanding of the basic physical phenomena

R Pub M12 Yes/M12

4 e-beam writing at 30 MHz demonstrated R Pub M18 Yes/M18

5 Functioning discrete amplifying elements at 300 K

D Pub M18 Yes/M18

6 Model extracted from devices in deliverable No. 2

R Pub M18 Yes/M12

7 Report on the possibilities with design of logic building blocks and analogue circuits

R Int M18 Yes/M18

8 Functioning single logic element made by imprint

D Pub M24 Yes/M18

9 Report on the possibilities with design of complex circuits

R Int M24 Yes/M24

10 Single logic element in Si at 300 K with linewidths 50-100 nm

D Int M30 Yes/M30

11 Proposal for complex circuit design of demonstrator, based on deliverable No 6

R Int M30 Yes/M32

(updated M36)

12 Full adder functioning at 300 K D Int M36 Yes/M36

Note 1: Types of deliverables include device demonstration (D) and result report (R). Note 2: Public classification (Pub) indicates the results were reported in international

conferences, scientific journals, etc; internal classification (Int) means that the results were made available within the NEAR partners.

Note 3: While most deliverables were made available on time or earlier than planned date, deliverable 11 was made available behind the schedule. This is because many new measured data were generated in the last year of NEAR, with which the deliverable 11 needed to be constantly updated.


8. Publications and conferences

8.1 Refereed journal papers

1. I. Shorubalko, H. Q. Xu, I. Maximov, D. Nilsson, P. Omling, L. Samuelson , W. Seifert, "A novel Frequency-Multiplication Device Based on Three-Terminal Ballistic Junction", IEEE Electron Device Letters, 23, 377 (2002)

2. I. Maximov, P. Carlberg, D. Wallin, I. Shorubalko, W. Seifert, H. Q. Xu, L. Montelius and L. Samuelson, "Nanoimprint lithography for fabrication of three-terminal ballistic junctions in InP/GaInAs", Nanotechnology, 13, 666 (2002)

3. H. Q. Xu, “Diode and transistor behaviors of three-terminal ballistic junctions”, Appl. Phys. Lett., 80, 853 (2002)

4. D. Csontos and H. Q. Xu, “Scattering-matrix formalism of electron transport through three-terminal quantum structures: formulation and application to Y-junction devices”, J. Phys.: Condens. Matter, 14, 12513 (2002)

5. H. Q. Xu, “A novel electrical property of three-terminal ballistic junctions and its applications in nanoelectronics”, Physica E 13, 942 (2002)

6. I. Shorubalko, H.Q. Xu, P. Omling, and L. Samuelson, “Tunable nonlinear current-voltage characteristics of three-terminal ballistic nanojunctions”, Appl. Phys. Lett. 83, 2369 (2003)

7. A. Löfgren, I. Shorubalko, P. Omling, and A. M. Song, “Quantum behavior in nanoscale ballistic rectifiers and artificial materials”, Phys. Rev. B67, 195309 (2003)

8. D. Csontos and H.Q. Xu, “Quantum effects in the transport properties of nanoelectronic three-terminal Y-junction devices”, Phys. Rev. B67, 235322 (2003)

9. I. Maximov, P. Carlberg, I. Shorubalko, D. Wallin, E-L. Sarwe, M. Beck, M. Graczyk, W. Seifert, H. Q. Xu, L. Montelius and L. Samuelson, “Nanoimprint technology for fabrication of three-terminal ballistic junction devices in GaInAs/InP”, Microelectronic Engineering, 67-68, 196 (2003)

10. D. Wallin and H. Q. Xu, “Electrical properties and logic function of multi-branch junction structures”, submitted to Appl. Phys. Lett. (2004)

11. H. Q. Xu, I. Shorubalko, D. Wallin, I. Maximov, P. Omling, L. Samuelson, and W. Seifert, “Novel Nanoelectronic Triodes and Logic Devices with Three-terminal Ballistic Junctions”, IEEE Electron Devices Letters 25, 164 (2004)

12. S. Reitzenstein, L. Worschech, P. Hartmann, M. Kamp, A. Forchel, “Capacitive-Coupling-Enhanced Switching Gain in an Electron Y-Branch Switch”, Phys. Rev. Lett. 89, 226804 (2002)

13. S. Reitzenstein, L. Worschech, P. Hartmann, A. Forchel, “Logic AND/NAND gates based on three terminal ballistic junctions”, Electron. Lett. 38, 951 (2002)


14. S. Reitzenstein, L. Worschech, D. Hartmann, and A. Forchel,” Pronounced switching bistability in a feedback coupled nanoelectronic Y-branch switch”, Appl. Phys. Lett., 82, 1980 (2003)

15. L. Worschech, S. Reitzenstein, P. Hartmann, S. Kaiser, M. Kamp, and A. Forchel, “Self-switching of branched multiterminal junctions: a ballistic half-adder”, Appl. Phys. Lett., 83, 2462 (2003)

16. S. Reitzenstein, L. Worschech, and A. Forchel, “A Novel Half-Adder Circuit Based on Nanometric Ballistic Y-Branched Junctions”, IEEE Electon Device Letters 24, 625 (2003)

17. S. Reitzenstein, L. Worschech, D. Hartmann, and A. Forchel, “Drain-voltage induced barrier increasing of quantum-wire transistors”, Electronics Lett. 40, 75 (2004)

18. S. Reitzenstein, L. Worschech, and A. Forchel, “Room-temperature operation of an inplane half-adder based on ballistic Y-junctions”, IEEE Electron Device Lett. 25, 462 (2004)

19. S. Reitzenstein, L. Worschech, C. Müller, and A. Forchel, “Compact logic NAND-gate based on a single in-plane quantum-wire-transistor“, accepted IEEE Electron Device Lett. (2004)

20. D. Hartmann, S. Reitzenstein, L. Worschech, A. Forchel, “Static memory elements based on a single electron Y-branch switch”, submitted to IEEE Electron Device Lett. (2004)

21. L. Worschech, D. Hartmann, and S. Reitzenstein, A. Forchel, “Non-Linear Properties of Ballistic Nanoelectronic Devices”, invited review to be submitted February 2005 – not available at report preparation date

22. Markku Åberg, Jan Saijets, Aimin Song, and Mika Prunnila, “Simulation and modeling of self-switching devices”, Physica scripta T114, 123 - 126 (2004)

23. A. M. Song, M. Missous, P. Omling, A. R. Peaker, L. Samuelson, and W. Seifert, “Unidirectional electron flow in a nanometer-scale semiconductor channel: A self-switching device”, Appl. Phys. Lett., 83, 1881 (2003)

24. A. M. Song, P. Omling, I. Maximov, M. Missous, L. Samuelson, and W. Seifert, “Nanometer-scale, two-terminal, semiconductor memory operating at room temperature”, Appl. Phys. Lett., accepted for publication (January 2005)

25. A. M. Song, I. Maximov, M. Missous, and W. Seifert, “Diode-like Characteristics of Nanometer-Scale Semiconductor Channels with A Broken Symmetry”, Physica E, 21, 1116 (2004)

8.2 Conference presentations

1. I. Maximov, P. Carlberg, I. Shorubalko, D. Wallin, E-L. Sarwe, M. Graczyk, W. Seifert, H. Q. Xu, L. Montelius and L. Samuelson, "Nanoimprint lithography for fabrication of three-terminal ballistic junction devices in GaInAs/InP", Micro- and Nanoengineering 2002 (MNE 2002), September 2002, Lugano, Switzerland, p. 392


2. H. Q. Xu, I. Shorubalko, I. Maximov, W. Seifert, P. Omling, L. Samuelson, "Three-terminal Ballistic Junctions: New Building Blocks for Functional Devices in Nanoelectronics", 26-th International Conference on the Physics of Semiconductors, 29 July-2 August, 2002, Edinburgh, Scotland, UK, part II, p. 270

3. I. Shorubalko, P. Omling, L. Samuelson and H. Q. Xu, “Current-voltage charcteristics of three-terminal ballistic junctions”, 26-th International Conference on the Physics of Semiconductors, 29 July-2 August, 2002, Edinburgh, Scotland, UK, part III, p. 332

4. S. Reitzenstein, L. Worschech, P. Hartmann, A. Forchel, “Voltage gain and switching effects in GaAs/AlGaAs Y-branches”, 26-th International Conference on the Physics of Semiconductors, 29 July-2 August, 2002, Edinburgh, Scotland, UK, part II, p. 185

5. I. Shorubalko, H. Q. Xu, I. Maximov, D. Nilsson, P. Omling, l. Samuelson, W. Seifert, "A novel frequency-doubling device based on three-terminal ballistic junction", Device Research Conference, Univ. California, Santa Barbara, June 24-26, 2002, USA, p. 159

6. S. Reitzenstein, L. Worschech, P. Hartmann, A. Forchel, “Observation of a self-gating effect in GaAs/AlGaAs Y-branch switches”, Presentation on the 12th NID Workshop, Helsinki, 1 - 3 Juli 2002

7. I. Maximov, P. Carlberg, I. Shorubalko, E.-L. Sarwe, W. Seifert, A. Song, H. Q. Xu, L. Montelius and L. Samuelson, "Nanoimprint lithography for fabrication of electron waveguide structures in InP/GaInAs", Workshop on compound semiconductor devices and integrated circuits (WOCSDICE-02), Moscow, Russia, May 2002, p. 79

8. S. Reitzenstein, L. Worschech, P. Hartmann, S. Kaiser, A. Forchel, “Logic gates and voltage amplification by nanoelectronic GaAs/AlGaAs junctions”, Presentation on the 9th NID Workshop, Catania, 6 - 8 February 2002

9. P. Carlberg, I. Maximov, D. Wallin, H. Q. Xu, W. Seifert, L. Montelius, L. Samuelson, “Nanoelectronic Circuits in GaInAs/InP Fabricated by Nanoimprint Lithography”, Micro- and Nanoengineering 2003 (MNE03), 22-25 September, Cambridge, UK, p. 54

10. P. Carlberg, D. Wallin, I. Maximov, H. Q. Xu, W. Seifert, L. Montelius, L. Samuelson, “Fabrication of Electron Waveguide devices in GaInAs/InP 2DEG Using Nanoimprint Lithography”, Proceedings of the International Conference “Trends in Nanotechnology” (TNT2003), Salamanca, Spain, Sept. 15-19, 2003, p. 415

11. C. Balocco, M. Missous, and A. M. Song, “Fully Electrically Controlled, Room-Temperature Memory Devices Based on Self-Assembled InAs Quantum Dots”, Proceedings of the International Conference “Trends in Nanotechnology” (TNT2003), Salamanca, Spain, Sept. 15-19, 2003

12. S. Reitzenstein, L. Worschech, D. Hartmann, and A. Forchel, “Intrinsic switching bistability in electron Y-branch switches”, Proceedings of the International Conference “Trends in Nanotechnology” (TNT2003), Salamanca, Spain, Sept. 15-19, 2003

13. I. Maximov, P. Carlberg, D. Wallin, I. Shorubalko, H. Q. Xu, W. Seifert, L. Montelius and L. Samuelson, “Nanoimprinted GaInAs/InP Circuits Based on Three-Terminal Ballistic Junction Devices, The 27-th Workshop on Compound Semiconductor Devices and Integrated Circuits held in Europe (WOCSDICE 2003), May 26-28, 2003, Fürigen, Switzerland, p. 107


14. A. M. Song, I. Maximov, M. Missous, P. Omling, A. R. Peaker, L. Samuelson, W. Seifert, “Nanometer scale diode and circuit made by one-step fabrication”, 11-th International Symposium, Nanostructures: Physics and Technology, SPB, Russia, 2003, p. 229

15. S. Reitzenstein, L. Worschech, P. Hartmann, S. Kaiser, and A. Forchel, “Nanoelectronic half adder based on branched ballistic junctions”, presented at 11th MEL-ARI/NID Workshop, February 5-7, Toulouse (2003)

16. Markku Åberg, Jan Saijets, and Aimin Song, “Simulation and Modeling of Self-switching Devices”, Nordic Semiconductor Meeting, Tampere, Finland 25-27.8.2003. Poster and abstract.

17. I. Maximov, P. Carlberg, D. Wallin, I. Shorubalko,W. Seifert, H. Q. Xu, L. Montelius and L. Samuelson, “Direct Printing of GaInAs/InP Logic Circuitry Based on Three-Terminal Ballistic Junctions”, 11-th International Symposium, Nanostructures: Physics and Technology, SPB, Russia, 2003, p. 285

18. L. Worschech, S. Reitzenstein, D. Hartmann, and A. Forchel, “Giant switching efficiency in an electron Y-Branch Switch”, presented at EP2DS Nara, Japan (2003)

19. A. M. Song, I. Maximov, M. Missous, W. Seifert, “Diode-like characteristics of a nanometer-scale semiconductor channel with broken symmetry”, The 11th International Conference on Modulated Semiconductor Structures (MSS), Nara, Japan, 2003

20. L. Worschech, S. Reitzenstein, D. Hartmann, A. Forchel, “Self-switching and giant capacitance in electron Y-branch switches”, invited talk presented at New Phenomena in Mesoscopic Structures 6 conference, Maui (2003)

21. S. Reitzenstein, L. Worschech, A.Forchel, ”Room temperature operation of an in-plane half adder based on ballistic Y-junctions”, The 11th International Conference on Modulated Semiconductor Structures (MSS), Nara, Japan, 2003

22. S. Reizenstein, L. Worschech, P. Hartmann, M. Kamp, A. Forchel, “Voltage gain in nanoelectronic GaAs/AlGaAs Y-branch switches”, presented at APS-MM: 2003 March Meeting, March 3-7, 2003, Austin, Texas (2003)

23. H.Q. Xu, I. Shorubalko, I. Maximov, W. Seifert, P. Omling and L. Samuelson, “Novel nanoelectronic devices based on three-terminal ballistic junctions”, the 4th Intl Symposium on Nanostructures and Mesoscopic Systems (NanoMES 2003, 17-21 February 2003, Tempe, Arizona, USA); Abstract in the Book of Abstracts of the Symposium, p. FA6

24. H.Q. Xu, D. Wallin, I. Shorubalko, I. Maximov, W. Seifert, P. Omling and L. Samuelson, “Effect of phonon scattering on the novel electric properties of three-terminal ballistic junction”, the 13th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors (HCIS-13, 28 July-1 August 2003, Modena, Italy)

25. Hongqi Xu, Ivan Shorubalko, Daniel Wallin, Ivan Maximov, Patrick Carlberg, Werner Seifert, Pär Omling, and Lars Samuelson, “Three-terminal Ballistic Junctions as Building Blocks for Room-temperature Functional Devices in Nanoelectronics”, invited talk presented at the 6th Japan-Sweden Joint QNANO workshop (Stockholm, December 15-16, 2003)


26. S. Reitzenstein, L. Worschech, A. Forchel, “Room temperature functional nanoelectronic logic circuits”, presented at 5th IWFIPT (International Workshop on Future Information Processing Technologies), November 10-13, 2003, Miyazaki, Japan (2003)

27. D. Csontos and H. Q. Xu, “Current rectification in three-terminal ballistic nanojunctions”, Annual APS March Meeting 2004, March 22-26, 2004, Montreal, Canada

28. I. Shorubalko, D. Wallin, P. Omling, L. Samuelson, and H. Q. Xu, “Ballistic behavior of electrons on several-micrometers scale at room temperature”, the 27th International Conference on Physics of Semiconductors, July 26-30, 2004, Flagstaff, Arizona, USA

29. I. Shorubalko, D. Wallin, P. Omling, L. Samuelson, and H. Q. Xu, “Nolinear electrical properties of large-size three-terminal junctions”, the 27th International Conference on Physics of Semiconductors, July 26-30, 2004, Flagstaff, Arizona, USA

30. I. Maximov, P. Carlberg, D. Wallin, A. M. Song, H. Q. Xu, L. Montelius, W. Seifert and L. Samuelson, “Nanoimprint Lithography as a Tool for Fabrication of Novel Devices and Circuits in GaInAs/InP”, 12-th International Symposium, Nanostructures: Physics and Technology, SPB, Russia, 2004, p. 197

31. H.Q. Xu, D. Wallin, I. Shorubalko, I. Maximov, P. Omling, and L. Samuelson, “Room-temperature Nanoelectronic Logic Devices with Ballistic Junctions”, the 8th Int. Conference on Nanometer Scale Science and Technology, June 28-July 2, 2004, Venice, Italy

32. H.Q. Xu, “Novel Electronic and Optoelectronic Devices with Nanometer-Scale Semiconductor Structures”, invited talk presented at the 2004 Scanning Probe Microscopy, sensors and nanostructures, May 23-27, 2004, Beijing - TEDA, China

33. I. Maximov, A. M. Song, D. Wallin, P. Carlberg, V. S. V. Prabhakar, W. Seifert and L. Samuelson, “Self-Switching Devices in GaInAs/InP Made by Nanoimprint Technique”, Micro- and Nanoengineering 2004 (MNE), 19-22 September, 2004, Rotterdam, The Netherlands, p. 370

34. L. Worschech, S. Reitzenstein, D. Hartmann, and A. Forchel, “Ballistic nanodevices in the non-linear regime“, invited lecture, SISPAD workshop 2004, http://www.tep.ei.tum.de/sispad04/

35. L. Worschech, S. Reitzenstein, and A. Forchel, “Ballistic switching devices in the non-linear transport regime“, invited talk, presented at the Quantum Transport Nano-Hana International Workshop 2004, Chiba, Japan, accepted for publication in IPAP conference Series

36. L. Worschech, S. Reitzenstein, D. Hartmann, and A. Forchel, “Current gain and switching bistability in nanoscale Y-branch switches”, invited talk presented at the Nanostructure Symposium in St. Petersburg 2004, accepted for conference proceedings

37. Markku Åberg, Jan Saijets, Eeva Pursula, Mika Prunnila, and Jouni Ahopelto, “Silicon self-switching-device based logic gates operating at room temperature”, Proceedings of the 22nd Norchip Conference, Oslo, 8 - 9 November 2004, TechnoData A/S. Copenhagen 40 - 43 (2004)

38. Aimin M. Song, “110 GHz Operations of Novel Nanodevices”, 2005’Guangzhou International Conference on Nanotechnology and Nano-Biotechnology (Invited talk), Guangzhou, China, Jan. 16-18, 2005


39. Aimin M. Song, “Novel room-temperature nanoelectronic devices”, Institute of Physics (IOP) Workshop on Nanoelectronics, (Invited talk), Warrington, Cheshire, UK, 11-12 January, 2005

40. J. Mateos, B. G. Vasallo, D. Pardo, T. González, and A. M. Song, “Operation of a novel nanoscale unipolar rectifying diode”, 16th International Conference on Indium Phosphide and Related Materials, Kagoshima, Japan, 31 May - 4 June, 2004

8.3 Book chapters

1. A. M. Song, “Room-Temperature Ballistic Nano-Devices”, (Invited book chapter), Encyclopedia of Nanoscience and Nanotechnology, Volume 9, Pages 371-389, American Scientific Publishers, 2004

8.4 Technical reports

1. D. Csontos and H. Q. Xu, “Quantum effects in the transport properties of nanoelectronic, three-terminal Y-junction devices” (2002)

2. I. Maximov, P. Carlberg, D. Wallin, H. Q. Xu, W. Seifert and L. Montelius, “Fabrication of Electron Waveguide-Based Devices using Nanoimprint Lithography”, manuscript (2003)

3. E. Pursula, “Lateral field effect devices for room temperature silicon nanoelectronics”, Master's thesis


9. Future outlook

In the three years of NEAR, the concepts of TBJs and SSDs have been much further advanced, and room-temperature functioning, integrated TBJ/SSD devices and circuits, including latch, half-adders and full adders, etc have been developed and realized. All these devices have a common feature of monolithic architecture, and therefore they require only one-step lithographic processes to be fabricated. Most devices have been demonstrated on III-V semiconductor heterostructures, while some demonstrations of simple SSD and TBJ devices have also been successfully carried out on silicon-on-insulator substrates. These works on silicon materials are of great importance, since they imply the possibilities of transferring our III-V device technology to silicon technology. We expect that the device and circuit developments made in NEAR may have an impact on the future nanoelectronics. It will be highly valuable to further improve the performance of silicon-based TBJ and SSD devices and to realize TBJ and SSD related integrated circuits on silicon materials. It will also be of great interest to demonstrate the TBJ concept in self-assembled nanostructures, such as branched carbon nanotube junctions and branched semiconductor nanowire junctions. Indeed, partners from NEAR are intending to cooperate in this direction in a proposed Integrated Project within IST-FET Nanoelectronics.

Great technology advances including, e.g. the development of fast e-beam system with writing speed of 40 MHz and development of nanoimprint technology for fabrication of TBJ and SSD integrated devices and circuits, have been achieved in the three years of NEAR. The presented progress in fabrication technologies has the potential to drastically reduce fabrication cost of future nanoelectronic devices and circuits.

Having these goals of the NEAR project at hand, at the present stage it is essential to demonstrate an integration of TBJ and SSD related devices with common HEMT or CMOS technology. If this can be achieved, then HEMT and/or CMOS can be used as buffer to connect the TBJ and/or SSD based nanoelectronic devices to main-stream electronics, and TBJ and SSD based devices can help us to enhance the functionalities and integration density of today’s electronic circuits. In another planned action, partners from NEAR are considering to form a focused effort in an EU-project where ballistic devices are to be integrated with HEMT and/or CMOS technologies.

For future efforts of this or similar kinds, we may have given some inspiration from the mode of operations within NEAR, in terms of very open forms of interactions and sharing of research progress, in mobility of young researchers among our research laboratories, in successful joint research efforts and in a highly inspirational internal competition among the partners. It was fun.

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