netfpga l2 switch
DESCRIPTION
NetFPGA L2 Switch. Sheng-Liang Song [email protected] EE384Y, Spring 2003. Overview of the NetFPGA Board. SRAM. SRAM. L2Sw4 User FPGA #1. Control FPGA. Ethernet Controller. Port 0. Port 1. Port 2. Port 3. User FPGA #2. Port 4. Port 5. Port 6. SRAM. Port 7. - PowerPoint PPT PresentationTRANSCRIPT
SRAM
L2Sw4UserFPGA #1
ControlFPGA
Eth
ern
et
Co
ntro
ller
SRAM
UserFPGA #2
SRAM
Overview of the NetFPGA Board
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
MemDiagCtrl
4-Port Layer 2 SwitchControl
TX data TX data
LEDs[3 : 0] Button InputLEDs[3 : 0]LEDs[3 : 0]
To/From SRAM
To/From CFPGA
Overview of the UFPGA (L2 Switch)
MemCtrl RX dataRX data
CFPGAInterface
Request
Grant
do_mem_diag
mem_diag_done
do_mem_diag
S4-CM FSM Diagram
mem_diag do_ctrl
idletry_read
nxt_rd_port
wait
try_write
wait_tx_done
do_mem_diag & ~mem_diag_done
1.myCtrlFifoNotEmpty
2.RxEn && |(QRxVector & rxFifoNotEmpty)
3.TxEn
~rx_done
rx_done
mem_diag_done
TxEn
~TxEn
~Qempty &(|QtxVector & txFifoNotFull)
“else”
“1”
“else”
tx_done
~tx_donectrl_done
rx_done
~mem_diag_done
Reset
S4-MEM Diag FSM Diagram
idle
fillcompare
Addr >= Max_addr
Addr >= Max_addr
Addr<Max_addr
Addr < Max_addr
do_mem_diag & ~mem_diag_done
Resetelse
Addr:[17:0]
31: done
20: fail
Data2:[31:0] = Mem[31:0]
Data1:[19:16] = Mem[35:32] Pattern[7:0]
Addr: 0x05
Data1: 0x06
Data2: 0x07
Registers
Ctrl: 0x02Ctrl
10: MemDiag
DeviceID[0xE384] Version[7:0] Ver: 0x01UFPGA_ID[1]
[20:18] Phase
Diag_phase[2:0] Data_Content
000 Pattern, PatternComp
001 PatternComp, Pattern
010 Addr_value
011 Pattern
100 EndOfDiag
Method for Memory Diagnostic
S4-MEM FSM Diagram:
read_wait0wait_i_not_empty
idleread_wait1
read_wait_not_full
write_0
write_1
write_done
if_wr_pktof_rd_pkt
Reset
i_not_empty
“1”
write_data_eop
i_not_empty
“1”
~of_full&tx_eop
~of_full & ~tx_eop
“1”
“1”
CFPGA Interface
Read Write
of_wr_en
SRAM
Write Read
Addr[que:2][pkt:7][wd:9]
S4-RX_CTRL FSM Diagram:
Getwd4
DoOp
WtEOP
Getwd3
Getwd2
Getwd1
idle
Try_Rd Getwd0
rd_rdy_ci_ufpga_d1
rd_rdy_ci_ufpga_d1
rd_rdy_ci_ufpga_d1
rd_rdy_ci_ufpga_d1
rd_rdy_ci_ufpga_d1
eop_ci_ufpga
do_ctrldeny_ci_ufpga
“1”
“1”
grant_ci_ufpgaload_DA0123
load_DA45SA01
load_SA2345
load_OpcodeAddr
load_WrData
Reset
~do_ctrl
S4-TX_CTRL FSM Diagram:
SendPkt
Wt_Grant
Request
idle
done
do_tx_ctrl
“1” deny_ci_ufpga
grant_ci_ufpgawr_rdy_ci_ufpga_d1 & tx_ctrl_last word
else
“1”
Reset ~do_tx_ctrl
~(grant_ci_ufpga | deny_ci_ufpga)
S4-RX FSM Diagram:
Wt_EOP
Rx_DoneChk_Match
Wt_DAvldl
getDAhiidle
Try_Rd Granted
rd_rdy_ci_ufpga_d1
rd_rdy_ci_ufpga_d1
rd_rdy_ci_ufpga_d1 & eop_ci_ufpga
deny_ci_ufpga
do_read
“1”
grant_ci_ufpga
else“1”
“1”
Reset~do_read
S4-TX FSM Diagram:
Wt_EOP
DoneGranted
Wt_Grant
Start_Txidle
tx_eop
“1”
else
wr_rdy_ci_ufpga_d1
grant_ci_ufpga
Resetdo_write
“1”
deny_ci_ufpga
else
else
References:
[1] N. McKeown, “NetFPGA Project.” Online http://klamath.stanford.edu/NetFPGA/, Apr, 2003 [2] S. Gaggara, “Control of the NetFPGA board.” Online http://klamath.stanford.edu/NetFPGA/docs/Control_NetFPGA.pdf [3] Henry Fu, and Harn Hua Ng, “NetFPGA: Documentation for Developing User Modules” Online http://klamath.stanford.edu/NetFPGA/docs/user_doc.pdf [4] “The Sw4 UFPGA.” http://klamath.stanford.edu/NetFPGA/docs/Sw4.pdf [5] Henry Fu, and Harn Hua Ng, “NetFPGA: Design Architecture and Implementation.” Online http://klamath.stanford.edu/NetFPGA/docs/dev_doc.pdf [6] Altera Corporation, "Altera(R) APEX 20K Programmable Logic Devices." Online http://www.altera.com/literature/ds/apex.pdf