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© 2009

Venkata Yallapragada

Venkat Gaddam

Shripal Pandya

ALL RIGHTS RESERVED

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APPROVED FOR THE DEPARTMENT OF GENERAL ENGINEERING

___________________________________________________________

Prof. Leonard Wesley

___________________________________________________________

Hemant Jain, IntruGuard Devices

___________________________________________________________

Prof. Morris Jones

APPROVED FOR THE UNIVERSITY

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ABSTRACT

Network based appliances need thorough testing before being deployed at the

customer site. This requirement demands usage of packet generators that can generate

wide variety of traffic patterns that appears on the TCP/IP network. There is also a need

to test the capability of network devices to work with random packets. Packet generators

can be used to randomize the different fields of a TCP/IP packet.

Objective of this project is to design and develop a cost effective and high

performance network packet generator. Network packet generator (NPG) is a testing

equipment to test the various layer 2 (L2), layer3 (L3), and layer 4 (L4) based devices

such as switches, firewalls, virtual private networks (VPNs), and routers. NPG is capable

of generating random and customized L2, L3, and L4 packets to stress the device under

test (DUT). The market for this product is huge as every local area network (LAN) and

wide area network (WAN) based device requires NPG for its testing. This product aims

at bridging the gap of organizations which cannot afford to build in house and cannot buy

the existing expensive test equipment.

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ACKNOWLEDGMENT

We would like to express our gratitude and sincere thanks to our committee

members in guiding, supporting, helping, and challenging us to define a clear scope for a

better product.

We thank our advisor, Professor Morris Jones, Dept of Electrical Engineering,

San Jose State University for his valuable guidance and support.

We are very grateful to Mr. Hemant Jain, CTO, IntruGuard Devices Inc. for his

persistent help and guidance at each stage of this project.

Our sincere thanks to Prof. Leonard Wesley, San Jose State University for giving

us an opportunity to pursue ENGR 298 course under his guidance, and for his valuable

advices and suggestions that made our goals clear.

-Venkata Yallapragada

-Venkat Gaddam

-Shripal Pandya

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TABLE OF CONTENT

1 OBJECTIVE .......................................................................................................................1

2 INTRODUCTION.................................................................................................................1

2.1 Project scope ............................................................................................................................... 2

3 PROJECT DESCRIPTION ..................................................................................................2

3.1 Implemented Features................................................................................................................. 2

3.2 Functional details ........................................................................................................................ 3 3.2.1 Host Configuration ..................................................................................................................4 3.2.2 Packet Generation ...................................................................................................................4 3.2.3 MAC Interface..........................................................................................................................5

3.3 Deliverables................................................................................................................................. 5

3.4 Resources Utilized ....................................................................................................................... 5

4 LITERATURE SURVEY......................................................................................................5

4.1 TCP/IP Layers............................................................................................................................... 6

4.2 Network Access Layer (Layer 2).................................................................................................... 7 4.2.1 IEEE 802.3 (Ethernet) frame format ........................................................................................7

4.3 Internet Layer (Layer 3)................................................................................................................ 7 4.3.1 IP header .................................................................................................................................7

4.4 Transport Layer (Layer 4) ............................................................................................................. 8 4.4.1 TCP header ..............................................................................................................................8 4.4.2 UDP header..............................................................................................................................9

4.5 Testing Requirements .................................................................................................................10 4.5.1 Functional ..............................................................................................................................10 4.5.2 Reliability and Stress..............................................................................................................10

4.6 Market Research.........................................................................................................................12 4.6.1 Software based packet generators........................................................................................12 4.6.1.1 Features ............................................................................................................................12 4.6.1.2 Advantages and Disadvantages ........................................................................................13

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4.6.1.3 Tools feature comparison.................................................................................................14 4.6.2 Hardware based packet generators ......................................................................................16 4.6.2.1 Features ............................................................................................................................17 4.6.2.2 Advantages and Disadvantages ........................................................................................18 4.6.2.3 Vendors feature comparison ............................................................................................19

5 PROPOSED SOLUTION ..............................................................................................21

5.1 Architectural Overview ...............................................................................................................21

5.2 Main blocks of NPG Controller ....................................................................................................22 5.2.1 MAC Interface........................................................................................................................22 5.2.2 Host Interface ........................................................................................................................22 5.2.3 Configuration.........................................................................................................................23 5.2.3.1 Programming options .......................................................................................................23 5.2.3.2 Profile storing ...................................................................................................................23 5.2.4 Status.....................................................................................................................................24

6 ECONOMIC JUSTIFICATION..................................................................................24

6.1 Executive Summary ....................................................................................................................24

6.2 Problem Statement.....................................................................................................................26

6.3 Solution and Value Proposition...................................................................................................26

6.4 Market Size ................................................................................................................................27 6.4.1 Switch Segment Market ........................................................................................................27 6.4.2 Firewall/VPN Segment Market ..............................................................................................28 6.4.3 Security Segment Market ......................................................................................................28 6.4.3.1 Top Five Vendors ..............................................................................................................28

6.5 Competitors................................................................................................................................29

6.6 Customers ..................................................................................................................................32

6.7 Cost ............................................................................................................................................34 6.7.1 Hardware Components .........................................................................................................34 6.7.2 Labor......................................................................................................................................36 6.7.2.1 Salaries for the Year 2009.................................................................................................38 6.7.2.2 Salaries for the Year 2010.................................................................................................38 6.7.2.3 Salaries for the Year 2011.................................................................................................39 6.7.2.4 Salaries for the Year 2012.................................................................................................39 6.7.2.5 Salaries for the Year 2013.................................................................................................40

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6.7.2.6 Salaries for the Year 2014.................................................................................................41 6.7.2.7 Salaries for the Year 2015.................................................................................................42 6.7.3 Overhead ...............................................................................................................................43 6.7.4 Total Cost...............................................................................................................................45

6.8 Price point ..................................................................................................................................48

6.9 SWOT Analysis............................................................................................................................50

6.10 Investment Capital Requirements...........................................................................................51

6.11 Personnel...............................................................................................................................52

6.12 Business and Revenue Models................................................................................................53

6.13 Strategic Alliance / Partners ...................................................................................................53

6.14 Profit and Loss........................................................................................................................54 6.14.1 Year 2009 P & L Estimate..................................................................................................57 6.14.2 Year 2010 P & L Estimate..................................................................................................58 6.14.3 Year 2011 P & L Estimate..................................................................................................59 6.14.4 Year 2012 P & L Estimate..................................................................................................60 6.14.5 Year 2013 P & L Estimate..................................................................................................61 6.14.6 Year 2014 P & L Estimate..................................................................................................62 6.14.7 Year 2015 P & L Estimate..................................................................................................63 6.14.8 Return on Investment (ROI)..............................................................................................64 6.14.9 Norden‐Rayleigh Profile....................................................................................................64

6.15 Exit Strategy...........................................................................................................................67

7 PROJECT SCHEDULE......................................................................................................68

7.1 First Semester Project Schedule ..................................................................................................68 7.1.1 Task Sheet..............................................................................................................................68 7.1.2 Gantt chart ............................................................................................................................68

7.2 Second Semester Project Schedule..............................................................................................69 7.2.1 Task Sheet..............................................................................................................................69 7.2.2 Gantt chart ............................................................................................................................69

8 RESULTS ..........................................................................................................................70

9 FUTURE PLANS ............................................................................................................71

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10 CONCLUSION ................................................................................................................72

REFERENCES .........................................................................................................................73

APPENDIX A: VERILOG CODE .......................................................................................81

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List of Tables

Table 1: Packet generator basic requirements .................................................................. 11 Table 2: Features of software based packet generator ...................................................... 13 Table 3: Advantages and disadvantages of software based packet generators ................. 13 Table 4: Software based packet generators feature comparison (features and limitations)........................................................................................................................................... 16 Table 5: Features of hardware based packet generators ................................................... 18 Table 6: Advantages and disadvantages of hardware based packet generators................ 19 Table 7: Hardware based packet generators feature comparison (features and limitations)........................................................................................................................................... 21 Table 8: Top five vendors in Western Europe Security Appliances Market Revenue ($M)........................................................................................................................................... 29 Table 9: List of competitors and their geographical regions ............................................ 30 Table 10: Targeted Customers with their geographical regions ....................................... 34 Table 11: Per unit cost estimation for the first 20 units.................................................... 35 Table 12: NRE costs ......................................................................................................... 35 Table 13: Salary estimation for company personnel......................................................... 37 Table 14: Salary Calculation for year 2010 ...................................................................... 38 Table 15: Salary Calculation for year 2010 ...................................................................... 38 Table 16: Salary Calculation for year 2011 ...................................................................... 39 Table 17: Salary Calculation for year 2012 ...................................................................... 40 Table 18: Salary Calculation for year 2013 ...................................................................... 41 Table 19: Salary Calculation for year 2014 ...................................................................... 42 Table 20: Salary Calculation for year 2015 ...................................................................... 43 Table 21: Overhead cost for the year 2009....................................................................... 44 Table 22: Overhead cost estimation for the years 2009-2015 .......................................... 44 Table 23: Total overhead cost estimation for seven years (2009-2015)........................... 45 Table 24: Total cost estimation for the years 2009-2015 ................................................. 46 Table 25: Total cost estimation over the seven years (2009-2015) .................................. 47 Table 26: Cost per unit estimation for the years 2009-2015............................................. 49 Table 27: Average cost per unit over the seven years (2009-2015) ................................. 49 Table 28: Human Resources ............................................................................................. 52 Table 29: The projection of the revenue and cost over the seven years (2009-2015) ...... 54 Table 31: Total P & L estimation over the seven years (2009-2015)............................... 55 Table 32: Year 2009 P & L estimation ............................................................................. 57 Table 33: Year 2010 P & L estimation ............................................................................. 58 Table 34: Year 2011 P & L estimation ............................................................................. 59 Table 35: Year 2012 P & L estimation ............................................................................. 60

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Table 36: Year 2013 P & L estimation ............................................................................. 61 Table 37: Year 2014 P & L estimation ............................................................................. 62 Table 38: Year 2015 P & L estimation ............................................................................. 63 Table 39: Milestone schedule for semester I .................................................................... 68 Table 40: Milestone schedule for semester II ................................................................... 69 Table 41: Results summary............................................................................................... 71

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List of Figures

Figure 1: Network Packet Generator block diagram .......................................................... 4 Figure 2: TCP/IP and OSI model........................................................................................ 6 Figure 3: IEEE 802.3 (Ethernet) frame format ................................................................... 7 Figure 4: IP header format .................................................................................................. 8 Figure 5: TCP header .......................................................................................................... 9 Figure 6: UDP header ......................................................................................................... 9 Figure 7: Network Packet Generator ................................................................................ 22 Figure 8: Ethernet switch market share ............................................................................ 27 Figure 9: Rankings of the leading companies based on revenues in 2008 ....................... 31

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List of Plots

Plot 1: Top 5 vendors in Western Europe Security Appliances Market Revenue (IDC 2008) ................................................................................................................................. 29 Plot 2: Overhead cost distribution over the seven years ................................................... 45 Plot 3: Total cost distribution over the seven years (2009-2015) ..................................... 48 Plot 4: Profit and Loss....................................................................................................... 54 Plot 5: Profit and Loss analysis......................................................................................... 56 Plot 6: Year 2009 quartely P & L ..................................................................................... 57 Plot 7: Year 2010 quartely P & L ..................................................................................... 58 Plot 8: Year 2011 quartely P & L ..................................................................................... 59 Plot 9: Year 2012 quartely P & L ..................................................................................... 60 Plot 10: Year 2013 quartely P & L ................................................................................... 61 Plot 11: Year 2014 quartely P & L ................................................................................... 62 Plot 12: Year 2015 quartely P & L ................................................................................... 63 Plot 13: Low risk Rayleigh curve ..................................................................................... 65 Plot 14: Funding over the time (Low Risk) ...................................................................... 66 Plot 15: High risk Rayleigh curve..................................................................................... 66 Plot 16: Funding over the time (High Risk)...................................................................... 67 Plot 17: Gantt chart for semester I .................................................................................... 68 Plot 18: Gantt chart for semester II................................................................................... 70

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1 Objective

The objective of this project is to design and develop a network packet generator

that supports basic features and can generates randomized Layer 2, Layer 3, and Layer 4

header fields. Currently there are no hardware based network packet generators that offer

low cost and high performance. The goal is to offer a simple, low cost, and high

performance packet generator that can meet the basic testing needs of network appliance

industry.

2 Introduction

In recent years the Internet has become a utility. This utility standing demands

high reliability of the Internet 99.99% of the time. Networking devices such as switches,

routers, firewalls, and hubs are critical in data forwarding from one place to another.

These network devices need to be tested for high quality in less time for on time

deployment.

The requirement of high quality products necessitates a change and enhancement

in the organization’s basic testing procedures and methodologies. This affects the basic

philosophy and culture of an organization as testing of the network devices needs more

attention than before. This has caused a major impact on the testing strategy of the

product companies and made them to move their basic philosophy from conventional

testing to automatic testing.

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It is difficult to build a comprehensive test setup to test network devices due to the

modern technology and complexity involved in the design. Organizations are constantly

looking for a new test infrastructure to adopt into their test suites to manufacture high

quality products. The test suites should also check conformity to various compliance

requirements, as this has become mandatory in today’s global market. Network devices

should also be tested with random packets for their robustness. This requirement

demands usage of packet generators which can generate wide variety of traffic patterns

that appears on the TCP/IP network.

2.1 Project scope

The scope of this project includes defining a profitable, structured, and

dependable business model. The scope also includes design and development of network

packet generator using Verilog-HDL language. The business model involves

comprehensive analysis of the market over a period of seven years including cost,

investment, and revenue. Currently available hardware based packet generators are very

expensive. By designing a simple, low cost, and high performance packet generator, NPG

Inc. expects huge demand and revenues for this project.

3 Project Description

3.1 Implemented Features

Following are the specifications followed while implementing the design.

• Two Ethernet ports

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o Half duplex

o Full Gigabit rate

• Single stream per Ethernet port

• Single field randomization of either Layer 2 or Layer 3 header

• IPv4 support

• Ability to generate 1.4 million packets per second

• Programmable packet sizes

o Supported packet sizes: 64 to 9,000 bytes

• Provision to specify number of packets per second to send

o Default value is 100,000 packets

• Configuration option for single, burst, and continuous traffic generation

o Default option is single

• Provision to specify the test duration

o Default test duration is 100ms

• Configuration option to generate incorrect checksum

• Local bus interface for configuration

3.2 Functional details

NPG is divided into three major blocks based on the functionality. They are

packet generation block, MAC interface block, and host configuration block. NPG

generates the packets with fixed or random header fields based on the user configuration.

The following block diagram shows the data flow of the network packet generator.

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Figure 1: Network Packet Generator block diagram

3.2.1 Host Configuration

This block interfaces with the host and packet generation block. It stores all the

user configurations programmed by the host.

3.2.2 Packet Generation

This block interfaces with the MAC interface block to transfer the data onto the

SPI3 interface. Packet generation block reads the user configurations and generates

packets accordingly. It stores predefined profiles of Layer 2 and Layer 3 protocol headers

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and different pay loads. Finite state machine (FSM) of this block controls the data flow to

the MAC interface. It also generates two independent packet profiles and sends them onto

the respective MAC interface.

3.2.3 MAC Interface

This block’s main function is to drive the data provided by the packet generation

block on the SPI3 interface. There are two instances of this interface block to

communicate with the each of SPI3 interface.

3.3 Deliverables

• Verilog RTL

• Simulation Environment

3.4 Resources Utilized

• HDL Language: Verilog

• Simulation Tool: ModelSim

• Operating System: Windows Vista

4 Literature Survey

Computer communication over the network built on the Open Systems Interface

(OSI). For better modularity and to reduce the overhead of each layer, the seven layer

OSI model has been reduced to four layer TCP/IP protocol. TCP/IP protocol suite defines

the rules to communicate computers over the network. It specifies how the data

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addressing, formatting, and routing should be done for correct delivery the packet to the

destination. Internet Engineering Task Force (IETF) maintains the TCP/IP protocol

standards and these standards are usually available as RFCs (Request for comments).

Each standard is referred with a specific RFC number.

The top layers of TCP/IP are closer to the user application where as the lower

layers are closer to the physical transmission. Most of the current network traffic is based

on the TCP/IP protocol as it avoids overhead of multiple layers when compared to the

OSI model. The scope of this document is limited to the first three layers of TCP/IP.

4.1 TCP/IP Layers

Figure 2: TCP/IP and OSI model

(Source: http://learn-networking.com/tcp-ip/the-tcpip-stack-and-the-osi-model)

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4.2 Network Access Layer (Layer 2)

TCP/IP combines OSI model’s data link layer and physical layer and is named as

network access layer. TCP/IP uses existing data link and physical link standards rather

than defining a new set.

Examples: Ethernet, ATM, Token Ring etc.

4.2.1 IEEE 802.3 (Ethernet) frame format

The following is the IEEE 802.3 frame format which is used in the development

of network packet generator.

Preamble (1 byte)

Destination Address (6

bytes)

Source Address (6 bytes)

Type/Length (2 bytes)

Data (46 - 1500 bytes)

Check Sum (4 bytes)

Figure 3: IEEE 802.3 (Ethernet) frame format

4.3 Internet Layer (Layer 3)

The primary protocol of TCP/IP’s Internet layer is Internet Protocol (IP). It

interfaces with the upper layers (Application and Transport) and also with the network

access layer below for the data transfer. IP supports many protocols. Most popular of

them are TCP, UDP, and ICMP.

4.3.1 IP header

The following is the IP header format which is used in the development of

network packet generator.

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Figure 4: IP header format

(Source: http://www.networksorcery.com/enp/protocol/ip.htm)

4.4 Transport Layer (Layer 4)

Transport layer consists of two main protocols. They are Transmission Control

Protocol (TCP) and User Defined Protocol (UDP). TCP is used for reliable

communication and UDP is used for end to end data transport without reliability

checking.

4.4.1 TCP header

The following is the TCP header format.

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Version IHL TOS Total length

Identification Flags Fragment offset

TTL Protocol Header checksum

Source IP address

Destination IP address

Options and padding

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http://www.networksorcery.com/enp/protocol/ip.htm#Padding�

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Figure 5: TCP header

(Source: http://www.networksorcery.com/enp/protocol/udp.htm)

4.4.2 UDP header

The following is the UDP header format.

Figure 6: UDP header

(Source: http://www.networksorcery.com/enp/protocol/udp.htm)

Source Port Destination Port

Sequence Number

Acknowledgment Number

Data Offset

Reserved ECN Control

Bits Window

Checksum Urgent Pointer

Options and padding

Data

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4.5 Testing Requirements

Organizations are looking for a packet generator that can meet the current

demands of the networking industry. This should be a packet generator that is very basic

and available at an affordable price. RFC 2544 describes the “Benchmarking

Methodology for Network Interconnect Devices” that operates at Layer 2 and Layer 3.

These tests give a measure how well the device can perform in the real world. Besides

describing about the tests to be run, this document also describes the formats for

reporting of the test results.

Testing requirements can be broadly divided into Functional and Reliability and

Stress.

4.5.1 Functional

Under functional category, DUT is tested for its defined functionality, tests

related to devices’ capability to handle un-implemented features, standard compliance

tests, and interoperability tests to test the ability of hardware or software to work on

different platforms and different vendor machines in data forwarding

4.5.2 Reliability and Stress

Under this category DUT is tested for Latency through the device, packet loss in

the DUT, robustness test to handle legal and illegal packets, stress test, with random

payloads, back to back packets and its response, and finally for performance.

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Test all the layers of TCP/IP protocol stack

Analyze and generate comprehensive reports

Simultaneously test different protocols, varying payloads, and speeds

Test in realistic network environments

Generate different kinds of tests depending on the device under test

Generate random, step, and exponential traffic patterns

Generate realistic traffic

Generate multiple streams with repeatability options

Generate multi client and server environment

Generate different kinds of attacks at line speed

Script based testing for the automation

Achieve line rate performance

Future device upgrades

Table 1: Packet generator basic requirements

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4.6 Market Research

Market research indicated that there are two types of packet generator

technologies available in the market. Based on the implementation, they are categorized

as software and hardware based packet generators.

4.6.1 Software based packet generators

Many software based packet generators uses Libnet as the underlying packet

generating program. User interface is customized by different developers based on their

need and research requirement. These generators are inexpensive, not precise, but

flexible, and are developed mostly by research units. They cannot achieve high

performance due to various factors such as CPU speed, OS, and IO activity. These are

mostly available as open-source.

4.6.1.1 Features

Legal and illegal frames generation

ARP cache poisoning

Packet hand crafting

Trace replay capability

Customize the packets based on the DUT requirement

Vary inter packet gap and packet sizes

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Different packet load distributions

Support for IPv4 and IPv6

Generate traffic for network, transport, and application layers

Exercise the stability of protocol stack

Script based protocol generation

Generate continuous traffic

Automatic configuration parameters extraction based on the Netflow traces

Simulate various attacks

Table 2: Features of software based packet generator

4.6.1.2 Advantages and Disadvantages

Advantages Disadvantages

Flexible Un predictable response times

Inexpensive Cannot handle high data rates

Available as open-source Performance depends on the CPU, OS, and CPU load

Table 3: Advantages and disadvantages of software based packet generators

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4.6.1.3 Tools feature comparison

The following table illustrates the software based packet generator supported

features and their limitations.

Tool Packet

Generation

Packet

Analysis

Remarks

Nemesis Yes No Generates wide variety of traffic

GASP Yes No Packets are handcrafted

GSpoof3.0 Yes No Manipulates Ethernet, IP, TCP headers and have

the capability to vary the payloads

Harpoon Yes No Generates packets based on the parameters

extracted from the Netflow traces

Distributed

Internet

Traffic

Generator

Yes No 1. Varies IPG and Packet Sizes

2. Distribution supported is exponential,

uniform, cauchy, and normal pareto

3. Supports IPv4 and IPv6

4. Capable to generate traffic at network,

transport, and application layer

Pktgen Yes No Built into kernel and generates packets at high

rate

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PacketGene

rator

Yes No Sends the same packet repeatedly

Packet

Excalibur

Yes Yes Script based protocol generation

Packgen Yes No Generates multiple flows with the option of

programming destination, bandwidth, packet

size, and time range

Rude and

Crude

Yes Yes Supports only UDP

Scapy Yes Yes Legal and illegal frames, VLAN Hopping, ARP

Cache poisoning, and custom 802.11 frames

ISIC Yes No 1. Exercises stability of the protocol stack

2. Generates Pseudorandom packets of the target

protocol (TCP,UDP,ICMP)

3. Ability to define the mixture of randomness

such as options traffic of 25% and fragment

traffic of 30%

Packet Yes No Generates packets to the targeted protocol

(Ethernet, TCP, UDP, ICMP, IGMP etc...)

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Packit Yes Yes Injects customized packets

PacketX Yes No Used to simulate various attacks

SendIP Yes No Generates different kinds of headers using large

number f command line options

TCPivo Yes No Supports only trace replay

TCPReplay Yes No Connects to the server and replays the client side

of the connection using pcap file

Libnet Yes No This tool allows the application programmer to

construct and inject the packet

ZTI Yes Yes 1. Supports different protocols such as

TCP,UDP, ICMP

2. Supports 16 concurrent connections

3. Supports different profiles on each connection

4. Supports traffic capture and replay

5. Supports real-time traffic statistics

Table 4: Software based packet generators feature comparison (features and limitations)

4.6.2 Hardware based packet generators

Most of the testing logic is implemented in the hardware. Due to inbuilt micro

controller, these appliances are platform independent. They do not depend on the CPU

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speed or OS, and they can achieve high performance. These appliances can work at

higher speeds and provide highly accurate tests and analysis reports. Due to the

complexity involved these devices are expensive and are not openly available like

software. They are not as flexible as a software based generators.

These appliances have built in test suites to emulate multi-client and server

environments. The test suites are easy to run and customize to create various traffic

patterns. Often these devices come with the standard compliance test suites.

4.6.2.1 Features

Multi Server and Client environnent

Full decode of all protocol layers

Threshold based alarms and logs

Multiple streams per port

Generate and maintain session based TCP connections

Randomize different Layer header fields

Built in conformance test suites

Script based User Interface and tools to atomize the tests

Generate legal and illegal frames

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Generate 10,000 requests per second

Simulate more than 250,000 simultaneously connected users

Generate over 300,000 connections per port

Generate over 150,000 HTTP transactions per second per port

Congestion handling

Support of multi profiles

Limited Trace replay capability

Vary inter packet gap and packet sizes

Distribution can be linear, exponential, Cauchy, and normal pareto

IPv4 and IPv6 support

Exercise the stability of protocol stack

Generate single, burst, and continuous traffic

Simulate various attacks

Table 5: Features of hardware based packet generators

4.6.2.2 Advantages and Disadvantages

Advantages Disadvantages

Handles high rates Expensive

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Accurate Complex

High performance Requires periodic firmware updates

Predictability of the tests and response times Only available commercially

Table 6: Advantages and disadvantages of hardware based packet generators

4.6.2.3 Vendors feature comparison

The following table illustrates the different vendor’s hardware based packet

generator supported features and limitations.

Vendor Features

Valid8 1. Supports VoIP session packets

2. Multi client and server emulation modes

3. Statistics of the packets sent, received, and lost

4. Supports DHCP, Static, Virtual IP, and VLAN addresses

5. Jumbo and short packet generation capability

Radcom 1. Supports Layer 2 to Layer 7 protocols

2. Event generation based on the thresholds

3. Extensive logging

4. Capture and Replay

Interworking

Labs

1. Capable of creating TCP sessions

2. Emulates real time TCP traffic

3. Capable of generating anomalies

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4. Capable of generating various fragment packets

5. Capable of generating jumbo and short frames

6. Capable of congestion handling

7. Capable of Network Address Translation

Spirent 1. High Performance

2. Capable of emulating multi client and server environment

3. Capable of generating session and non session based packet traffic

4. Capable of generating 10,000 HTTP requests per second

5. Capable of handling 250,000 concurrent connections

6. Capable of generating 300,000 connections per second on each

port

7. Provides User Interface to program the various header fields

8. Supports automated testing using Tcl scripts

9. Capable of providing real-time statistics

Ixia 1. Supports only predefined test cases

2. Supports SONET and ATM

3. Supports daisy chaining of Chassis

4. Generates and monitors the packet traffic over several ports

simultaneously

Xtramus 1. Supports Gigabit traffic generation

2. Supports two switch and 16 module cards per chassis

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3. Supports collision generation and receipt

4. Supports single and burst mode of operation

5. Supports client and server architecture

Table 7: Hardware based packet generators feature comparison (features and limitations)

5 Proposed Solution

Literature review indicated that the all the software based packet generators lack

in performance even though they are inexpensive and flexible. Hardware based packet

generators are very expensive due to the complexity of the logic involved. Network based

devices should process variety of traffic that appears on the network. Hence every device

needs affordable and high performance packet generator for its testing. This is possible

by avoiding the complex logic that involves session based information handling and the

other protocol related logic.

The proposed solution is to design and develop a high performance and cost

effective network packet generator.

5.1 Architectural Overview

The following figure shows the data flow and various interfaces of the NPG.

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Figure 7: Network Packet Generator

5.2 Main blocks of NPG Controller

5.2.1 MAC Interface

The MAC Interface (MIF) block interfaces with the MAC controller to send and

receive packets in and out of the packet generator.

5.2.2 Host Interface

The Host Interface (HIF) block interfaces with the PCI local bus or USB local bus

to get the configuration information from the host and also provides support to access

status information.

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5.2.3 Configuration

Holds the user configuration values and passes this information to the other

blocks. Packet generator logic generates packet based on the configuration values

obtained from configuration block and also stores the profiles of the generated packets.

This is the main block of the design and its main functions are, stream control

generation, profiles storing, packet generation, and packet checking control generation.

5.2.3.1 Programming options

o User can configure up to two streams per port

o Bandwidth of each stream is controlled in terms of Mbps or packets/sec (ratio

is calculated based on this option and packets from these streams are mixed

based on this ratio)

o Header fields are randomized

o Burst or continuous option to control number of packets to send

o Provision to initialize non randomized fields of the header

o Random or fixed payload selection

5.2.3.2 Profile storing

o Hash is calculated on the randomized field. To have better distribution of hash

calculation includes all fields of the header

o Counters are maintained for each possible value of hash

o Once Packet is received, hash will be recalculated on the randomized data and

received packet count of that hash is incremented

24

o Each stream will have its own profile

5.2.4 Status

Packet check logic compares the incoming packet header fields with the stored

profiles. Generate reports for number of packet received without errors, packets received

with errors, and packets dropped.

o Counts number of packets sent

o Maintains test end time

For burst option test end time is 50ms after last packet sent

For continuous option test end time is controlled by user

o Counts number of packets received

o Reports number of packets received with and without errors

o Compares number of packet sent and received counts

o Reports number of packets dropped

6 Economic Justification

6.1 Executive Summary

In recent years network has become a commodity. This status demands the entire

network based devices tested thoroughly before being deployed. Network industry needs

automatic test equipment to automate the test environment and test the products

extensively with the variety of packets that appears on the network. This necessitates the

requirement of network packet generator that operates at high speed and available at an

affordable price.

25

NPGen Inc. intends to serve the network market test requirements by offering low

cost and high performance hardware based packet generator. Currently available

hardware based packet generators are very expensive and NPGen Inc. targets to reduce

the cost by eliminating the complex logic.

Networking industry can be represented broadly by three market segments. They

are Ethernet switches, Security appliances, and Firewall/VPNs and majority of these

devices operate on TCP/IP protocol. Every device of these segments require packet

generator to test for its functionality, performance, and compliance. Hence there is a huge

market for automatic network packet generator.

As per the electronics industry market research report, worldwide test equipment

market is valued at $19.5 billion in 2008 and the automatic test equipment (ATE)

segment itself is $3.7 billion. The report anticipates revenue growth of 11.5% for the year

2009 as ATE growth is relatively higher in 2008. Within next five years the total revenue

is expected to reach $13.4 billion, a 7.7% growth for the next five years. (“2008

Semiconductor”, 2008)

For the initial three years company will need an investment of $2,067,084 and in

the year 2012 company will become profitable. In the year 2015, company’s return on

investment (ROI) expected to be 127.48 % with the revenue of approximately $50

million.

26

6.2 Problem Statement

Currently available software based packet generators are not capable of

generating traffic at gigabit rate. Also they lack in performance and response times are

unpredictable. Whereas hardware based packet generators are very expensive and

involves complex logic. Majority of the network based devices needs to be tested

primarily for packet processing capability, hence there is a need for a packet generator

that offers low cost, basic features, and high performance.

6.3 Solution and Value Proposition

All the commercially available packet generators come with the complex

functions to support the variety of Internet based applications.

By avoiding the session oriented logic and by allowing the user to configure the

Layer 2, Layer 3, and Layer 4 header field randomization, NPGen Inc. offers a product at

low cost and high performance.

Most of the software based solutions are open source, but they cannot offer high

data rates due to the dependency on the underlying CPU speed. Hardware based solutions

are efficient and expensive due to the complexity in the design. Current available

hardware based packet generators price ranges from $25,000 to hundreds of thousand

dollars. NPGen Inc. packet generator cost will be around $5,000 and this price difference

will create a huge demand and profits.

27

6.4 Market Size

6.4.1 Switch Segment Market

Worldwide Ethernet switch market share is $18.2 billion in the year 2008, a

growth of 5% compared to the previous year in spite of global economic recession. (“The

Ethernet switch market”, 2009) In the year 2008, there is a jump of 56.4% in the one

gigabit (1G) fixed Ethernet market and 10 gigabit (10G) fixed Ethernet switch revenues

doubled. (“The Ethernet switch market”, 2009) The following figure compares the web-

managed 1G and 100M Ethernet switch ports shipped during 2008. (“A few surprises”,

2008)

Figure 8: Ethernet switch market share

(Source:

http://www.infonetics.com/pr/chartpopup.asp?id=2009/charts/ms09_sw_4q08_chart.jpg)

28

6.4.2 Firewall/VPN Segment Market

Firewall/VPN market was valued as $106.57 million in the second quarter of

2008, an increase of 24.8% over the year 2007. (IDC, 2008)

6.4.3 Security Segment Market

For the security appliances the revenue is expected to grow from $1.48 billion in

the year 2008 to $1.65 billion in 2009. (“Bucking a Trend”, 2009) Newer generations of

security appliances are offering some of the Firewall/VPN functions as part of the unified

threat management (UTM). Due to this there is a decrease in the firewall market revenues

and rise in the security segment.

6.4.3.1 Top Five Vendors

The following table shows the security appliance revenues of top five vendors in

Western Europe. There is a growth of 20% in this market from the year 2007 to 2008.

Vendor 2Q07

Revenue

2Q07 2Q08

Revenue

2Q08 Growth

Cisco $82.47 26.50% $108.34 29.00% 31.40%

Juniper $30.65 9.80% $29.50 7.90% -3.70%

Fortinet $13.54 4.40% $15.37 4.10% 13.50%

Nokia $12.94 4.20% $13.73 3.70% 6.10%

IronPort Systems $9.52 3.10% $11.96 3.20% 25.70%

Others $162.21 52.00% $194.25 52.10% 19.75%

29

Total market $311.33 100% $376.14 100% 19.90%

Table 8: Top five vendors in Western Europe Security Appliances Market Revenue ($M)

(Source: http://www.idc.com/getdoc.jsp?containerId=prUK21441308)

Plot 1: Top 5 vendors in Western Europe Security Appliances Market Revenue (IDC 2008)

6.5 Competitors

Since packet generator is a part of communication test equipment segment the

following analysis shows the direct and indirect competitors. Below table shows the list

of competitors and the geographical regions of market.

30

Competitors Geographic Regions

Agilent Technologies North America, South America, Europe,

Middle East, Africa, Asia-Pacific

Rohde and Schwarz North America, South America, Europe,


Anritsu North America, South America, Europe,


JDSU North America, South America, Europe,


Spirent Communications North America, South America, Europe,

Middle East, Africa, Asia-Pacific,

Australia

Tektronix Communications North America, South America, Europe,


EXFO North America, South America, Europe,


IXIA North America, South America, Europe,


Sunrise Telecom North America, South America, Europe,

Middle East

Table 9: List of competitors and their geographical regions

31

Ranking chart of leading communication test equipment market leaders based on

the revenues in 2008 is given below.

Figure 9: Rankings of the leading companies based on revenues in 2008

(Source: http://www.frost.com/prod/servlet/market-insight-top.pag?docid=161390925)

Agilent Technologies generated $366 million in communication test equipment

for the last quarter of 2008 fiscal year, which is 3 % of increase from the previous year.

(“Communication Test”, 2009)

32

Rohde and Schwarz, revenues were €1.4 billion which is approximately $1.8

billion in 2008 fiscal year. (“Communication Test”, 2009)

Anritsu’s test and measurement division revenues are ¥64,949.5 million which is

approximately $647 million for the fiscal year 2008. (“Communication Test”, 2009)

Spirent communication’s communication group made $251 million for the first

nine months of year 2008. (“Communication Test”, 2009)

IXIA revenues in the year 2008 are $175.4 million for year 2008.

(“Communication Test”, 2009)

6.6 Customers

NPGen Inc. targeted customers are in the field of security appliances and Ethernet

switch market. A subset of the targeted customers listed below.

Customer’s Name Geographic Regions

IntruGuard Devices USA

Cisco Systems USA, Africa, Asia/Pacific, Middle East, Europe

Juniper Networks USA, Africa, Asia/Pacific, Middle East, Europe

HP ProCurve USA, Africa, Asia/Pacific, Middle East, Europe

3Com North America, South America, Asia/Pacific, Middle

33

East , Europe, Australia

NETGEAR North America, South America, Asia/Pacific, Middle


Force10 Networks North America, South America, Asia/Pacific, Middle


Foundry Networks North America, South America, Asia/Pacific, Middle


Nortel Networks North America, South America, Asia/Pacific, Middle


D-Link North America, South America, Asia/Pacific, Middle


SMC Networks North America, South America, Asia/Pacific, Middle

East , Europe

Alcatel-Lucent North America, Asia/Pacific, Europe

Redback Networks North America, Asia/Pacific, Middle East , Europe

Huawei Technologies North America, South America, Asia/Pacific, Middle


34

Extreme Networks North America, Asia/Pacific, Middle East , Europe

Table 10: Targeted Customers with their geographical regions

6.7 Cost

The total cost of the product includes cost of materials required for board design

and development, cost of labor, and overhead cost.

6.7.1 Hardware Components

Hardware components are the materials used for the board assembly and

manufacturing. The cost of the product is based on the current value of the components

and engineering values. The first 20 units will cost more due to the Non Recurring

Expenditure (NRE) cost associated with the basic ASIC design. The component cost

mentioned in the below table includes FPGA cost of $500 is associated with prototype

product only. This cost will be replaced by chassis cost.

Component or Associated Technology Price

MAC (2-ports) $80

PHY (2-ports) $40

SRAM $15

FPGA (For proto-type only)/ Chassis $500

Power $60

35

Clocking $50

PCB $350

Assembly $400

PLX Chip $45

Miscellaneous (resistors, capacitors, LEDs, etc.) $45

Heat sink, Fan $20

ASIC Chip $150

Chip Test $5

Total $1760

Table 11: Per unit cost estimation for the first 20 units

The table above for the price point shows the cost for the first 20 units.

Component cost will significantly reduce based on the volume of products.

The following two items represents the NRE costs and is independent of number

of units produced per year.

NRE (Design) $25,000

NRE (ASIC) $250,000

Table 12: NRE costs

36

6.7.2 Labor

NPGen Inc. was started with three entrepreneurs in the third quarter of 2008. New

personnel will be hired based on the business needs in the subsequent years. For the

software development the company is also planning to set up an offshore facility in India.

The labor cost is low in the first year because the production will start in the year 2010.

The salary approximation for different positions is given below based on their experience

and skill in their respective field.

Position Salary (per annum)

CEO $180K – $200K

CFO $170K - $180K

CTO $160K – $180K

Director of Operations $140K – $150K

Marketing Personnel $140K – $150K

Sr. Software Engineer $100K – $110K

Sr. Hardware Engineer $100K – $110K

Jr. Software Engineer $60K – $70K

Jr. Hardware Engineer $60K – $70K

37

Test Engineer $60K - $70k

Desk Operator $30K – $40K

Supporting Staff $40K

Table 13: Salary estimation for company personnel

Each position in the company will be designated based on the experience and

education. The company will have four groups when the production starts in 2010 based

on the responsibilities and they are technical, admin, marketing, and support.

Technical group includes Sr. Engineers and Jr. Engineers. Sr. Engineers are

responsible for the core design and Jr. Engineers will be helping in the different

development phases of the product. Jr. Engineers are also responsible for testing.

Admin group has three different roles to perform; they are administrative,

management, and operational segments of the company. Depending on the position of

each personnel they will be assigned a specific task. Chief Executive Officer (CEO),

Chief Technology Officer (CTO), Chief Financial Officer (CFO), Director of Operations

(D.O.), and Vice President (VC) are going to be a part of this admin group.

Marketing group is responsible for the marketing of the product. This group will

work with the customers for strategic alliances to expand the market. They participate in

trade shows to market the product. This group will have Director of Marketing (DM),

sales managers, and sales persons.

38

Supporting staff will include quality assurance persons, laborers, and desk

operators.

There will be annual performance reviews for the employees. Based on the

business and profit the salaries will be revised. The following table shows human

resource requirement and their salaries year by year.

6.7.2.1 Salaries for the Year 2009

Dept Category Personnel Salary Total

Technical Sr. Engineer 3 100,000 300,000

Total 3 300,000

Table 14: Salary Calculation for year 2010



Sr. Engineer 3 100,000 300,000 Technical

Jr. Software 1 60,000 60,000

CEO 1 180,000 180,000 Admin

D.O 1 140,000 140,000

Marketing Marketing 1 140,000 140,000

Others Supporting staff 2 40,000 80,000

Total 9 900,000


39


Dept. Category Personnel Salary Total

Sr. Engineer 3 $100,000 $300,000

Jr. Engineer 1 $60,000 $60,000

Sr. Software 1 $100,000 $100,000

Technical

Jr. Software 1 $60,000 $60,000

CEO 1 $180,000 $180,000

CFO 1 $170,000 $170,000

CTO 1 $160,000 $160,000

Admin

D.O.s 1 $140,000 $140,000

Marketing D. of M. 1 $140,000 $140,000

Others Supporting staff 3 $40,000 $120,000

Total 14 $1,430,000




Sr. Engineer 3 $105,000 $315,000

Jr. Engineer 2 $65,000 $130,000

Sr. Software 1 $105,000 $105,000

Technical

Jr. Software 1 $65,000 $65,000

40

CEO 1 $190,000 $190,000

CFO 1 $175,000 $175,000

CTO 1 $165,000 $165,000

V.P. 1 $155,000 $155,000

Admin

D.O 1 $145,000 $145,000

D. of M. 1 $145,000 $145,000

Sales Manager 1 $100,000 $100,000

Marketing

sales Man 1 $70,000 $70,000

Other Supporting staff 4 $42,000 $168,000

Total 19 $1,928,000




Sr. Engineer 3 $110,000 $330,000

Jr. Engineer 3 $70,000 $210,000

Sr. Software 1 $110,000 $110,000

Technical

Jr. Software 2 $70,000 $140,000

CEO 1 $200,000 $200,000

CFO 1 $180,000 $180,000

Admin

CTO 1 $170,000 $170,000

41

V.P. 1 $165,000 $165,000

D.O 1 $150,000 $150,000

D. of M. 1 $150,000 $150,000

Sales Manager 1 $105,000 $105,000

Marketing

Sales Man 2 $75,000 $150,000


Total 23 $2285,000




Sr. Engineer 3 $115,000 $345,000

Jr. Engineer 3 $75,000 $225,000

Sr. Software 2 $110,000 $220,000

Technical

Jr. Software 2 $75,000 $150,000

CEO 1 $210,000 $210,000

CFO 1 $190,000 $190,000

CTO 1 $180,000 $180,000

V.P. 1 $175,000 $175,000

Admin

D.O 1 $160,000 $160,000

Marketing D. of M. 1 $160,000 $160,000

42

Sales Manager 2 $110,000 $220,000

sales Man 2 $80,000 $160,000

Others Supporting staff 6 $48,000 $288,000

Total 26 $2,683,000




Sr. Engineer 3 $120,000 $360,000

Jr. Engineer 3 $80,000 $240,000

Sr. Software 2 $115,000 $230,000

Technical

Jr. Software 2 $78,000 $156,000

CEO 1 $215,000 $215,000

CFO 1 $195,000 $195,000

CTO 1 $185,000 $185,000

V.P. 1 $180,000 $180,000

Admin

D.O 1 $165,000 $165,000

D. of M. 1 $165,000 $165,000

Sales Manager 2 $120,000 $240,000

Marketing

sales Man 4 $80,000 $320,000


43

Total 34 $3,251,000


6.7.3 Overhead

Cost associated with the overhead is based on different items. Overhead costs will

be applicable from the first year. Cost of office rent and utilities includes the cost for

current and future office space. Office supply and stationary includes paper products,

printers, scanners, telephone services, and packaging service costs. Travel expenses cover

the cost of travel for marketing the product at different geographic locations. Licensing

and documentation includes the cost of licenses for the tools and equipment with every

year’s upgrade. Compliance certification is required in order to sell the product in

different geographical locations. Overhead cost estimation for the first year is shown

below.

Expenses Amount

Office Rent and Utilities $120,000

Office supply and Stationary $12,000

Travel Expenses $24,000

Licensing and Documentation $5,000

Certification $50,000

44

Total $211,000

Table 21: Overhead cost for the year 2009

Below table shows year by year overhead cost approximation for the next seven

years.

Table 22: Overhead cost estimation for the years 2009-2015

Expenses Total

Office Rent and Utilities $1,045,960

Office supply and Stationary $112,357

Travel Expenses $234,332

Expenses 2009 2010 2011 2012 2013 2014 2015

Office Rent and

Utilities

$120,000 $126,000 $132,300 $138,915 $145,861 $153,154 $229,731

Office supply

and Stationary

$12,000 $12,360 $12,978 $14,276 $16,417 $19,701 $24,626

Travel

Expenses

$24,000 $25,440 $26,966 $29,663 $34,112 $40,935 $53,215

Licensing and

Documentation

$5,000 $5,000 $5,300 $5,600 $6,130 $6,970 $8,503

Certification $50,000 $51,500 $53,000 $54,500 $56,000 $57,500 $59,000

45

Licensing and Documentations $42,503

Certification $381,500

Table 23: Total overhead cost estimation for seven years (2009-2015)

The Pie chart below shows overhead cost distribution based on the categories over

the next seven years. Expenditure on office rent and utilities is 58% of total overhead,

where as travel expenses are 13%, and certification cost is about 21%.

Plot 2: Overhead cost distribution over the seven years

6.7.4 Total Cost

Total cost includes salaries of the employees, equipment cost, manufacturing cost,

product improvement cost, overhead cost, and marketing expenses.

46

Detailed year by year expenditure estimation of NPGen Inc. is listed below.

Category Year

2009 2010 2011 2012 2013 2014 2015

Salary $300,000 $900,000 $1,430,000 $1,928,000 $2,285,000 $2,683,000 $3,251,000

Tools $10,000 $20,000 $25,000 $30,000 $35,000 $40,000 $45,000

Equipment $5,000 $7,000 $10,000 $20,000 $25,000 $35,000 $45,000

Manufacturing $0 $378,400 $719,840 $1,439,680 $3,095,840 $7,120,960 $17,446,880

Product

Improvements

$0 $250,000 $250,000 $275,000 $300,000 $350,000 $425,000

Overhead $211,000 $220,300 $230,544 $242,954 $258,520 $278,259 $375,074

Marketing

Expenses

$0 $100,000 $120,000 $130,000 $150,000 $175,000 $200,000

Total $526,000 $1,875,700 $2,785,384 $4,065,634 $6,149,360 $10,682,219 $21,787,954

Table 24: Total cost estimation for the years 2009-2015

Salaries will be the second biggest cost after manufacturing costs. Manufacturing

cost is calculated by multiplying the number of units produced for each year with the

47

component cost ($1,760). Equipment and Tools cost includes computer servers,

automatic assembling machine and software license costs. Software license cost also

includes renewal and upgrades for each year. Product improvement includes NRE design

and ASIC development costs. Marketing costs include expenses for the trade-shows,

direct demos at customer site, and web casts.

Below table shows the total cost estimation over the next seven years.

Category Cost (in Dollars)

Salary $12,777,000

Tools $205,000

Equipment $147,000

Manufacturing $30,201,600

Product Improvements $1,850,000

Overhead $1,816,651

Marketing Expenses $875,000

Total $47,872,251

Table 25: Total cost estimation over the seven years (2009-2015)

Manufacturing is the biggest component with 63% of the total cost, whereas the

salaries are about 27 %, product inprovemets are 4%, overhead is 4%, and marketing

expenses are 2%. Tools and equipments are negligible with respect to other costs.

48

Plot 3: Total cost distribution over the seven years (2009-2015)

6.8 Price point

At present customers are paying about $25,000 to couple of hundred thousands of

dollars for the network packet generator. For example, basic model of Spirent costs

$25,000 and Ixia’s is $50,000. Depending on the features and applications required over

the base model, the cost of these products will increase significantly. (IXIA, 2008 &

SPIRENT, 2008)

The following tables illustrate the cost per unit of NPGen Inc. network packet

generator.

49

Year 2009 2010 2011 2012 2013 2014 2015

Number of Units

0 215 409 818 1759 4046 9913

Total Cost

$526,000 $1,875,700 $2,785,384 $4,065,634 $6,149,360 $10,682,219 $21,787,954

Cost per

Unit

$0 $8724 $6810 $4970 $3495 $2640 $2197

Table 26: Cost per unit estimation for the years 2009-2015

For 7 Years Total

Number of Units 17160

Total Cost $47,872,251

Price per Unit $2790

Table 27: Average cost per unit over the seven years (2009-2015)

The average cost of NPGen’s network packet generator is $2790 over the next

seven years. Even though in the initial years per unit cost is higher, with the increased

sales the cost will reduce as the percentage change in all other costs is less compared to

the number of units sold. NPGen’s packet generator is priced at $5,000 for the next seven

years. Even though the selling price is less than the cost during the initial years, increased

sales over the next years will offset the loss. The huge price difference between the

currently available packet generators and NPGen’s packet generator will enable NPGen

50

to enter into the market and gain market share. NPGen’s packet generator is an ideal

solution for the customers who need layer 2 to layer 4 gigabit packet generator at a lower

price.

6.9 SWOT Analysis

The SWOT analysis can be defined based on the Strengths, Weaknesses,

Opportunities, and Threats associated with the project in different characteristics.

According to the SWOT analysis strengths and weakness are associated internally,

whereas opportunities and threats are associated externally to the project. Basically

SWOT analysis helps to find the key areas correlated with the project at the initial

planning stage.

The SWOT analysis for NPGen is described below.

• Strengths:

o Currently no products available with basic feature set at lower price

o Simple design with basic features needed by the networking industry

o Inexpensive and easy to adopt compared to the existing solutions

o Full gigabit traffic generation capability

• Weaknesses:

o Limited to layer 2 to layer 4 packet generation

51

o No support for application based traffic generation

• Opportunities:

o As per the electronics industry market research, worldwide ATE segment

size is $3.7 billion with revenue growth of 11.5% for 2009. (“2008

Semiconductor”, 2008)

o Within next five years the total revenue is expected to grow about $13.4

billion, a growth of 7.7% for the next five years. (“2008 Semiconductor”,

2008)

• Threats:

o Software based solutions might give high performance due to the

improvement in the CPU speed.

o Established competitors can also develop similar low cost product.

6.10 Investment Capital Requirements

Cost analysis of NPGen shows that company needs an approximate investment of

$2,067,084 for the first three years of operation. In the subsequent years the company

will be profitable due to increase in sales and can generate revenue for the operation

through the sales. NPGen plans to get the investment through venture capitalists and

through the bank loans.

52

6.11 Personnel

The approximate human resources count over the next five years is shown in the

following table. Company will have only three human resources in the first year and

more people will be hired in the subsequent years as production starts. The expected head

count by the year 2015 is about 34. As the sales increase, additional sales and marketing

executives will be hired to support the increased customer base.

Department 2009 2010 2011 2012 2013 2014 2015

Engineering 3 3 4 5 6 6 6 Technical

Group Software 0 1 2 2 3 4 4

Administrative 0 1 1 1 1 1 1

Management 0 1 2 3 3 3 3

Admin Group

Operations 0 1 1 1 1 1 1

Marketing

Group

Marketing and

Sales

0 1 1 3 4 5 7

Other Supporting Staff 0 2 3 4 5 6 12

Total 3 10 14 19 23 26 34

Table 28: Human Resources

53

6.12 Business and Revenue Models

NPGen Inc. is expected to start its production in year 2010 with an initial target of

215 units. The company’s product is developed based on the strong technology demand

and huge global networking market. In the initial phase marketing will participate in

tradeshows and technological fairs at various places. Sales personnel will give live demo

of the product at the targeted customer’s site to familiarize them with the product.

Marketing team will also organize web-cast programs to show the customers benefits of

the product.

NPGen’s revenue is expected to grow every year based on the demand in the

market. From the year 2014 onwards, NPGen will cover different geographic regions as

customer base expands. In the year 2015, company will be producing about 10,000 units

with the total revenue of approximately $50 million. The ROI is expected to be 128% by

year 2015. Based on the revenue projections, company will occupy 1% of the total

networking testing equipment market by 2015.

6.13 Strategic Alliance / Partners

The company is mainly associated with IntruGuard Devices Inc. Initial production

of the company will support the requirements of the IntruGuard Devices Inc.

subsequently the production will be expanded to cater other targeted customers. The

facilities of the company will be established at various geographical regions such as,

South Asia, Middle East, Europe, and Australia to support customers at different

geographical regions.

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6.14 Profit and Loss

The estimated price of NPGen’s packet generator is $5,000. The following table

shows the revenue, cost, and profit calculations from 2009 to 2015. Revenue and cost are

based on the number of units sold in each year.

Year 2009 2010 2011 2012 2013 2014 2015

Number of

units

0 215 409 818 1759 4046 9913

Revenue $0 $1,075,000 $2,045,000 $4,090,000 $8,795,000 $20,230,000 $49,565,000

Cost $526,000 $1,875,700 $2,785,384 $4,065,634 $6,149,360 $10,682,219 $21,787,954

Profit/(loss) -$526,000 -$800,700 -$740,384 $24,366 $2,645,640 $9,547,781 $27,777,046

Table 29: The projection of the revenue and cost over the seven years (2009-2015)

Plot 4: Profit and Loss

55

In the year 2009, the company will not generate any revenues as the product is

still in the development phase and is not ready for the production. The company will

incur loss for the first three years. Company will achieve break even in the year 2012

with a marginal profit of $24,366. Company is going to make a profit of $27.8M by year

2015.

For 7 years Total

Number of units 17,160

Revenue $85,800,000

Cost $47,872,251

Profit/(loss) $37,927,749

Table 30: Total P & L estimation over the seven years (2009-2015)

56

• P & L estimation chart

Plot 5: Profit and Loss analysis

Quarterly break down of the P & L estimation for the years 2009 to 2015 is described

below.

57

6.14.1 Year 2009 P & L Estimate

1st Qt 2nd Qt 3rd Qt 4th Qt Total

Number of units 0 0 0 0 0

Revenue 0 0 0 0 0

Cost $131,500 $131,500 $131,500 $131,500 $526,000

Profit/Loss -$131,500 -$131,500 -$131,500 -$131,500 -$526000

Table 31: Year 2009 P & L estimation

Plot 6: Year 2009 quartely P & L

58



Number of units 30 45 60 80 215

Revenue $150,000 $225,000 $300,000 $400,000 $1,075,000

Cost $261,726 $392,589 $523,452 $697,933 $1,875,700

Profit/Loss -$111,726 -$167,589 -$223,452 -$297,933 -$800,700



59



Number of units 82 95 110 124 411

Revenue $410,000 $475,000 $550,000 $620,000 $2,055,000

Cost $555,721 $643,824 $745,480 $840,359 $2,785,384

Profit/Loss -$145,721 -$168,824 -$195,480 -$220,359 -$730,384



60



Number of units 150 185 225 258 818

Revenue $750,000 $925,000 $1,125,000 $1,290,000 $4,090,000

Cost $745,532 $919,489 $1,118,298 $1,282,315 $4,065,634

Profit/Loss $4,468 $5,511 $6,702 $7,685 $24,366



61



Number of units 345 395 475 544 1759

Revenue $1,725,000 $1,975,000 $2,375,000 $2,720,000 $8,795,000

Cost $1,206,100 $1,380,897 $1,660,572 $1,901,792 $6,149,360

Profit/Loss $518,900 $594,103 $714,428 $818,208 $2,645,640



62



Number of units 700 850 1040 1456 4046

Revenue $3,500,000 $4,250,000 $5,200,000 $7,280,000 $20,230,000

Cost $1,848,133 $2,244,162 $2,745,798 $3,844,117 $10,682,209

Profit/Loss $1,651,867 $2,005,839 $2,454,202 $3,435,883 $9,547,791



63



Number of units 1800 2200 2650 3263 9913

Revenue $9,000,000 $11,000,000 $13,250,000 $16315000 $49,565,000

Cost $3,956,229 $4,835,424 $5,824,488 $7,171,813 $21,787,954

Profit/Loss $5,043,771 $6,164,576 $7,425,512 $9,143,187 $27,777,046



64

6.14.8 Return on Investment (ROI)

ROI is defined as the ratio of profit earned over total capital invested.

ROI for the year 2015 =

=

= 127.48 %

Estimated ROI for the year 2015 is 127.48%.

6.14.9 Norden-Rayleigh Profile

Norden-Rayleigh curve shows the cumulative cost distribution over a time frame.

The equation is given below,

V (t) = d (1-e-at2)

V (t) = Total effort expected

d = Amount of money needed to approach the project (Investment)

t = Time

a = Shape factor (value of cost driver)

65

The shape factor can be defined as a positive or negative driver of the cost. In this

analysis we assumed two values of shape factors to cover low risk and high risk

situations.

The following curve shows the low risk analysis with the positive shape factor value of

0.4.

Drivers that contribute to the low risk (0.4 Value) are

1. Initial manufacturing setup cost

2. Competition with the established companies of the network test equipment market

Plot 13: Low risk Rayleigh curve

66

Plot 14: Funding over the time (Low Risk)

The following curve shows the low risk analysis with the negative shape factor value of

0.8.

Drivers that contribute to the high risk (0.8 Value) are:

1. Non availability of low cost and high performance packet generator

2. Huge market cap

Plot 15: High risk Rayleigh curve

67

Plot 16: Funding over the time (High Risk)

6.15 Exit Strategy

NPGen Inc. will either go for public offering or will look for an acquisition

depending on the market conditions and economy. Since this product can cater large

portion of networking market and generate huge revenues, the company will be

successful whatever path it might take.

68

7 Project Schedule

7.1 First Semester Project Schedule

7.1.1 Task Sheet

Table 38: Milestone schedule for semester I

7.1.2 Gantt chart

Plot 17: Gantt chart for semester I

69

7.2 Second Semester Project Schedule

7.2.1 Task Sheet

Table 39: Milestone schedule for semester II

7.2.2 Gantt chart

70

Plot 18: Gantt chart for semester II

8 Results

The following table lists implemented features, expected, and actual results. The

results are observed in the Verilog simulation using ModelSim simulator.

Feature Expected Actual

Gigabit rate packet

generation

Should generate 1.4 million

packets per second with 64

byte packet

Simulated with 100 packets

with 128 byte packet within

0.1ms. This results to 1.7

million packets per second.

Single field randomization

of Layer 2 and Layer 3

On selected field of Layer 2

or Layer 3 should be

randomized while all other

fields have default values

Simulated and verified that

the programmed field got

randomized while all other

fields are matched with the

default values

Programmable packet sizes Packet sizes should be

between 64 bytes to 9000

bytes

Verified the generation of

62 byte and 9002 byte

packet

Number of packets to send Number of packets

generated should be

programmed number of

packets

Verified with different

value of packet counts

71

Single Programmed number of

packets will be per test

Verified with a value of 10

packets

Burst Programmed number of will

be generated and sent for 8

times per test


packets

Continuous Programmed number of

packets will be generated

till user stop the test


packets

Programmable test duration Test duration should be as

per the programmed test

duration

Verified with different

values of test duration

Incorrect checksum

generation

Generate incorrect

checksum

Verified the generation of

incorrect checksum

Table 40: Results summary

9 Future Plans

In future the product performance can be enhanced to support 10 Gigabit traffic.

Enhancements can be made to support full duplex traffic handling, multiple streams per

MAC port, self checking and exhaustive status reporting. The status can include number

of packets generated, received correctly, received with errors, and lost.

72

10 Conclusion

The need for high performance and low cast hardware based packet generator is

achieved through the proposed network packet generator. By implementing the basic

features that are needed by networking industry, the testing cost can be reduced

considerably while the quality of the product improves. Design is implemented in Verilog

and results are verified using ModelSim simulator. Current product supports 1Gbps data

rate, however performance can be increased to cater 10GE products with minor changes

to the design.

Economic analysis shows that there is a great demand for this product. Analysis

further indicated that break-even is possible within three years of the product launch and

ROI of 128% is achieved by the year 2015. NPGen Inc. requires an investment of $2M

and the product is profitable from the year 2012 onwards.

73

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81

Appendix A: Verilog code

//-------------------------------------------------------------------------//

//

// Venkata Yallapragada : 004790397

// Venkat Gaddam : 004466749

// Shripal Pandya : 005349956

//

// Course : ENGR298 (Spring 2009)

// Project : Network Packet Generator

// Module : tb_npgen

// San Jose State University

//-------------------------------------------------------------------------//

`timescale 1ns/1ns

module tb_npgen;

`define NPG_CR_REG_ADDR 31'd0

`define PRG_PKT_CNT_REG_ADDR 31'd1

`define PRG_PKT_SIZE_REG_ADDR 31'd2

`define TEST_TIME_REG_ADDR 31'd3

reg clk, reset;

reg host_wr_rd_l;

reg host_ce_l;

reg [31:0] host_addr;

82

reg [31:0] host_wr_data;

wire [31:0] host_rd_data;

wire dtpa_p0;

wire [31:0] tdat_p0;

wire tsop_p0;

wire teop_p0;

wire tenb_p0;

wire terr_p0;

wire tprty_p0;

wire [1:0] tmod_p0;

wire dtpa_p1;

wire [31:0] tdat_p1;

wire tsop_p1;

wire teop_p1;

wire tenb_p1;

wire terr_p1;

wire tprty_p1;

wire [1:0] tmod_p1;

initial

begin

clk = 1'b0;

reset <= 1'b0;

host_wr_rd_l <= 1'd0;

host_ce_l <= 1'd0;

83

host_addr <= 32'd0;

host_wr_data <= 32'd0;

end

always #16 clk = ~clk;

npg_top npg_top (

.tdat_p0(tdat_p0),

.tsop_p0(tsop_p0),

.teop_p0(teop_p0),

.tenb_p0(tenb_p0),

.terr_p0(terr_p0),

.tprty_p0(tprty_p0),

.tmod_p0(tmod_p0),

.dtpa_p0(dtpa_p0),

.tdat_p1(tdat_p1),

.tsop_p1(tsop_p1),

.teop_p1(teop_p1),

.tenb_p1(tenb_p1),

.terr_p1(terr_p1),

.tprty_p1(tprty_p1),

.tmod_p1(tmod_p1),

.dtpa_p1(dtpa_p1),

.host_wr_rd_l(host_wr_rd_l),

.host_ce_l(host_ce_l),

.host_addr(host_addr),

84

.host_wr_data(host_wr_data),

.host_rd_data(host_rd_data),

.reset(reset),

.clk(clk)

);

port_stim port_stim0(

.tdat(tdat_p0),

.tsop(tsop_p0),

.teop(teop_p0),

.tenb(tenb_p0),

.terr(terr_p0),

.tprty(tprty_p0),

.tmod(tmod_p0),

.dtpa(dtpa_p0),

.reset(reset),

.clk(clk)

);

port_stim port_stim1(

.tdat(tdat_p1),

.tsop(tsop_p1),

.teop(teop_p1),

.tenb(tenb_p1),

.terr(terr_p1),

.tprty(tprty_p1),

85

.tmod(tmod_p1),

.dtpa(dtpa_p1),

.reset(reset),

.clk(clk)

);

// Tasks

task nop;

input [63:0] cnt;

begin

repeat (cnt) @ (posedge clk);

end

endtask

task apply_reset;

begin

reset = 1'd1;

nop(4);

reset = 1'd0;

end

endtask

task start_pktgen;

input port;

begin

host_wr(port, `NPG_CR_REG_ADDR, 32'd1);

end

86

endtask

task stop_pktgen;

input port;

begin

host_wr(port, `NPG_CR_REG_ADDR, 32'd0);

end

endtask

task host_wr;

input port;

input [30:0] addr;

input [31:0] wr_data;

begin


host_ce_l <= 1'd0;

host_addr <= {port, addr};

host_wr_data <= wr_data;

@(posedge clk);

host_ce_l <= 1'd1;

if (port) port_stim1.host_wr(addr[30:0], wr_data);

else port_stim0.host_wr(addr[30:0], wr_data);

end

endtask

task host_rd;

input port;

87

input [31:0] addr;

input [31:0] rd_data;

begin

@(posedge clk);


host_ce_l <= 1'd0;

host_addr <= {port, addr};

@(posedge clk);

host_ce_l <= 1'd1;

if(host_rd_data === rd_data) $display ("Expected data is read (=%h)", host_rd_data);

else $display ("FAIL: Expected data is not read EXP= %h ACT= %h", rd_data, host_rd_data);

end

endtask

task stopsim;

begin

nop(10);

fork

if(port_stim0.pkt_tx_start) port_stim0.stopsim; else port_stim0.port_done = 1'd1;

if(port_stim1.pkt_tx_start) port_stim1.stopsim; else port_stim1.port_done = 1'd1;

join

wait(port_stim0.port_done & port_stim0.port_done);

port_stim0.port_done = 1'd0;

port_stim1.port_done = 1'd0;

88

if(port_stim0.err_cnt > 0 | port_stim1.err_cnt > 0 ) $display ("\n\n%t %m Simulation FAIL: P0 Err count = %d P1 Err count = %d\n\n",$realtime, port_stim0.err_cnt, port_stim1.err_cnt);

else $display ("\n\n%t %m Simulation PASS\n\n",$realtime);

$stop;

end

endtask

task endsim;

begin

$finish;

end

endtask

`include "test.v"

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : port_stim


89

//-------------------------------------------------------------------------//

`timescale 1ns/100ps

module port_stim(

input [31:0] tdat,

input tsop,

input teop,

input tenb,

input terr,

input tprty,

input [1:0] tmod,

output reg dtpa,

input reset,

input clk

);

reg [7:0] pkt_start;

reg [2:0] l2h_len;

reg [2:0] l3h_len;

reg [15:0] l3d_len;

reg l2h_rcvd;

reg l3h_rcvd;

reg l3d_rcvd;

reg sop_rcvd_pipe;

reg eop_rcvd_pipe;

reg [31:0] tdat_pipe;

90

reg [1:0] tmod_pipe;

reg pkt_tx_start;

reg [26:0] pkt_cnt_lim;

reg [16:0] pkts_rcvd;

integer err_cnt;

reg [31:0] l3h_exp_data_pipe;

reg data_rcvd;

reg sop_rcvd_pipe1;

reg prg_psize;

reg pkt_cnt_prg;

reg random_psize;

reg [15:0] pkt_size_lim;

reg [15:0] def_pkt_cnt_lim;

reg [31:0] rand_modifier;

reg port_done;

reg chksum_err;

reg crc_err;

initial

begin

err_cnt = 0;

dtpa <= 1'b1;

pkt_tx_start <= 1'd0;

l2h_rcvd <= 1'd0;

l3h_rcvd <= 1'd0;

91

l3d_rcvd <= 1'd0;

l2h_len <= 3'd4;

l3h_len <= 3'd5;

l3d_len <= 16'd88;

data_rcvd<= 1'd0;

sop_rcvd_pipe<= 1'd0;

eop_rcvd_pipe<= 1'd0;

sop_rcvd_pipe1<= 1'd0;

port_done <= 1'd0;

chksum_err <= 1'd0;

crc_err <= 1'd0;

prg_psize <= 1'd0;

pkt_cnt_prg <= 1'd0;

random_psize <= 1'd0;

pkt_size_lim <= 16'd88;

rand_modifier <= 32'ha59b_4fd7;

ìfdef LESS_PKT_CNT

def_pkt_cnt_lim = 27'd4;

èlse

def_pkt_cnt_lim = 27'd100_000;

èndif

pkt_cnt_lim = def_pkt_cnt_lim;

pkts_rcvd = 0;

end

92

// Tasks

task nop;

input [63:0] cnt;

begin

repeat (cnt) @ (posedge clk);

end

endtask

reg random_en;

reg [3:0] random_sel;

reg ttype_cont;

task host_wr;

input [31:0] addr;

input [31:0] wr_data;

begin

if(addr == `NPG_CR_REG_ADDR) pkt_tx_start <= wr_data[0];

if(addr == `NPG_CR_REG_ADDR) prg_psize <= wr_data[1];

if(addr == `NPG_CR_REG_ADDR) pkt_cnt_prg <= wr_data[2];

if(addr == `NPG_CR_REG_ADDR) random_en <= wr_data[3];

if(addr == `NPG_CR_REG_ADDR) random_sel <= wr_data[3] ? wr_data[15:12] : 4'd0;

if(addr == `PRG_PKT_CNT_REG_ADDR) pkt_cnt_lim <= wr_data[26:0];

if(addr == `TEST_TIME_REG_ADDR) pkt_cnt_lim <= (wr_data[3:0] + 1) * pkt_cnt_lim;

if(addr == `NPG_CR_REG_ADDR) pkt_cnt_lim <= (wr_data[5:4] == 2'd1 ? 8 : 1) * pkt_cnt_lim;

93

if(addr == `NPG_CR_REG_ADDR) ttype_cont <= wr_data[5:4] == 2'd2;

if(addr == `PRG_PKT_SIZE_REG_ADDR) pkt_size_lim <= wr_data[15:0];

if(addr == `NPG_CR_REG_ADDR) pkt_size_lim <= wr_data[1] ? pkt_size_lim : 16'd88;

if(addr == `NPG_CR_REG_ADDR) chksum_err <= wr_data[6];

if(addr == `NPG_CR_REG_ADDR) crc_err <= wr_data[7];

end

endtask

task stopsim;

begin

wait (pkts_rcvd == pkt_cnt_lim);

if(err_cnt > 0) $display ("\n\n%t %m Simulation FAIL: Err count = %d\n\n",$realtime, err_cnt);

else $display ("\n\n%t %m Simulation PASS: Err count = %d\n\n",$realtime, err_cnt);

port_done = 1'b1;

end

endtask

always @ (posedge clk or posedge reset)

if(reset)

begin

pkt_start <= 8'd0;

end

else

begin

94

pkt_start <= {pkt_start[6:0], pkt_tx_start};

end

wire sop_rcvd = !tenb & tsop;

wire eop_rcvd = !tenb & teop;

reg [15:0] rand_psize;

wire [15:0] rand_psize_orig = (random_sel == 4'd5 ? rand_modifier[15:0] ^ 16'd88 : pkt_size_lim);

wire [15:0] rand_psize_pre = (rand_psize_orig / 4) * 4;

always @ (posedge clk)

begin

l2h_len <= sop_rcvd ? 3'd4 : l2h_rcvd ? l2h_len - 1'b1 : l2h_len;

l3h_len <= sop_rcvd ? 3'd6 : l3h_rcvd ? l3h_len - 1'b1 : l3h_len;

l3d_len <= sop_rcvd ? rand_psize_pre : l3d_rcvd ? (l3d_len < 16'h4 ? 0 : l3h_rcvd ? l3d_len - 16'd2 : l3d_len - 16'd4): l3d_len;

end


if(sop_rcvd | sop_rcvd_pipe | sop_rcvd_pipe1) begin

l2h_rcvd <= !tenb & (l2h_len > 3'd1) | sop_rcvd;

l3h_rcvd <= !tenb & (l3h_len > 3'd1) & (l2h_len <= 3'd2);

l3d_rcvd <= !tenb & (l3h_len == 3'd2 | l3d_len > 16'd2 & l3h_len < 3'd2);

end


begin

sop_rcvd_pipe <= sop_rcvd ? 1'b1 : eop_rcvd ? 1'd0 : sop_rcvd_pipe;

95

sop_rcvd_pipe1 <= sop_rcvd_pipe;

data_rcvd <= !tenb;

eop_rcvd_pipe <= eop_rcvd;

tdat_pipe <= tdat;

tmod_pipe <= tmod;

rand_modifier <= rand_modifier + data_rcvd;

end


begin

pkts_rcvd <= sop_rcvd_pipe1 & !sop_rcvd_pipe ? (!pkt_tx_start ? pkt_cnt_lim : (ttype_cont ? pkts_rcvd : pkts_rcvd + 1'b1)) : pkts_rcvd;

rand_psize <= sop_rcvd ? rand_psize_pre : rand_psize;

end

wire [31:0] l2h_exp_data = l2h_len == 3'd4 ? random_sel == 4'd1 ? rand_modifier ^ {2{16'hf0e2}} : {2{16'hf0e2}} :

l2h_len == 3'd3 ? {random_sel == 4'd2 ? rand_modifier[31:16] ^16'h0f2e :16'h0f2e, random_sel == 4'd1 ? rand_modifier[15:0] ^ 16'hf0e2 : 16'hf0e2} :

l2h_len == 3'd2 ? random_sel == 4'd2 ? rand_modifier ^ {2{16'hf0e2}} : {2{16'hf0e2}} :

random_sel == 4'd3 ? rand_modifier ^ {16'd0, {16'h0011}} : {16'd0, {16'h0011}};

wire [31:0] l3h_exp_data = l3h_len == 3'd6 ? {rand_psize,

random_sel == 4'd4 ? rand_modifier[15:8]^ 8'd0 : 8'd0, 4'd5, 4'd4} :

l3h_len == 3'd5 ? {random_sel == 4'd8 ? rand_modifier[31:19] ^ 13'd0 : 13'd0,

96

random_sel == 4'd7 ? rand_modifier[18:16] ^ 3'd2 : 3'd2,

random_sel == 4'd6 ? rand_modifier[15:0] ^ 16'd1 : 16'd1} :

l3h_len == 3'd4 ? {random_sel == 4'd10 ? rand_modifier[31:24] ^8'd2 : 8'd2,

random_sel == 4'd9 ? rand_modifier[23:16]^ 8'd6 : 8'd6, 16'hx} :

l3h_len == 3'd3 ? random_sel == 4'd11 ? rand_modifier ^ {1'b0, 7'd1, 24'd1} : {1'b0, 7'd1, 24'd1} :

random_sel == 4'd12 ? rand_modifier ^ {1'b0, 7'd1, 24'd2} : {1'b0, 7'd1, 24'd2};

wire [31:0] l3d_exp_data = l3d_len[2] ? 32'h9867_4321 : 32'hbaba_dada;

reg [31:0] crc_exp_data;

reg [31:0] crc_exp_data1;


begin

l3h_exp_data_pipe <= l3h_exp_data;

end

wire [15:0] chk_byte32 = tmod_pipe[1] ? 16'h0 :

l2h_rcvd & !l3h_rcvd ? 16'd0:

(l2h_rcvd | l3h_rcvd & !l3d_rcvd) ? tdat_pipe[31:16] : 16'd0;

wire [15:0] chk_byte10 = tmod_pipe[0] ? 16'h0 :

l2h_rcvd ? 16'd0 :

l3h_rcvd ? tdat_pipe[15:0] : 16'd0;

wire [15:0] exp_byte32 = tmod_pipe[1] ? 16'hxxxx :

97

l2h_rcvd & !l3h_rcvd ? l2h_exp_data[31:16] :

(l2h_rcvd | l3h_rcvd & !l3d_rcvd) ? l3h_exp_data[15:0] :

l3d_len <= 16'd2 ? crc_exp_data[15:0] : l3d_exp_data[15:0];

wire [15:0] exp_byte10 = tmod_pipe[0] ? 16'hxxxx :

l2h_rcvd ? l2h_exp_data[15:0] :

l3h_rcvd ? l3h_exp_data_pipe[31:16] :

l3d_len == 16'd0 ? crc_exp_data1[31:16] : l3d_exp_data[31:16];

wire [15:0] crc_byte32 = tmod_pipe[1] ? 16'h0 :

l2h_rcvd & !l3h_rcvd ? l2h_exp_data[31:16] :

(l3h_rcvd & l3h_len == 3'd4) ? tdat_pipe[31:16] :

(l2h_rcvd | l3h_rcvd & !l3d_rcvd) ? l3h_exp_data[15:0] :

l3d_len <= 16'd2 ? 16'd0 : l3d_exp_data[15:0];

wire [15:0] crc_byte10 = tmod_pipe[0] ? 16'h0 :

l2h_rcvd ? l2h_exp_data[15:0] :

l3h_rcvd ? l3h_exp_data_pipe[31:16] :

l3d_len == 16'd0 ? 16'd0 : l3d_exp_data[31:16];

wire [31:0] exp_data = {exp_byte32, exp_byte10};


if(data_rcvd)

if ((tdat_pipe[31:24] === exp_data[31:24] | exp_data[31:24] === 8'hxx) &

(tdat_pipe[23:16] === exp_data[23:16] | exp_data[23:16] === 8'hxx) &

(tdat_pipe[15:8] === exp_data[15:8] | exp_data[15:8] === 8'hxx) &

98

(tdat_pipe[7:0] === exp_data[7:0] | exp_data[7:0] === 8'hxx))

$display ("%m %t Expected data is read (=%h), pkt rcvd = %d, pkt_cnt = %d, data type = %b", $realtime, tdat_pipe, pkts_rcvd, l3d_len, {l2h_rcvd, l3h_rcvd, l3d_rcvd});

else begin

err_cnt = err_cnt + 1'b1;

$display ("%m %t FAIL: Expected data is not read EXP= %h ACT= %h , pkt rcvd = %d, pkt_cnt = %d, data type = %b", $realtime, {exp_byte32, exp_byte10}, tdat_pipe, pkts_rcvd,l3d_len, {l2h_rcvd, l3h_rcvd, l3d_rcvd});

end

reg [31:0] chk1;

wire [15:0] chk = chk1[15:0] + chk1[31:16];


begin

if(data_rcvd) chk1 <= chk1 + chk_byte32 + chk_byte10;

else if (tsop | teop) chk1 <= 32'd0;

if(teop)

if(!chksum_err) begin

if(chk !== 16'hFFFF) begin err_cnt = err_cnt + 1'b1; $display("%m %t FAIL: Check sum is not correct = %h", $realtime, chk); end

else $display("%m %t Check sum is correct = %h", $realtime, chk);

end

else begin

if(chk == 16'hFFFF) begin err_cnt = err_cnt + 1'b1; $display("%m %t FAIL: Check sum is not correct = %h", $realtime, chk); end

99

else $display("%m %t Check sum is correct = %h", $realtime, chk);

end

end

parameter eth_crc_pol = 32'h04C11DB7;

integer data_len, pos;

reg last_bit;

reg [7:0] tx_data;

reg [31:0] final_crc32;

reg [31:0] tb_crc32;

reg [7:0] c1;

reg [7:0] c2;

reg [7:0] c3;

reg [7:0] c4;

reg [7:0] d1;

reg [7:0] d2;

reg [7:0] d3;

reg [7:0] d4;

always @ (data_rcvd or eop_rcvd_pipe or crc_byte10 or crc_byte32)

if(eop_rcvd_pipe) tb_crc32 <= #1 {32{1'b1}};

else if(data_rcvd)

begin

for (data_len = 0; data_len < 4; data_len = data_len + 1) begin

tx_data = data_len < 1 ? crc_byte10[7:0] :

100

data_len < 2 ? crc_byte10[15:8]:

data_len < 3 ? crc_byte32[7:0] : crc_byte32[15:8];

for (pos = 0; pos < 8; pos = pos + 1) begin

last_bit = tb_crc32[31]; tb_crc32 = {tb_crc32[30:0], 1'b0};

if (last_bit != tx_data[pos]) begin tb_crc32 = tb_crc32 ^ eth_crc_pol; tb_crc32[0] = 1; end

end

end

end

always @ (tb_crc32) begin

c1 = tb_crc32[31:24];

c2 = tb_crc32[23:16];

c3 = tb_crc32[15:8];

c4 = tb_crc32[7:0];

for (pos = 7; pos >= 0; pos = pos - 1) begin

d1[pos] = ~c1[7-pos];

d2[pos] = ~c2[7-pos];

d3[pos] = ~c3[7-pos];

d4[pos] = ~c4[7-pos];

end

final_crc32 = {d1,d2, d3, d4};

end


crc_exp_data <= final_crc32;

101


crc_exp_data1 <= crc_err ? ~crc_exp_data : crc_exp_data;

initial

begin

chk1 = 0;

tmod_pipe = 0;

tb_crc32 = {32{1'b1}};

end

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : npg_top


//-------------------------------------------------------------------------//

module npg_top(

output [31:0] tdat_p0,

output tsop_p0,

102

output teop_p0,

output tenb_p0,

output terr_p0,

output tprty_p0,

output [1:0] tmod_p0,

input dtpa_p0,

output [31:0] tdat_p1,

output tsop_p1,

output teop_p1,

output tenb_p1,

output terr_p1,

output tprty_p1,

output [1:0] tmod_p1,

input dtpa_p1,

input host_wr_rd_l,

input host_ce_l,

input [31:0] host_addr,

input [31:0] host_wr_data,

output [31:0] host_rd_data,

input reset,

input clk

);

wire [31:0] host_rd_data_p0;

wire [31:0] host_rd_data_p1;

103

sng_port sng_port0 (

.port_num(1'b0),

.tdat(tdat_p0),

.tsop(tsop_p0),

.teop(teop_p0),

.tenb(tenb_p0),

.terr(terr_p0),

.tprty(tprty_p0),

.tmod(tmod_p0),

.dtpa(dtpa_p0),





.host_rd_data(host_rd_data_p0),

.reset(reset),

.clk(clk)

);

sng_port sng_port1 (

.port_num(1'b1),

.tdat(tdat_p1),

.tsop(tsop_p1),

.teop(teop_p1),

104

.tenb(tenb_p1),

.terr(terr_p1),

.tprty(tprty_p1),

.tmod(tmod_p1),

.dtpa(dtpa_p1),





.host_rd_data(host_rd_data_p1),

.reset(reset),

.clk(clk)

);

assign host_rd_data = host_rd_data_p1 | host_rd_data_p0;

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : sng_port

105


//-------------------------------------------------------------------------//

module sng_port(

input port_num,

output [31:0] tdat,

output tsop,

output teop,

output tenb,

output terr,

output tprty,

output [1:0] tmod,

input dtpa,

input host_wr_rd_l,

input host_ce_l,




input reset,

input clk

);

wire [31:0] npg_cr;

wire [26:0] prg_pkt_cnt;

wire [15:0] prg_pkt_size;

wire [3:0] test_time ;

106

wire [31:0] tdat_local;

wire tsop_local;

wire teop_local;

wire tenb_local;

wire terr_local;

wire tprty_local;

wire [1:0] tmod_local;

host_if host_if(

.port_num(port_num),

.npg_cr(npg_cr),

.prg_pkt_cnt(prg_pkt_cnt),

.prg_pkt_size(prg_pkt_size),

.test_time(test_time),





.host_rd_data(host_rd_data),

.reset(reset),

.clk(clk)

);

mac_if mac_if(

.tdat(tdat),

.tsop(tsop),

107

.teop(teop),

.tenb(tenb),

.terr(terr),

.tprty(tprty),

.tmod(tmod),

.dtpa(dtpa),

.tdat_local(tdat_local),

.tsop_local(tsop_local),

.teop_local(teop_local),

.tenb_local(tenb_local),

.terr_local(terr_local),

.tprty_local(tprty_local),

.tmod_local(tmod_local),

.dtpa_local(dtpa_local),

.reset(reset),

.clk(clk)

);

pkt_gen pkt_gen (

.tdat(tdat_local),

.tsop(tsop_local),

.teop(teop_local),

.tenb(tenb_local),

.terr(terr_local),

.tprty(tprty_local),

108

.tmod(tmod_local),

.dtpa_local(dtpa_local),

.npg_cr(npg_cr),

.prg_pkt_cnt(prg_pkt_cnt),

.prg_pkt_size(prg_pkt_size),

.test_time(test_time),

.reset(reset),

.clk(clk)

);

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : host_if


//-------------------------------------------------------------------------//

module host_if (

input port_num,

input host_wr_rd_l,

109

input host_ce_l,




output reg [31:0] npg_cr,

output reg [26:0] prg_pkt_cnt,

output reg [15:0] prg_pkt_size,

output reg [3:0] test_time,

input reset,

input clk

);

wire host_access_wren = ~host_ce_l & host_wr_rd_l;

wire npg_cr_reg_wren = host_access_wren & (host_addr == {port_num, 31'd0});

wire prg_pkt_cnt_wren = host_access_wren & (host_addr == {port_num, 31'd1});

wire prg_pkt_size_wren = host_access_wren & (host_addr == {port_num, 31'd2});

wire test_time_size_wren = host_access_wren & (host_addr == {port_num, 31'd3});

always @(posedge clk or posedge reset)

if(reset)

begin

npg_cr <= 32'd0;

prg_pkt_cnt <= 27'd0;

110

prg_pkt_size <= 16'd0;

test_time <= 3'd0;

end

else begin

npg_cr <= npg_cr_reg_wren ? host_wr_data[31:0] : npg_cr;

prg_pkt_cnt <= prg_pkt_cnt_wren ? host_wr_data[27:0] : prg_pkt_cnt;

prg_pkt_size <= prg_pkt_size_wren ? host_wr_data[15:0] : prg_pkt_size;

test_time <= test_time_size_wren ? host_wr_data[3:0] : test_time;

end

assign host_rd_data = (host_addr == {port_num, 31'd0}) ? npg_cr :

(host_addr == {port_num, 31'd1}) ? {5'd0, prg_pkt_cnt} :

(host_addr == {port_num, 31'd2}) ? {16'd0, prg_pkt_size} :

(host_addr == {port_num, 31'd3}) ? {29'd0, test_time} : 32'd0;

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : pkt_gen


111

//-------------------------------------------------------------------------//

module pkt_gen(

output [31:0] tdat,

output reg tsop,

output reg teop,

output reg tenb,

output terr,

output tprty,

output [1:0] tmod,

input [31:0] npg_cr,

input [26:0] prg_pkt_cnt,

input [15:0] prg_pkt_size,

input [3:0] test_time,

input dtpa_local,

input reset,

input clk

);

parameter [2:0] IDLE = 3'h0;

parameter [2:0] L2H_SEND = 3'h1;

parameter [2:0] L3H_SEND = 3'h2;

parameter [2:0] L3DATA_SEND = 3'h3;

parameter [2:0] CRC_SEND = 3'h4;

parameter [2:0] EOP_SEND = 3'h5;

reg [2:0] pktgen_cs, pktgen_ns ;

112

reg tx_l2h;

reg tx_l2h_stage;

reg tx_l3h;

reg tx_l3h_stage;

reg tx_l3data;

reg tx_l3data_stage;

reg tx_l2crc;

reg [1:0] l2h_cnt;

reg [2:0] l3h_cnt;

reg [15:0] l3_pkt_size;

reg sop_send;

reg [1:0] l2_rdptr;

reg [2:0] l3_rdptr;

reg [31:0] default_l3_pkt[0:7];

reg [31:0] default_l2_pkt[0:3];

reg [15:0] l3_header_reg;

reg [1:0] start_pkt_gen_1q;

reg [26:0] pkt_cnt;

wire start_pkt_gen = npg_cr[0];

wire pkt_size_pre_prg = npg_cr[1];

wire number_of_pkts_prg = npg_cr[2];

wire en_rand_field = npg_cr[3];

wire [1:0] test_type = npg_cr[5:4];

wire gen_chksum_err = npg_cr[6];

113

wire gen_crc_err = npg_cr[7];

wire single_test = test_type[1:0] == 2'd0 | test_type[1:0] == 2'd3;

wire burst_test = test_type[1:0] == 2'd1;

wire cont_test = test_type[1:0] == 2'd2;

wire [3:0] rand_filed_sel = npg_cr[15:12];

wire sea_rand_en = en_rand_field & rand_filed_sel == 4'd1;

wire dea_rand_en = en_rand_field & rand_filed_sel == 4'd2;

wire type_ea_rand_en = en_rand_field & rand_filed_sel == 4'd3;

wire tos_rand_en = en_rand_field & rand_filed_sel == 4'd4;

wire total_length_rand_en = en_rand_field & rand_filed_sel == 4'd5;

wire id_rand_en = en_rand_field & rand_filed_sel == 4'd6;

wire flags_rand_en = en_rand_field & rand_filed_sel == 4'd7;

wire frag_offset_rand_en = en_rand_field & rand_filed_sel == 4'd8;

wire ttl_rand_en = en_rand_field & rand_filed_sel == 4'd9;

wire protocol_rand_en = en_rand_field & rand_filed_sel == 4'd10;

wire src_ip_rand_en = en_rand_field & rand_filed_sel == 4'd11;

wire dst_ip_rand_en = en_rand_field & rand_filed_sel == 4'd12;

reg [31:0] rand_fuction;


if(reset)

start_pkt_gen_1q <= 2'd0;

else

start_pkt_gen_1q <= {start_pkt_gen_1q[0], start_pkt_gen};

wire start_pkt_tx = start_pkt_gen_1q[0] & ~start_pkt_gen_1q[1];

114

wire load_pkt_cnt = start_pkt_gen & ~start_pkt_gen_1q[0];

wire [15:0] check_sum;

wire l2h_done = l2h_cnt == 2'h0;

wire l3h_done = l3h_cnt == 2'h0;

wire l3d_last = l3_pkt_size < 16'd4;

wire l3d_done = l3_pkt_size == 16'd0;

wire [31:0] l2_header = default_l2_pkt[l2_rdptr];

wire [31:0] l3_header = default_l3_pkt[l3_rdptr];

wire [31:0] l3_data = l3_pkt_size[2] ? 32'h9867_4321 : 32'hbaba_dada;

wire [31:0] CRC;

reg [31:0] crc_pipe;

wire l3h_b23_sel = (tx_l3h_stage & !l3h_done ) | (tx_l2h_stage & l2h_done );

wire l2h_b23_sel = (tx_l2h_stage & !l2h_done );

wire crc_b23_sel = (tx_l3data_stage & l3d_last );

wire chk_sum_sel = (tx_l3h_stage &l3_rdptr == 3'd2);

assign tdat[31:24] = crc_b23_sel ? CRC[15:8] : l2h_b23_sel ? l2_header[31:24] : chk_sum_sel ? check_sum[15:8] : l3h_b23_sel ? l3_header[15:8] : l3_data[15:8];

assign tdat[23:16] = crc_b23_sel ? CRC[7:0] : l2h_b23_sel ? l2_header[23:16] : chk_sum_sel ? check_sum[7:0] : l3h_b23_sel ? l3_header[7:0] : l3_data[7:0];

assign tdat[15:8] = tx_l2crc ? crc_pipe[31:24] : tx_l2h_stage? l2_header[15:8] : tx_l3h_stage? l3_header_reg[15:8] : l3_data[31:24];

assign tdat[7:0] = tx_l2crc ? crc_pipe[23:16] : tx_l2h_stage? l2_header[7:0] : tx_l3h_stage? l3_header_reg[7:0] : l3_data[23:16];

assign tmod = tx_l2crc ? 2'b10 : 2'b00;

always @ (pktgen_cs or start_pkt_tx or sop_send or l2h_done or l3h_done or l3d_last or dtpa_local or l3_pkt_size or l3d_done or pkt_cnt)

115

begin

pktgen_ns = pktgen_cs;

tenb = 1'd1;

teop = 1'd0;

tsop = 1'd0;

tx_l2h = 1'd0;

tx_l2h_stage = 1'd0;

tx_l3h = 1'd0;

tx_l3h_stage = 1'd0;

tx_l3data = 1'd0;

tx_l3data_stage = 1'd0;

tx_l2crc = 1'd0;

case(pktgen_cs)

IDLE: begin

if(start_pkt_tx & pkt_cnt > 0)

pktgen_ns = dtpa_local ? L2H_SEND : IDLE;

end

L2H_SEND: begin

tx_l2h_stage = 1'b1;

if(dtpa_local) begin

pktgen_ns = l2h_done ? L3H_SEND : L2H_SEND;

tsop = ~sop_send;

tenb = 1'b0;

tx_l2h = 1'b1;

116

end

end

L3H_SEND: begin

tx_l3h_stage = 1'b1;


pktgen_ns = l3h_done ? L3DATA_SEND : L3H_SEND;

tenb = 1'b0;

tx_l3h = 1'b1;

end

end

L3DATA_SEND: begin

tx_l3data_stage = 1'b1;


pktgen_ns = l3d_last ? CRC_SEND : L3DATA_SEND;

tenb = 1'b0;

tx_l3data = 1'b1;

end

end

CRC_SEND: begin


pktgen_ns = dtpa_local ? EOP_SEND : CRC_SEND;

tenb = 1'b0;

tx_l2crc = 1'b1;

teop = dtpa_local;

117

end

end

EOP_SEND: begin

pktgen_ns = (pkt_cnt > 0 ? L2H_SEND : IDLE);

end

default: pktgen_ns = IDLE;

endcase

end


if(reset)

pktgen_cs <= IDLE;

else

pktgen_cs <= pktgen_ns;

reg [15:0] rand_pkt_size;

wire [15:0] rand_pkt_size_pre = ({16{total_length_rand_en}} & rand_fuction[15:0]) ^ 16'd88;

wire [15:0] rand_pkt_size_pre2 = rand_pkt_size_pre > 3'd4 ? {rand_pkt_size_pre[15:2], 2'd0} : 16'd4;


if(reset)

begin

l2h_cnt <= 2'h3;

l3h_cnt <= 3'h4;

l3_pkt_size <= 16'd88;

118

sop_send <= 1'h0;

rand_pkt_size <= 16'd88;

end

else

begin

l2h_cnt <= tx_l2h ? l2h_cnt - 1'b1 : l2h_cnt;

l3h_cnt <= (tx_l3h & l3h_done) ? 3'h4 : tx_l3h ? l3h_cnt - 1'b1 : l3h_cnt;

l3_pkt_size <= tsop ? (pkt_size_pre_prg ? {prg_pkt_size[15:2], 2'd0} : total_length_rand_en ? rand_pkt_size_pre2 : 16'd88) :

(tx_l3h & l3h_done) ? ((l3_pkt_size > 16'd3) ? l3_pkt_size - 3'd2 : 16'd0) :

tx_l3data ? ((l3_pkt_size > 16'd3) ? l3_pkt_size - 3'd4 : 16'd0) : l3_pkt_size;

sop_send <= teop ? 1'h0 : tsop ? 1'b1 : sop_send;

rand_pkt_size <= sop_send ? l3_pkt_size : rand_pkt_size;

end


if(reset)

begin

l2_rdptr <= 2'h0;

l3_rdptr <= 3'h0;

end

else

begin

l2_rdptr <= tx_l2h ? l2_rdptr + 1'b1 : l2_rdptr;

l3_rdptr <= teop ? 3'h0 : (tx_l3h | tx_l2h & l2h_done) ? l3_rdptr + 1'b1 : l3_rdptr;

119

end

ìfdef LESS_PKT_CNT

wire [26:0] def_pkt_cnt = 27'd4;

èlse

wire [26:0] def_pkt_cnt = 27'd100_000;

èndif

wire [3:0] burst_mul = (burst_test ? 8 : 1);


if(reset)

pkt_cnt <= def_pkt_cnt;

else if (load_pkt_cnt)

pkt_cnt <= number_of_pkts_prg ? prg_pkt_cnt * burst_mul:

pkt_size_pre_prg ? def_pkt_cnt * burst_mul:

total_length_rand_en ? def_pkt_cnt * burst_mul:

(test_time +1) * def_pkt_cnt * burst_mul;

else if (start_pkt_gen & teop & pkt_cnt != 15'd0)

pkt_cnt <= cont_test ? pkt_cnt : pkt_cnt - 1'b1;

else if (!start_pkt_gen )

pkt_cnt <= 27'd0;


if(reset)

l3_header_reg <= 16'd0;

else

l3_header_reg <= (tx_l3h | tx_l2h & l2h_done) ? l3_header[31:16] :l3_header_reg ;

120

integer i, j;

reg [15:0] check_sum1;

wire [31:0] l3h_data;

assign l3h_data[31:24] = crc_b23_sel ? 8'd0 : l2h_b23_sel ? 8'd0 : l3h_b23_sel ? l3_header[15:8] : 8'd0;

assign l3h_data[23:16] = crc_b23_sel ? 8'd0 : l2h_b23_sel ? 8'd0 : l3h_b23_sel ? l3_header[7:0] : 8'd0;

assign l3h_data[15:8] = tx_l2crc ? 8'd0 : tx_l2h_stage? 8'd0 : tx_l3h_stage? l3_header_reg[15:8] : 8'd0;

assign l3h_data[7:0] = tx_l2crc ? 8'd0 : tx_l2h_stage? 8'd0 : tx_l3h_stage? l3_header_reg[7:0] : 8'd0;

wire [31:0] l3h_t3 = default_l3_pkt[3];

wire [31:0] l3h_t4 = default_l3_pkt[3];

wire [31:0] l3h2 = ({{8{protocol_rand_en}}, {8{ttl_rand_en}}, 16'd0} & rand_fuction + 1) ^{8'd2, 8'd6, 16'd0};

wire [31:0] l3h3 = ({32{src_ip_rand_en}} & (rand_fuction + 2)) ^ {1'b0, 7'd1, 24'd1};

wire [31:0] l3h4 = ({32{dst_ip_rand_en}} & (rand_fuction + 3)) ^ {1'b0, 7'd1, 24'd2};

wire [31:0] check_sum2 = l3h_data[16:0] + l3h_data[31:16] + (l3_rdptr == 3'd1 ? l3h2[31:16] + l3h3[16:0] + l3h3[31:16] + l3h4[16:0] + l3h4[31:16] : 0) + check_sum1;

wire [15:0] check_sum3 = check_sum2[15:0] + check_sum2[31:16];

assign check_sum = gen_chksum_err ? check_sum3 : ~check_sum3;


if(reset)

check_sum1 <= 32'd0;

else

check_sum1 <= teop ? 32'd0 : !tenb ? check_sum2 : check_sum1;

121

always @ (load_pkt_cnt or rand_fuction or tos_rand_en or rand_pkt_size or id_rand_en or flags_rand_en or frag_offset_rand_en or ttl_rand_en or protocol_rand_en or src_ip_rand_en or dst_ip_rand_en )

begin

default_l3_pkt[0] <= ({{16{1'b0}},{8{tos_rand_en }}, {8{1'd0 }}} & rand_fuction) ^ {rand_pkt_size, 8'd0, 4'd5, 4'd4};

default_l3_pkt[1] <= ({{13{frag_offset_rand_en}}, {3{flags_rand_en}}, {16{id_rand_en}}} & rand_fuction) ^ {13'd0, 3'd2, 16'd1};

default_l3_pkt[2] <= ({{8{protocol_rand_en}}, {8{ttl_rand_en}}, {16{1'b0 }}} & rand_fuction) ^ {8'd2, 8'd6, 16'd0};

default_l3_pkt[3] <= ({32{src_ip_rand_en}} & rand_fuction) ^ {1'b0, 7'd1, 24'd1};

default_l3_pkt[4] <= ({32{dst_ip_rand_en}} & rand_fuction) ^ {1'b0, 7'd1, 24'd2};

end

wire [31:0] l2_rnd_0 = sea_rand_en ? rand_fuction : 32'd0;

wire [31:0] l2_rnd_1 = {dea_rand_en ? rand_fuction[31:16] : 16'd0, sea_rand_en ? rand_fuction[15:0] : 16'd0};

wire [31:0] l2_rnd_2 = dea_rand_en ? rand_fuction : 32'd0;

wire [31:0] l2_rnd_3 = type_ea_rand_en? rand_fuction : 32'd0;

wire [31:0] l2_pkt_0 =l2_rnd_0 ^ {2{16'hf0e2}};

wire [31:0] l2_pkt_1 =l2_rnd_1 ^ {16'h0f2e, {16'hf0e2}};

wire [31:0] l2_pkt_2 =l2_rnd_2 ^ {2{16'hf0e2}};

wire [31:0] l2_pkt_3 =l2_rnd_3 ^ {16'd0, {16'h0011}};

always @ (load_pkt_cnt or l2_pkt_0 or l2_pkt_1 or l2_pkt_2 or l2_pkt_3 )

begin

default_l2_pkt[0] <= l2_pkt_0;

122




end


if(reset)

rand_fuction <= 32'ha59b_4fd7;

else

rand_fuction <= !tenb ? rand_fuction + 1'b1 : rand_fuction;

reg [31:0] cur_crc;

wire [31:0] crc_out;

wire [31:0] tdat_4_crc;

assign tdat_4_crc[31:24] = crc_b23_sel ? 8'd0 : l2h_b23_sel ? l2_header[31:24] : chk_sum_sel ? check_sum[15:8] : l3h_b23_sel ? l3_header[15:8] : l3_data[15:8];

assign tdat_4_crc[23:16] = crc_b23_sel ? 8'd0 : l2h_b23_sel ? l2_header[23:16] : chk_sum_sel ? check_sum[7:0] : l3h_b23_sel ? l3_header[7:0] : l3_data[7:0];

assign tdat_4_crc[15:8] = tx_l2crc ? 8'd0 : tx_l2h_stage? l2_header[15:8] : tx_l3h_stage? l3_header_reg[15:8] : l3_data[31:24];

assign tdat_4_crc[7:0] = tx_l2crc ? 8'd0 : tx_l2h_stage? l2_header[7:0] : tx_l3h_stage? l3_header_reg[7:0] : l3_data[23:16];

pkt_crc pkt_crc(.data(tdat_4_crc), .cur_crc(cur_crc), .crc_out(crc_out));


if(reset)

cur_crc <= {32{1'b1}};

else

123

cur_crc <= teop ? {32{1'b1}} : !tenb ? crc_out : cur_crc;

integer swap;

reg [31:0] swap_crc;

always @ (cur_crc) for (swap = 31; swap >= 0; swap = swap - 1) swap_crc[swap] = ~cur_crc[31- swap];

assign CRC = {swap_crc[7:0],

swap_crc[15:8],

swap_crc[23:16],

swap_crc[31:24]};


if(reset)

crc_pipe <= {32{1'b1}};

else

crc_pipe <= gen_crc_err ? ~CRC : CRC;

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : pkt_crc

124


//-------------------------------------------------------------------------//

module pkt_crc(

input [31:0] data,

input [31:0] cur_crc,

output [31:0] crc_out

);

wire [31:0] next_crc0;

















125
















crc_bit crc_bit00 (.data(data[ 0]), .cur_crc(cur_crc), .next_crc(next_crc0));

crc_bit crc_bit01 (.data(data[ 1]), .cur_crc(next_crc0), .next_crc(next_crc1));








126


crc_bit crc_bit10 (.data(data[10]), .cur_crc(next_crc9), .next_crc(next_crc10));






















assign crc_out = next_crc31;

127

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : crc_bit


//-------------------------------------------------------------------------//

module crc_bit(

input data,

input [31:0] cur_crc,

output [31:0] next_crc

);

wire [31:0] eth_crc_pol = 32'h04C11DB7;

reg [31:0] next_crc_int;

reg next_crc_b0;

wire crc_last_bit = cur_crc[31];

wire [31:0] cal_crc = {cur_crc[30:0], 1'b0};

always @ (cur_crc or data or eth_crc_pol or cal_crc)

begin

128

next_crc_int = (cur_crc[31] != data) ? eth_crc_pol ^ cal_crc :cal_crc;

next_crc_b0 = (cur_crc[31] != data) ? 1'b1 : cal_crc[0];

end

assign next_crc = {next_crc_int[31:1], next_crc_b0};

endmodule

//-------------------------------------------------------------------------//

//




//



// Module : mac_if


//-------------------------------------------------------------------------//

module mac_if(

output reg[31:0] tdat,

output reg tsop,

output reg teop,

output reg tenb,

output reg terr,

output reg tprty,

output reg[1:0] tmod,

129

input dtpa,

input [31:0] tdat_local,

input tsop_local,

input teop_local,

input tenb_local,

input terr_local,

input tprty_local,

input [1:0] tmod_local,

output reg dtpa_local,

input reset,

input clk

);


if(reset)

begin

tdat <= 32'd0;

tsop <= 1'd0;

teop <= 1'd0;

tenb <= 1'd1;

terr <= 1'd0;

tprty<= 1'd0;

tmod <= 2'd0;

dtpa_local <= 1'd0;

end

130

else

begin

tdat <= tdat_local;

tsop <= tsop_local;

teop <= teop_local;

tenb <= tenb_local;

terr <= terr_local;

tprty<= tprty_local;

tmod <= tmod_local;

dtpa_local <= dtpa;

end

endmodule

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