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Neuromorphic Computing with NanoCrossbar Circuits

Dmitri StrukovUniversity of California at Santa Barbara

Acknowledgments:

Research group: G. Adam, B. Chakrabarti, X. Guo, B. Hoskins, F. Merrikh Bayat, M. Prezioso

Collaborators: P. Auroux, J. Edwards, M. Graziano (BAE), I. Kataeva (DENSO), K. K. Likharev (SBU), N. Do (SST), L. Sengupta (NGC)

Funding support: AFOSR MURI, ARO, DARPA UPSIDE, DENSO CORP., NSF

1

NanoXbar Workshop, July 2016

2

RECENT SURGE OF A.I.(you could not avoid the buzz…)

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“OK, it's amazing right now with ISIS, I tell you what? I don't want them to vote, the worst very social people. I love me”


3

PATTERN CLASSIFICATION

IN CONVOLUTIONAL (A.K.A. “DEEP”) NETWORKS

Input

1@32x32

Layer 1

6@28x28

Layer 2

6@14x14

Layer 3

12@10x10Layer 4

12@5x5

Layer 5

100@1x1

10

5x5convolution

5x5convolution

5x5convolution2x2

pooling/sub-sampling

2x2pooling/sub-sampling

Layer 6: 10

- MLP with limited bio-inspired connectivity

- the best method for hand-writing recognition

- used by NCR for check reading machines

- used by Microsoft for OCR

- 0.62% error on the MNIST set

Y. LeCun (2007)

Example:

MNIST set (60,000-image database)


4

PATTERN CLASSIFICATION

IN CONVOLUTIONAL (A.K.A. “DEEP”) NETWORKS

Input

1@32x32

Layer 1

6@28x28

Layer 2

6@14x14

Layer 3

12@10x10Layer 4

12@5x5

Layer 5

100@1x1

10

5x5convolution

5x5convolution

5x5convolution2x2

pooling/sub-sampling

2x2pooling/sub-sampling

Layer 6: 10

- supervised error

backpropagation training

- weights determine functionality

- neurons learn “features”

- most computationally intensive

operation: dot product

- 4 to 5-bit synapses (weights)

accuracy sufficient

Y. LeCun (2007)

Example:


j

n

j

j xwo

1

]tanh[oy

inputs

weights

activation function

weighted sum

Single layer perceptron:

5

U. TORONTO’S NETWORK

- 650,000 neurons, 0.63109 synapses

- Image Net LSVRS-2010 benchmark set

- 1.2 M images; 1,000 classes

- error rates: top-1 37.5%, top-5 17%


Bottleneck: massive number of dot

product (vector-by-matrix) computations

between analog inputs and analog

(fixed) weights

Google’s Tensor Processing Unit

DIGITAL CIRCUITS FOR DEEP LEARNING

Movidius’s fanthom

15 inferences /sec @ 16-bit FP precision for ImageNet@ <2W

Nvidia’s Pascal

21 TFLOPS for deep learning performance

- Proposed by Carver Mead and his

students 25+ years ago

- Exact analog-domain dot-product due to

Ohm’s and Kirchhoff's law

- No need to waste energy on memory

bits movement (in-memory computing)

- Major challenge: adjustable cross-point

devices

- Two very promising recent options:

- Custom-built metal-oxide memristors

- Redesigned commercial NOR flash

- Other (not discussed) options: phase

change, ferroelectric, and magnetic

devices

7


ANALOG VECTOR-BY-MATRIX COMPUTATION

Strukov et al., DRC’16

MEMRISTORS

8

modulation of defect profile

electrolyte (ECM) metal oxide (VCM)

ON state

OFF state

redoxreaction

primary mechanism:

Pt

TiO2-x

Pt

Pt

Ag2S

Ag

-1.0 0 1.0

-1.0

0

1.0

Voltage (V)

Cu

rren

t (m

A) =

+Vswitch-Vswitch

Alibart et al., Nature Comm, 2013

S

S

A

V

Analog switching: Any state between ON and OFF Strongly (superexp) nonlinear switching dynamics Gray area = no change Memory state defined as current measured within gray area

25 nm Au / 15 nm Pt top electrode

5 nm Ti / 25 nm Pt bottom electrode

e-beam patterned Pt protrusion

30 nm TiO2-x

20 nm

Typical I-V for Pt/TiO2-x/Pt devices Two major types of memristors


0 1000 2000 3000

1E-5

1E-4

7A

120A

60A

30A

Curr

ent @

-200m

V (

A)

Pulse Number

15A

Increase WeightDecrease Weight

Stand-by (Read only)

2006 2007 2008 2009 2010 20111,000

100,000

1E7

1E9

1E11

1E13

Fujitsu Labs

Panasonic Corp.

SAIT

En

dru

an

ce

(cycle

s)

Year

HP Labs

several groups

Kawahara et al. Panasonic, 2012

Alibart et al, Nanotechnology 23 074508, 2012

Schindler, PhD Thesis, 2009

Govoreanu,et all IEDM, 2012

Strachan et al, Nanotechnology 22505402 2011

ON

OFF

Torrezan et al, Nanotechnology 22 485203 2011

J. Yang, DBS, and D. Stewart Nature Nano 8 13-24 (2013)

4) switching speed

2) endurance

5) retention 6) ON/OFFcurrent ratio

7) OFF stateresistance

8) I-V nonlinearity

3) reciprocal switching energy

10) density

1) reproducibility

9) number of states

memorylogicneuro

storage

demonstrated

9

STATE-OF-THE-ART PERFORMANCE


10

10 100

10

100

Aver

age

R (k

)

Setpoint R (k)

10 12 14 16 18 20 22

10

12

14

16

18

20

22

Avera

ge R

(k

)

Setpoint R (k)

Target resistance @ 0.1V (kΩ)10 100

100

10

222018161412

10

10 12 14 16 18 20 22

Ave

rage

res

ista

nce

@ 0

.1V

(kΩ

)

-2.0-1.5-1.0-0.5 0.0 0.5 1.0 1.5 2.0

-600

-500

-400

-300

-200

-100

0

100

200

300

Cu

rre

nt (

A)

Voltage (V)

Reset

SetForm

SiO2/Si

Pt (60 nm)

TiO2-x (30 nm)

Ti (15 nm)

Al2O3 (4 nm)

Ta (5 nm)

Pt (60 nm)

VW-

VRVW

+

Voltage (V)-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

300

200

100

0

-100

-200

-300

-400

-500

-600C

urr

ent

(μA

)

-1.5 -1.0 -0.5 0.0 0.5 1.00

5

10

15

Cou

nts

Threshold Voltage (V)

1.7 1.8 1.9 2.0 2.10

10

20

30

40

Cou

nts

Forming voltage (V)

0.3 0.4 0.5 0.60

5

10

15

Cou

nts

Conductance @0.1V (S)

Reset Set

Switching threshold voltage (V)

Forming voltage (V)

Conductance @ 0.1V (μS)

Co

un

tC

oun

tC

oun

t

15

10

5

0

40302010

0

15

10

5

0-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

1.7 1.8 1.9 2.0 2.1

0.3 0.4 0.5 0.6

Re

sis

tan

ce

@0

.1V

(Ω

)

105

104

Time (s)0 20 40 60 80 100 120 140 160 180

Major features

- 0T1R- 200 nm wide lines - Al2O3 and TiO2-x by

sputtering - Very uniform (~17%)

norm. RMS of [email protected] for 8x10 virgin array

- >500K stress pulses without much degradation

PASSIVE MEMRISTIVE CROSSBAR CIRCUIT Crossbar circuit

2 μm

Typical I-Vs Statisticsas

fabricated

forming

switching threshold

Analog properties and state tuning

M. Prezioso et al., Nature May 2015 M. Prezioso et al., IEDM’15NanoXbar Workshop, July 2016

CLASSIFIER OPERATION (INFERENCE)

- Neurons functionality (opamp) is emulated in software- Differential pair of memristors per weight

differential pair

A A A A

V1

V2

V10

G1,1+ G1,1

-

G1,2+ G1,2

-

G1,10+ G1,10

-

G3,1+ G3,1

-

G3,2+ G3,2

-

G3,10+ G3,10

-

bias

pattern (“z”)

V=

I1+ I1

- I2+ I2

- I3+ I3

-

+VR

-VR

-VR

+VR

+VR

+VR

-VR

-VR

+VR

-VR

11


M. Prezioso et al., Nature May 2015M. Prezioso et al., IEDM’15

Σ

V10

V1

V2

bias

input

neurons

output neurons

V1 V4 V7

V2 V5 V8

V3 V6 V9

V10

3×3 binary

image

W1,1

W3,10

𝑓1Σ

weights

Σ 𝑓3

𝐼1

𝐼3𝑓2

𝐼2

CLASSIFIER IN-SITU TRAINING (WEIGHT UPDATE)

differential pair

A A A A

V1

V2

V10

G1,1+ G1,1

-

G1,2+ G1,2

-

G1,10+ G1,10

-

G3,1+ G3,1

-

G3,2+ G3,2

-

G3,10+ G3,10

-

Analog vector-by-matrix multiplier

- Half-biasing technique- One column at a time (fully parallel

possible with stochastic training mode)

- Neurons functionality (opamp) is emulated in software- Differential pair of memristors per weight

bias

pattern (“z”)

V=

I1+ I1

- I2+ I2

- I3+ I3

-

+VR

-VR

-VR

+VR

+VR

+VR

-VR

-VR

+VR

-VR

step 1: set G+

step 2: reset G+

step 3: reset G-

step 4: set G-

0 0 0 00

0

0

0

0

0

0 0 0 00

-VW+/2

00

0

0

0

-VW+/2

-VW+/2

-VW+/2

-VW+/2

+VW+/2

+VW+/2

+VW+/2

+VW+/2

+VW+/2

-VW+/2

+VW+/2

sgn[ΔW]=

calculate

fi (n) =

calculate

𝐼𝑖(n) =

calculateset

n = 1

Δij = 0

desired class fi(g)(n)

last patter

n?

no

yes

update

weights

Vj(n)

n = n +1

next epoch

end of

epoch

no

last patter

n?

yesupdate

weights

n = n +1

stochastic

batch

J

j

jijVW1

iItanh

nVnn jiij

)(

)(

nIIi

i

g

iidI

dfnfnfn

training set:

𝑉𝑗 𝑛 , 𝑓𝑖(g)(𝑛)𝑛=1

𝑁

initializeWij

sgn[ΔW]=

sgn[δi(n)Vj (n)]0

0

00

0

0 00

0

00

0

0

0 00

-VW+/2

-VW+/2

-VW+/2

-VW+/2

-VW+/2

+VW+/2+VW

+/2+VW+/2

+VW+/2

+VW+/2

+VW+/2

+VW+/2

+VW+/2

-VW+/2 -VW

+/2-VW+/2

Weight updatestochastic

batch

12


M. Prezioso et al., Nature May 2015M. Prezioso et al., IEDM’15

EXPERIMENTAL RESULTS

0

20

40

60

80

100

0 10 20 30 40 5005

1015202530

Test set

26% misclassification

# m

iscla

ssifie

d p

attern

s

Training set

Epoch

Batch Manhattan rule in-situ training:

Trained on the original training set

Test set formed by flipping two pixels

Perfect classification for multiple runs on training set

Perfect classification on test set hardly possible (e.g. see pattern highlighted with red)

Classification performance (batch)

… test sets

znv

Batch training and …

z

v

n

13M. Prezioso et al., Nature May 2015M. Prezioso et al., IEDM’15 NanoXbar Workshop, July 2016

OVERCOMING NONLINEAR SWITCHING KINETICS

NanoXbar Workshop, July 2016 14

+log[V1(n)]

-log[δ1(n)]

0

0

-log[V1(n)]

0

0 +log[δ2(n)]

+log[V2(n)]

0

0

-log[V2(n)]

0

0-log[δ2(n)] +log[δ1(n)]

step 1 step 2

step 3 step 4

-2 -1 0 1 2 3

-1

-0.5

0

0.5

1

x 10-3

Voltage (V)

Current

(A

)

Experimental Data

Dynamic Model

Dynamic & Static Models

MODELING OF LARGE-SCALE CLASSIFIERS

I. Kataeva et al., IJCNN’15, M. Prezioso et al., IEDM’15

Main result: Comparable to the state-of-the-art classification performance for MNIST, GTSRB, and CIFAR benchmarks when using accurate models of hardware

Mis

cla

ssific

ation r

ate

Ratio of stuck devices (%)0 10 20 30 40 50 60 70 80 90 100

300-hidden-neuron MLP, variable-amplitude for in-situ training

Error rate is normalized with respect to the best software results (see table above)

2 1 0.4 0.2 0.1 0.04 0.02 0.01

100

10-1

10-2

10-3

3.0

2.5

2.0

1.5

1.0

0.5Norm

aliz

ed m

iscla

ssific

ation r

ate

Normalized STD for weight import (%)

~ 8 bit weight import precision

Dataset

Software Xbarin-situ (var. ampl.)

Xbarex-situ 2%

Xbarex-situ 0.2%

best average best average best average best averageMNIST 0.40 0.47±0.05 0.4 0.48±0.024 0.61 0.89±0.22 0.41 0.42±0.01GTSRB 1.36 1.53±0.18 1.26 1.56±0.27 1.42 1.56±01 1.46 1.47±0.01

CIFAR10 15.63 15.91±0.22 15.67 15.87±0.22 19.77 20.29±0.43 15.5 15.8±0.01

Experimentally-verified memristor device models

F. Merrikh Bayat et al., Applied Physics A, 2015

Classification performance results for large-scale deep learning convolutional neural networks

Performance sensitivity to defects and ex-situ training precision

15


16

CMOS/NANO HYBRIDS: THE IDEA

bottom nanowire level

top

nanowire level

similar

two-terminal

nanodevices

(“memristors”)

at each

crosspoint

WHAT:

• CMOS stack + simple nanoelectronic add-on

• nanowire / memristor crossbar

WHY:

• CMOS functionality and infrastructure intact

• potentially inexpensive fabrication

add-on

CMOSstack


17

DrainSource

Control Gate

Interpoly

DrainSource

Control Gate

DrainSource

Floating Gate

Control Gatedielectric

Gate

oxide

NVM (“FLASH”) MEMORY TECHNOLOGY

FG

CG

FG

CG

Channel

Channel Channel


18

NVM CELLS FOR ANALOG APPLICATIONS

J. Hasler and B. Marr (2013)

Example: “extended drain” NMOS structure

Hasler’s group at Georgia Tech (http://www-old.me.gatech.edu/mist/gokce.htm)

(from late 1990s: C. Mead, C. Diorio, P. Hasler,…)


NanoXbar Workshop, July 2016 19

bit line bit line

shared source line

word line 1 word line 2

common substrate

S

GG

D D

SILICON STORAGE TECHNOLOGY, INC. (SST): ESF1

0 0.2 0.4 0.6 0.8 10

20

40

60

|VDS

(V)|

|ID

S(

A)|

Fully Erased, VS=0, V

D=swept

Fully Erased, VD=0, V

S=swept

0 1 2 3 4 51E-13

1E-11

1E-9

1E-7

1E-5

VG

(V)|I

DS(A

)|

Fully Erased,VDS

=1V

Fully Erased,VDS

=-1V

Fully Programmed,VDS

=1V

Fully Programmed,VDS

=-1V

(a)

(b) VG=4V

3.5V

3.0V

2.5V

2.0V

1.5V

1.0V

Output current as a function of applied voltages:

F. Merrikh-Bayat et al. (2015)NanoXbar Workshop, July 2016

20

FLASH ARRAY REDESIGN FOR ANALOG APPLICATIONS

VSE = 0V

half-selected cell (type D)

3.8

4μ

m

1.36μm

3.8

4μ

m

3.12μm

VGE

0V

VDE0V 0V

VSE’

0V

VGE = 11V

0V

0V

0V

0V

VDE=0V VD

E ’

half-selected cell (type C)

selected cell

VDP=0V

VSP = 7.6V

0V

VDP ’ > 2V

VGP = 1.6V

0V

0V

selected cell half-selected cell (type A)

half-selected cells (type B)

VGP

VSP

0VVGP’

0V

0V

selected cell selected cellhalf-selected cells (type B)

half-selected cell (type E)

VGP’ = 0V

VGP’

Old array:

New array:

“program” “erase”

“program” “erase”

F. Merrikh-Bayat et al. (2015)<100F2 area per synapse


21

0 20 40 60 80 1000.95

1

1.05

Read Pulse Number

Cu

rre

nt

(nA

)

0 20 40 60 80 1000.99

0.995

1

1.005

1.01

Read Pulse Number

Cu

rre

nt

( A

)

0 100 200 300 400 500 600 700 800 900

1E-9

1E-8

1E-7

1E-6

Pulse Number

Cu

rre

nt

(A)

TUNING (OF EACH CELL!) TO PRE-SET VALUES

F. Merrikh-Bayat et al. (2015)NanoXbar Workshop, July 2016

22

-1 -0.5 0 0.5 1 -0.1

-0.05

0

0.05

0.1

inI

inI

outI

outI

2ini

2ini

Vdd

w1+

w1-

w1-

w1+

ddV

Ibias = 500 nA

Vdd = 1V

w1+ ≈ 10-5

Iout+ - Iout

- = (w1+ - w1

-)(Iin+ - Iin

- )

I ou

t+-

I ou

t-(µ

A)

Iin+ - Iin

- (µA)

-1 -0.5 0 0.5 1-0.115

-0.11

-0.105

-0.1

-0.095

-0.09

-0.085

Iin

+-I

in

- (A)

Slo

pe

VECTOR-BY-MATRIX MULTIPLIER (VMM) DEMO

VMM linearity:

F. Merrikh-Bayat et al. (2015)

Transfer to a better NVM 2D technology would bring

synapse area well below ~ 1 μm2.


SPIKING NEURAL NETWORKS

23

-60 -40 -20 0 20 40 60-100

-75

-50

-25

0

25

50

75

100

W

(

)

t(ms)

-60 -40 -20 0 20 40 60

-1.0

-0.5

0.0

0.5THRESHOLD

Min

Max

Vo

lta

ge

(V

)

t (ms)

RESET

THRESHOLD

SET

0 20 40 60

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

Vo

lta

ge

(V

)

t (ms)

Pre

Post

- Richer functionality (spatial

and temporal processing) and

better energy efficiency of

spiking networks as compared

to firing rate

- Local (Hebbian) training

more efficient hardware

- Essential feature to

demonstrate: Spike-timing

dependent plasticity (STDP)

Motivation Experimental demonstration of STDP

- Three STDP windows

demonstrated using crossbar

- The most accurate STDP

demonstration to date

no

n128in

n2in

n1in

𝐺0

𝐺1

𝐺128

𝑆1in(𝑡)

𝑆2in(𝑡)

𝑆128in (𝑡)

nd

𝑆o(𝑡)

𝑆d(𝑡)

teacher

output leaky

integrate-and-

fire neuron

input

neurons

synapses

time

G𝑆d(𝑡)𝑆in(𝑡)

𝑡d − 𝑡in

time

G𝑆𝑜(𝑡)𝑆in(𝑡)

𝑊o

𝑡o − 𝑡in

0 50 100 150 200

Time (ms)

0 5 10 15 20 25 30

128

96

64

32

15

10

5

01.5

1.0

0.5

0

2015 10 50

Epoch #Pe

rfo

rma

nce

index

Neuro

n

pote

ntialE

poch #

Neuro

n #

𝑆in

𝑆d

𝑆o

threshold

STD/mean

10

5

0

<P

erf

orm

ance i

ndex>

CombinedDevice-to-deviceCycle-to-cycle Initial state

no spiking

1000 training

epochs

STD/mean

<P

erf

orm

ance i

ndex>

50100 -50 0 50

-50

0

50

100

150

200

t (ms)W (S)

W

(%

)Δ

G(%

)

Δt (ms)

2040

6080

100

-50

-25

0

25

50

75

100

125

150

175

200

-60 -40 -20 0 20 40 60

100 S

75 S

50 S

25 S

W

(%

)

t (ms)

Weight (S)

ΔG

(%)

,GtG

,0,1tanh

,0,1tanh

tctba

tctba

tt

tt

t

.0 ,tanh1

,0,tanh1

0

0

tcGb

tcGb

GG

GG

G

Experimentally-verified analytical model STDP

Simulation of memristor-based spiking neural networks

M.Prezioso et al., Nature Scientific Report, 2016

M. Prezioso et al., ISCAS 2016NanoXbar Workshop, July 2016

24


SUMMARY

Emerging nonvolatile memories enable (for the first time?) efficient analog neural network implementations and could challenge human brain in energy efficiency and speed Experimental demonstration of key hardware block for both memristor

and flash-based artificial neural networks Small scale demonstrations of firing-rate feedforward/recurrent and

spiking memristor-based artificial neural networks with comparable to state-of-the-art functional performance for large scale NVM-based networks via simulation with data-verified device models

Estimated >100x / >1000x improvement in energy efficiency as compared to ASICs for flash / memristor based implementations

Need industry involvement to develop large-scale memristor circuit no such issue with flash memory–based circuit

Strukov et al., DRC’16

THANK YOU!

[email protected]

25NanoXbar Workshop, July 2016

SELECTED RECENT PUBLICATIONS

26


• F. Merrikh-Bayat, X. Guo, M. Klachko, N. Do, K. Likharev, and D. Strukov, “Model-based high-precision tuning of NOR flash memory cells for analog computing applications”, to appear in Device Research Conference (DRC’16), Newark, DE, June 2016 (NOR flash)

• M. Prezioso, Y. Zhong, D. Gavrilov, F. Merrikh Bayat, B. Hoskins, G. Adam, K.K. Likharev, and D.B. Strukov, “Spiking Neuromorphic Networks with Metal-Oxide Memristors”, to appear in International Symposium on Circuits and Systems (ISCAS'16), Montreal, Canada, May 2016 (Memristor spiking neural networks)

• M. Prezioso, F. Merrikh Bayat, B. Hoskins, K. Likharev, and D. Strukov, "Self-adaptive spike-time-dependent plasticity of metal-oxide memristors", Nature Scientific Reports 6, art. 21331, Jan. 2016. (Memristor spiking neural networks)

• F. Merrikh Bayat, M. Prezioso, X. Guo, B. Hoskins, D.B. Strukov, and K.K. Likharev, "Memory technologies for neural networks", in: Proc. IMW'15, Monterey, CA, May 2015, pp. 1-4. (brief review)

• F. Merrikh Bayat, X. Guo, H.A. Om'mani, N. Do, K.K. Likharev, and D.B. Strukov, "Redesigning commercial floating-gate memory for analog computing applications", in: Proc. ISCAS'15, Lisbon, Portugal, May 2015, pp. 1921-1924. (NOR flash)

• M. Prezioso, F. Merrikh Bayat, B.D. Hoskins, G.C. Adam, K.K. Likharev, and D.B. Strukov, "Training and operation of an integrated neuromorphic network based on metal-oxide memristors", Nature 521, pp. 61-64, May 2015. (Memristor firing-rate MLP networks)

• X. Guo, F. Merrikh-Bayat, L. Gao, B. D. Hoskins, F. Alibart, B. Linares-Barranco, L. Theogarajan, C. Teuscher, and D.B. Strukov, "Modeling and experimental demonstration of a Hopfield network analog-to-digital converter with hybrid CMOS/memristor circuits", Frontiers in Neuroscience 9, art. 488, Dec. 2015. (Memristor recurrent networks)

• F. Merrikh Bayat, B. Hoskins, and D.B. Strukov, "Phenomenological modeling of memristive devices", Applied Physics A 118 (3), pp. 770-786, 2015. (Memristor model)

• M. Prezioso, I. Kataeva, F. Merrikh-Bayat, B. Hoskins, G. Adam, T. Sota, K. Likharev, and D. Strukov, "Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2-x/Pt memristors", IEDM'15, Dec. 2015. (Memristor firing-rate MLP networks)

• M. Payvand, A. Madhavan, M. Lastras-Montaño, A. Ghofrani, J. Rofeh, K.-T. Cheng, D. Strukov, L. Theogarajan, "A configurable CMOS memory platform for 3D-integrated memristors", in: Proc. ISCAS'15, Lisbon, Portugal, May 2015, pp. 1378-1381. (Memristor integration)

• I. Kataeva, F. Merrikh Bayat, E. Zamanidoost, and D.B. Strukov, "Efficient training algorithms for neural networks based on memristive crossbar circuits", in: Proc. IJCNN'15, Killarney, Ireland, July 2015, pp. 1-8. (Memristor firing-rate MLP networks modeling)

• F. Alibart, E. Zamanidoost, and D.B. Strukov, "Pattern classification by memristive crossbar circuits with ex-situ and in-situ training", Nature Communications 4, art. 2072, 2013 (Memristor firing-rate MLP networks)

• J.J. Yang, D.B. Strukov and D.R. Stewart, “Memristive devices for computing”, Nature Nanotechnology 8, pp. 13-24, 2013 (review)

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