The Phase-1 Upgrade of the ATLAS Level-1 Endcap Muon TriggerShunichi Akatsuka (Kyoto University, Japan) on behalf of the ATLAS Collaboration

RealTime 2018 @Williamsburg, 9th-15th June, 2018

Introduction◆ LHC Run 3: 2021~ 2023 ‣ √s = 14 TeV, instantaneous luminosity will be 3.0 × 1034 cm-2s-1

+50 % compared to Run 2 luminosity of ~2.0 × 1034 cm-2s-1 ‣ Integrated luminosity estimated to be ~150 fb-1 → Run 2 + Run 3 = 300 fb-1

◆ ATLAS Trigger System - basic scheme will remain the same in Run 3

◆ Phase-1 Upgrade for Level-1 Muon Trigger ‣ With Run 2 trigger algorithm, the rate for muon trigger with pT > 20 GeV (L1_MU20)

will become 30 kHz @ 3.0×1034 cm-2s-1 ‣ Run 3 requirement at this luminosity is 15 kHz (TDAQ TDR, ATLAS-TDR-023) ‣ More powerful trigger strategy is needed to reduce the trigger rate,

while keeping the trigger threshold and the efficiency

2

From Detector

Level-1 trigger

High Level Trigger

~ 40 MHz ~100 kHz, within 2.5 μs

~1 kHz, within a few sec.

Data Recorded

Fixed latency, Hardware-based trigger

L1 Muon Trigger in Run 2◆ Run 2 Level-1 muon trigger rate is dominated by:

① Triggers with no matching real muons (Fake triggers) ② Triggers by Low pT muons especially in |η| > 1 region (Endcap region).→ Strategy: Reject these triggers by introducing new “coincidence logic”

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rejected by Tile coincidenceexpected distribution at the end of Run 2

offline reconstructed muons 20 GeV≥

Toffline p

ATLAS Preliminary

muons with pT over threshold

①①

② ②

L1 Muon Endcap Trigger in Run 3 4

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Figure 2: Schematic side view of the ATLAS muon spectrometer depicting the naming andnumbering scheme; top: sector with large chambers; bottom: sector with small chambers.

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Figure 2: Schematic side view of the ATLAS muon spectrometer depicting the naming andnumbering scheme; top: sector with large chambers; bottom: sector with small chambers.

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η=2.4

η=1.0

η=1.3

TGC Big WheelNew Small Wheel

real

Tile Calorimeter

fake

EI RPC BIS 7/8

◆ Run 3 Trigger scheme overview ‣ TGC BW hit position defines the RoI, which will be the trigger seed. ‣ TGC Big Wheel local dR/dPhi coincidence logic calculates the pT of the track. ‣ Require additional inner coincidence to reject fakes, and also to re-calculate the pT

I.P.

zdRdΦ

Φ

R

dΦ

dR

Toroidal Field

pT = ∞

muon track

M1

M2M3

z = 13

z = 14z = 14.5

z = 7

Detectors Inside the

Magnetic Field

Online hardware triggering◆ Main idea of the trigger logic: ‣ dR, dφ defined as the hit position difference between M1and M3 ‣ dR, dφ are handed over to a Look-Up-Table,

which immediately returns the trigger decision and the candidate’s pT ‣ Similar logic to take coincidence with detectors inside to reject fake/low-pT muons→ New LUT for the Inner Coincidence is needed for additional fake and low-pT rejection

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1 1 1 1 2 2 2

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2

1 1 1 1 1 1 1 1 1 2 2 2 2 2 2

1 1 1 1 1 1 1 1 1 2 2 2 2 2 21 1 1 1 1 1 1 1 1 2 2 2 2 2 11 1 1 1 1 1 1 1 2 2 2 3 3 1 11 1 1 1 1 1 1 1 2 2 3 3 2 1 11 1 1 1 1 1 1 3 3 3 3 3 2 2 11 1 1 1 1 1 1 3 3 3 3 3 3 1 11 1 1 1 1 1 1 3 3 4 4 4 1 1 11 1 1 1 1 1 4 4 5 5 5 4 1 1 11 1 1 1 1 4 5 5 5 6 5 4 1 1 11 1 1 1 1 1 5 5 6 6 5 5 3 1 11 1 1 1 1 6 6 6 6 6 6 3 1 1 11 1 1 1 1 6 6 6 6 6 6 1 1 1 11 1 1 1 6 6 6 6 6 6 6 1 1 1 11 1 1 1 6 6 6 6 6 6 6 1 1 1 11 1 1 1 6 6 6 6 6 6 6 1 1 1 11 1 1 1 6 6 6 6 6 6 6 1 1 1 11 1 1 4 5 5 5 6 6 5 1 1 1 1 11 1 1 4 4 5 5 5 5 5 1 1 1 1 11 1 1 4 3 4 4 5 5 5 1 1 1 1 11 1 1 3 4 3 4 4 5 5 1 1 1 1 11 1 1 3 3 3 3 3 3 3 1 1 1 1 1

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φ∆

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example of Look-Up Table

What sort of LUTs can effectively

reduce fake/low-pT ?

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Inner Coincidence Logic (1)◆ Position matching ‣ Matching between TGC BW and Inner station hit position. ‣ Fake triggers can be rejected dramatically ‣ Low-pT muons can also be rejected (with enough granularity at inner station)

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7 m 13 m 14.5 m

Toroidal Magnetic Field

pT = ∞

NSW

TGC BW

M1

M3

High pT

calorimeter

Big Wheel dR has coarser granularity

NSW dη has finer granularity

Low pT

η�（

NSW

）�-

η (

BW

) NSW BW

dΦ dΦ

dR

Inner Coincidence Logic (2)◆ Angle matching ‣ Angle information at the inner station can be used to

further reject the low-pT triggers. ‣ Combine position and angle to tag muons with large incident angle

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7 m 13 m 14.5 m

Low pT

pT = ∞

NSW

TGC BW

M1

M3

High pT

multiple scattering

calorimeter

coarser granularity

dη cannot distinguish

combining dη and dθ can distinguish

IP ~ 10 cm

Toroidal Magnetic Field

dθ

straight line from detector center

muon track

dθ definition

NSW

Trigger performance studies (1)◆ Fake rejection power estimation ‣ Fakes cannot be modeled in MC, so we used 2017 data for the estimation. ‣ MDT segments are used to emulate NSW, by smearing its position and angles

resolution to NSW resolution for the Level-1 trigger ‣ ~90% fake triggers are rejected with η- and (rough) phi- position coincidence

◆ Low-pT rejection power estimation ‣ Single muon MC is used to estimate low-pT rejection for NSW and RPC BIS7/8. ‣ Low-pT candidates are rejected effectively: -50% @10 GeV, -85% @5 GeV

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[GeV]muonT

Offline p0 5 10 15 20 25 30 35 40

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02000400060008000

1000012000140001600018000

Phase I upgrade study = 13 TeV, 25 nssData

| < 2.4RoIη1.3 < |

ATLAS Preliminary

Run-2 (BW + FI))φ:dηBW + NSW(d

)θ:dη & dφ:dηBW + NSW(d

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20 GeV≥ T

offline p

ATLAS Preliminary

Trigger performance studies (2)◆ Fake rejection power estimation ‣ Fakes cannot be modeled in MC, so we used 2017 data for the estimation. ‣ MDT segments are used to emulate NSW, by smearing its position and angles

resolution to NSW resolution for the Level-1 trigger ‣ ~90% fake triggers are rejected with η- and (rough) phi- position coincidence

◆ Low-pT rejection power estimation ‣ Single muon MC is used to estimate low-pT rejection for NSW and RPC BIS7/8. ‣ Low-pT candidates are rejected effectively: -50% @10 GeV, -85% @5 GeV

◆ Rate reduction and efficiency ‣ Rate reduction

Run 2 extrapolation: 30 kHz Run 3 14.2 kHz (~53% rate reduction)

‣ Efficiency~ 95% for muons with pT > 20 GeV,relative to Run2 trigger(assuming NSW segment finding efficiency 97%)

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20 GeV≥ T

offline p

ATLAS Preliminary

L1 Muon Trigger implementationTGC Big Wheel New Small WheelBW1 BW2 BW3

New Trigger Processor

ηNSW : 8 bitsφNSW : 6 bitsdθ : 5 bits

flag, spare : 5 bits

Same as Run 2; 202-bit /25 ns ~8 Gbps

( ηBW, φBW )

muon

IP

( dR, dφ )

Trigger data to Central

Trigger Processor

vector information

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dθ( ηNSW, φNSW )

max. 24 track candidates/ 25 ns

576 bit/ 25ns, ~23 Gbps

New Sector Logic

Tile, TGC EI, RPC BIS 7/8

Other detectors:

New Sector Logic Board design 11

New Sector Logic Board design 12

Optical interfaces to use GTX transceiver* at 6.4 Gbps

12 lanes × 6.4 Gbps = 76.8 Gbps for NSW and Tile, BIS7/8 **

Optical interfaces for G-Link connection at 0.8 Gbps 14 × 0.8 Gbps = 11.2 Gbps

for TGC BW and EI

795 × 36 Kb Block RAM → × 20 times the resource compared to the FPGA for the current trigger board

* GTX: multi-gigabit transceivers for Xilinx Kintex-7 FPGAs [Link] ** For Tile, we actually use 1.6 Gbps × 2 lanes

Xilinx Kintex-7 XC7K410T

Firmware design for Fixed Latency 13

optical fibers

sync. to LHC clock, but with different phase fiber-by-fiber

Firmware design for Fixed Latency 14

optical fibers

sync. to LHC clock, but with different phase fiber-by-fiber

LHC 40 MHz clock

Trigger decision

Align to same clock domain

◆ Trigger decision part ‣ Maximum 16 inner station candidates will be given for 1 BW trigger seed ‣ Regardless of the number of candidates, we need the trigger decision in

a fixed (and small) latency. What can we do? -> Try taking coincidence with all 16 candidates, choose the best one among them

‣ In a simple implementation, this requires 16 times the latency, or 16 same LUTs, which is not realistic in terms of latency/resource on FPGA.-> Use a faster clock to re-use the same LUT while keeping the latency small

‣

Firmware design for Fixed Latency 15

BW trigger seed pos. & pT

NSW candidates’ pos. & angle

0 to max. 16 candidates

LUT pT re-calc. selector

LUT pT re-calc. selector

All within 2 × 40 MHz clock 40 MHz320 MHz

Final pT

8-to-1 selection 2-to-1Schematic diagram

Test results◆ Firmware logic test for trigger part ‣ Simulation test for trigger part, on Vivado software (Xilinx compiler, Link) ‣ Shown below is an example of very simple test, where: ‣ 1 LUT is implemented to process 8 candidates one-by-one, on 320 MHz clock. ‣ The LUT simply returns least-significant 3 bits of the input address.

‣ Other tests are successfully done with different input patterns,not only on simulation but also on the actual SL board.

‣ Tests using more realistic LUTs (created from MC data), is ongoing.

16

input

40 MHz

320 MHz

Test results◆ Firmware logic test for trigger part ‣ Simulation test for trigger part, on Vivado software (Xilinx compiler, Link) ‣ Shown below is an example of very simple test, where: ‣ 1 LUT is implemented to process 8 candidates one-by-one, on 320 MHz clock. ‣ The LUT simply returns least-significant 3 bits of the input address.

‣ Other tests are successfully done with different input patterns,not only on simulation but also on the actual SL board.

‣ Tests using more realistic LUTs (created from MC data), is ongoing.

17

processing 8 NSW candidates one-by-one

Final pT Back to 40 MHz domain

40 MHz

320 MHzoutput

40 MHz

Summary◆ Upgrade of the muon trigger system is essential for Run 3: ‣ The main strategy is to take coincidence with NSW and other detectors,

to reject fake and low pT muons. ‣ New hardware is needed to combine data from current trigger chamber BW, NSW,

and several other detectors.

◆ Trigger Logic and Performance ‣ Taking position matching and angle matching between BW and NSW can reject low

pT muon candidates effectively. ‣ The estimated rate is 14.2 kHz @ L = 3.0×1034 cm-2s-1,

which meets the Run3 requirement of 15 kHz. (ATLAS-TDR-023)

◆ Hardware and Firmware development ‣ New trigger processor board, New Sector Logic, has been produced for Run3. ‣ Firmware is fully-designed with all the trigger LUTs implemented. ‣ Fast clock is used in the trigger logic to overcome the latency limitation

while keeping the FPGA resource usage reasonable.

18

backup slides

Physics Motivation◆ Run 3 trigger rate estimation

‣ Without the phase-1 upgrade, to keep the trigger rate to the require level, the pT threshold will need to be raised to ~40 GeV.

20

◆ Physics Acceptance

◆ If the threshold is raised to 40 GeV,the efficiency for muons from the decays of W boson produced in association with Higgs will be 61%.

threshold [GeV]T

p5 10 15 20 25 30 35 40 45

Muo

n le

vel-1

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ger r

ate

[Hz]

410

510

610= 14 TeVs -1s-2 cm34 10×L=3

Extrapolationwith 2012-run settingExtrapolationwith Pre-phase1Extrapolationwith Pre-phase1 + NSW

ATLAS

15 kHz

New Small Wheel◆ Consists of sTGC and Micromegas ‣ sTGC: small strip TGC ‣ TGC chamber with strip width of 3.2mm, smaller than the strip width of current TGC (> 15 mm)

‣ 4 wire-strip pairs are combined to make 1 module. ‣ position resolution 60~150 μm

‣ Micromegas: micro mesh gaseous structure ‣ position resolution ~90 μm ‣ 8 layers are sandwiched by sTGC 4-layer modules,to compose the New Small Wheel

21

sTGC 4 layers

Micromegas 8 layers

sTGC 4 layers

~22 cm~36 cm

Resolution: position ~30 μm angle ~0.3 mrad.

NSW Technical Design Report, ATLAS-TDR-020

Region of Interest◆ The smallest unit for the Level-1 Muon Trigger: ‣ Each side is divided into 72 parts, shown as green line in this figure → 72 ‘Sectors’ per side, 48 × Endcap sectors and 24 × Forward sectors

‣ Each Endcap (Forward) sector is divided into 148 (64) ‘Regions of Interest’ = RoI

‣ One Endcap (Forward) SL board handles 2 Sectors, i.e. 296 RoIs (128 RoIs)

‣ Trigger decision is performed RoI by RoI → 296 trigger decision logic should run in parallel on a single FPGA → 296 different LUTs need be implemented

22

Trigg

er S

ecto

r

2.5

2.0

1.5

η = 1.0

4 4 4 RoI = 16 x 4 = 6416

RoI = 37 x 4 = 148

RoIΔφ = 0.1

44 4 4 4

4

37

coverage per Endcap SL

coverage per Forward SL

New Sector Logic Board design 23

FPGA (Xilinx Kintex-7 XCK410T)

CPLD (XC2C256-7PQ208C) for VME control

BPI (PC28F256P30TF) for FPGA configuration

14 optical inputs (800 Mbps) from BW-TGC SFP RX + G-Link RX chip

RJ45 connector for readout (SiTCP)

LEMO IN/OUT

16-pin connector to receive trigger/ timing information

6 optical inputs for other detectors SFP+ with GTX RX

6 optical inputs (6.4 Gbps) from NSW SFP+ with GTX RX in FPGA

2 optical outputs (6.4 Gbps) to MUCTPI SFP+ with GTX TX

Input Data Format (1)◆ TGC BW ‣ G-LINK 16 or 17 bits/BC per fiber ‣ Endcap: 12 fibers per Sector Logic, 202 bits/BC ‣ Forward: 6 fibers per Sector Logic, 100 bits/BC

◆ TGC EI ‣ G-LINK 16 bits/BC per fiber ‣ Endcap only, 2 fibers per SL, 32 bits/BC

◆ New Small Wheel ‣ GTX 6.4 Gbps (= 128 bit/BC, with 8B/10B) per fiber ‣ Endcap: 6 fibers per SL, 768 bit/BC ‣ Forward: 8 fibers per SL, 1024 bit/BC

24

) (-452-452-452-452-452-452-452-452

31762 3 489 3

65013 6501365013 6501365013 65013

65013 6501365013 6501365013 65013

17550 . 17550 .

ATLAS Phase-I UpgradeLevel-1 Endcap Muon Trigger

Full Design ReportDraft 0.5, March 7, 2018 21:59

Data format, connection and protocol Sector Logic receives both position (⌘, �) and angle272

information (d✓) of the track from the NSW trigger processor. These information are calculated273

separately on sTGCs and MicroMegas local trigger processor, and are merged by the NSW274

trigger processors. The expected resolution, range, and the assigned bit width for each of the275

variables are summarized in Table 2. In addition to these variables, NSW trigger processor are276

expected to send some flag bits for sTGC and MM track qualities. The track information arepacked into 24 bits, as shown in Figure 3.277

Table 2: Resolution and bit assignment

variable resolution range for 1 NSW sector range/ resolution assigned bit width⌘ 0.005 1.2(1.3 ⇠ 2.5) 240 8 bits (256 patterns)� 10 mrad. 2⇡/12(2⇡/24) rad. 52.3 (26.2) 6 bits (64 patterns)d✓ 1 mrad. 32 mrad. (�15 ⇠ 15 mrad.) 32 5-bit (32 patterns)

Table 3: Bit assignment for one NSW track. Track information are encoded into 24 bits.

Bit Assigned information7-0 ⌘[7 : 0]13-8 �[5 : 0]

18-14 �✓[4 : 0]20-19 MM type22-21 sTGC type

23 spare

The data transfer from NSW trigger processor to the Sector Logic is performed throughoptical serial connections. The Xilinx GTX transceiver, which is one of Multi-Gigabit Transceiver278

(MGT) technology, is adopted as the serial-parallel interface. GTX enables the data transfer279

rate of maximum 12.5 Gb/s [8]. The most popular SFP+ optics are directly supported by the280

transceiver. The optical links will be operated with bit rate of 6.4 Gb/s, synchronous with the281

LHC bunch crossing clock provided from CTP via TTC systems. 8b/10b encoding are used for282

the data transfer, therefore 128-bit data per fibre can be transferred every BC. The data formatis shown in Figure 9. Sector Logic can receive 4 track candidate per fibre, every BC.283

) (-452-452-452-452-452-452-452-452

31762 3 489 3

65013 6501365013 6501365013 65013

65013 6501365013 6501365013 65013

17550 . 17550 .

Figure 9: Data format for data from NSW per BC, received using 1 fibre. 4 track candidate with24-bit information can be received.

In order to cover boundaries of NSW sectors by a Sector Logic, as shown in Figure 8, track

10 2 Physics Algorithm

Input Data Format (2)◆ Tile Cal. ‣ GTX 1.6 Gbps (= 32 bits/BC with 8B/10B) per fiber ‣ Endcap only, 1 fiber per SL

◆ RPC BIS 7/8 ‣ GTX 6.4 Gbps (= 128 bits/BC with 8B/10B) per fiber ‣ Endcap only, 1 fiber per SL

25

( ) (H[] &)H[] &*

78>9K,3)L) A[ ,K+3)L

9 G .NL 0D KL .NL

FF 3 ( A[ +K+3)L A[ *K+3)L A[ )K+3)L 8NOXRK*3)L

GA97K,3)L

) (563563563563563563563563

76124 076124 0

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17550 . 17550 .

76124 076124 076124 076124 076124 0

76124 076124 076124 076124 076124 0

0- 0

ATLAS Phase-I UpgradeLevel-1 Endcap Muon Trigger

Full Design ReportDraft 0.5, March 7, 2018 21:59

) (563563563563563563563563

76124 076124 0

31762 3 489 3

17550 . 17550 .

76124 076124 076124 076124 076124 0

76124 076124 076124 076124 076124 0

0- 0

Figure 14: Format for data from RPC BIS 7/8. 6.4 Gbps GTX.

Table 7: Bit assignment for RPC BIS 7/8 trac candidate. ⌘, � are the track position, and d⌘, d�are the track segment angle. 2/3 flag shows whether the track candidate passed 3-out-of-3 or2-out-of-3 locacl coincidence. 2 bits are assigned to this flag to show which 2 layers (layers 1-2,1-3 or 2-3) are used to calculate the position/angle of the track.

Bit Assigned information5-0 ⌘[5 : 0]11-6 �[5 : 0]

14-12 d⌘[2 : 0]17-15 d�[2 : 0]19-18 2/3 flag[1:0]23-20 spare

Secotr Logic will be connected to MUCTPI.343

Data format, connection and protocol Data format to MUCTPI board is well described in344

a document at MUCTPI PDR [9]. The number of muon candidate per sector will increase in345

Phase-I upgrade of MUCTPI. For each LHC bunch crossing, every Sector Logic will send four346

muon candidate information to MUCTPI. A specificpT value indicates if it is an empty candidate347

to be ignored by MUCTPI. The muon candidate will be ordered in terms of the pT-threshold348

value, the first muon candidate being the one with the highest pT-threshold value. 6.4 Gbps349

GTX protocol will be used for connection between the Sector Logic and the MUCTPI. The dataformat is shown in Figure 15, and the content of each track information is shown in Table 8.350

6BC6BC6BC6BC6BC6BC (6BC )6BC

10 54 234 54

4 B .9 9D 7 (4 B .9 9D 7 (4 B .9 9D 7 (

.5.7 F0 3

4 B .9 9D 7 (1 B:9 9 7 -.2 7

F-. 3 ( F.( ( ) F.( ( ) F.( ( )

Figure 15: Format for data to MUCTPI, per trigger sector. Up to four candidates will be sent,each muon candidate will have 16-bit data width.

16 2 Physics Algorithm

Output Data Format◆ Output to Muon-to-CTP Interface (MUCPTI) ‣ GTX 6.4 Gbps (= 128 bits/BC with 8B/10B) per fiber ‣ 1 fiber per trigger sector, 2 fibers per SL board ‣ Commas are sent at the end to gain latency.

26

6BC6BC6BC6BC6BC6BC (6BC )6BC

10 54 234 54

4 B .9 9D 7 (4 B .9 9D 7 (4 B .9 9D 7 (

.5.7 F0 3

4 B .9 9D 7 (1 B:9 9 7 -.2 7

F-. 3 ( F.( ( ) F.( ( ) F.( ( ) ATLAS Phase-I Upgrade

Level-1 Endcap Muon TriggerFull Design Report

Draft 0.5, March 7, 2018 21:59

Table 8: Muon candidate data format. 16 bits are assigned for each muon candidate. 8 bits areused to indicate the RoI of the candidate, 4 bits for the pT value, and 4 bits for other flags. 1 bitof the flag bits are used to indicate the sign of the muon candidate’s charge. The other flag bitscan be used for inner coincidence debug signals, during the commissioning period.

Bit Assigned Data7-0 RoI

11-8 pT value12 Candidate sign

15-13 NSW/Inner Coincidence flags

2.3 Algorithms in the Sector Logic351

In this section, the algorithm that will be implemented on the new SL is explained. A brief352

block diagram of the endcap Sector Logic trigger algorithm is shown in Figure 16. The Sector353

Logic algorithm can be divided into several sub-modules. The Decoder part receives the data354

and translates the data into position/ track information, and provide them to the downstream355

logics. TGC Big-Wheel coincidence part receives the dR and d� information of the TGC BW, to356

take dR - d� coincidence. Inner coincidence part receives the information of the inside-magnet357

detectors such as NSW, to take BW - Inner coincidence. The Track Selection part selects up358

to 4 track candidates, and the output data is sent to the MUCTPI. The implementation of thetrigger logic on the firmware will be discussed in detail at Section 4.359

2.3.1 Decoder360

The Decoder module retrieves �R and �� information from the TGC BW signal received viaG-LINK.361

The Decoder module converts raw data of tracks into the format of BW-Inner Coincidenceand ditribute to each logic.362

2.3.2 TGC Big Wheel coincidence363

The Sector Logic uses LUTs for the R–� coincidence of TGC Big wheel, where the �R in-364

formation with �� information from the HPT boards is combined to get pT information of the365

muon track. To implement LUTs in FPGA embedded memory (Block RAM; BRAM), one sector366

is divided into small blocks called Sub-Sector-Cluster (SSC). Figure 17 shows one SSC which367

consists of 8 ROIs (2 rows of wire by 4 columns of strips). Thanks to the specification of HPT368

board coincidence, one SSC includes a maximum of only one hit in R and two hits in �. Hit369

information is 19 bits in total and is used as the LUT address. The output of the TGC-BW R–�coincidence logic will be the pT of the track candidates in 4-bit resolution.370

2.3.3 Inner coincidence371

The main idea of the inner coincidence is simple: when the TGC Big Wheel finds a trigger372

candidate, confirm the decision by requiring hit in detectors inside the magnetic field. The373

simplest way to implement this algorithm is to require hit at approriate position in the inner374

detector (position matching). As shown in Fig. 18, the position matching algorithm will not only375

2.3 Algorithms in the Sector Logic 17

[GeV]muonT

Offline p0 5 10 15 20 25 30 35 40

Rel

ativ

e ef

ficie

ncy

0

0.2

0.4

0.6

0.8

1

Run-2 (BW + FI))φ:dηBW + NSW(d

)θ:dη & dφ:dηBW + NSW(d

Phase I upgrade study| < 2.4RoIη1.3 < |

ATLAS Simulation Preliminary

‣ New Inner LUTs uses NSW position & angle information ‣ Efficiency is calculated by simulation, for L1_MU20(L1_MU20: Level-1 trigger for muon with pT > 20 GeV)

‣ The track finding efficiency is assumed to be 97%

Trigger Performance 27

Efficiency > 95% for pT > 20 GeVSharper curve

acquired with new LUT

◆ Data reception Clock-Domain-Crossing part ‣ choose a phrase of 40 MHz to latch the received data, so that they will have enough

margin from the data transition point:

Firmware design for Fixed Latency 28

128-bit word

received data (phase unknown)

LHC 40 MHz

+ π/2

+ π

+ 3π/2use this phase to latch data

data transition

quite a lot of margin

less margin

Run 3 Readout system

SROD on PC‣Event Building ‣Formatting for ROS ‣Error handling

10GbE Switch‣ N-to-1 connection

‣Hit information ‣event ID

TTC Fan-out board

‣event ID ‣Trigger Information

Read Out System

S-LINK Card

GbE 10 GbE

GbE

(Trigger, Timing & Control)

New Sector Logic

TTC

SiTCP

SiTCP

SiTCP

TTCrq

… × 12

29

SiTCP[*] : Technology to connect FPGA to the Ethernet, and establish connection via TCP/IP

[*] Tomohisa Uchida, “Hardware-Based TCP Processor for Gigabit Ethernet”, IEEE Trans. Nucl. Sci. Vol.55, No.3, June 2008, [LINK]