nextgenio flyer for sc15
TRANSCRIPT
Next Generation I/O Solutions for the Exascale
Come and speak to us at SC15!Many of the NEXTGenIO project partners are
represented at SC15, so please stop by our
booths and talk to us about the work we do:
• EPCC: #2503
• Intel: #1333,1533
• Fujitsu: #1827
• TUD: #1351
• BSC: #241
• Allinea: #1722
www.nextgenio.eu
NEXTGenIO has received funding from the European Union’s Horizon2020 Research and Innovation programme under Grant Agreement no. 671951.
@nextgenio
The problemToday most high-end HPC systems employ data storage separate from the main computer system. The I/O subsystem often struggles to deal with the degree of parallelism present simply because too many processors are trying to communicate with the slow disk storage at once. The result is poor I/O performance, which impacts application runtimes and thus science throughput.
As we move into the domain of extreme parallelism at the Exascale, we need to address the I/O bottleneck challenge if such systems are to deliver acceptable performance and efficiency for their application user communities.
The NEXTGenIO solutionThe NEXTGenIO project will explore the use of Intel’s 3D XPointTM technology and associated systemware developments through a co-design process with three end-user partners: a high-end academic HPC service provider, a global numerical weather centre and a commercial on-demand HPC service provider. A key output of NEXTGenIO will be a prototype system built by Intel and Fujitsu, based on the new technologies.
NEXTGenIO will also develop an I/O workload simulator to allow improvements in performance to be directly measured on the new system in a range of research configurations. Systemware developed in the project will include performance analysis tools, advanced schedulers that take into account data locality and energy efficiency, optimised programming models, and APIs and drivers for optimal use of the new I/O hierarchy.
NEXTGenIO detailsThe NEXTGenIO project started on the 1st October 2015 and is set to run for 3 years.
NEXTGenIO is coordinated by EPCC, the supercomputing centre at the University of Edinburgh.
The NEXTGenIO project was awarded €8.1m by the European Commission as part of its Horizon2020 FETHPC programme.
For more information, please contactProf Mark Parsons, NEXTGenIO Project Coordinator <[email protected]>
Dr Michèle Weiland, NEXTGenIO Project Manager <[email protected]>
671591&NEXTGenIO& Part&B& 7&
However,&even&if&we&can&execute&an&application&on&extreme¶llel&systems&at&the&Exascale,&we&still&need&to&be&
able&to&read&the&executable&application&and&its&data&into&the&system&and&write&the&results&(and&any&intermediate&
checkpoint&data)&out&of&the&system.&As&we&discuss&further&below,&what&is&rarely&acknowledged&is&that&as&core_counts&
have&increased&the&performance&of&I/O&subsystems&have&struggled&to&keep&up&with&computational&performance&and&
have,&over&the&past&few&years,&become&a&key&bottleneck&on&today’s&largest&systems.&Indeed,&Gene&Amdahl,&famous&
for&Amdahl’s&Law,&also&developed&three&additional&“laws”&[AMDAHL]3&the&most&interesting&of&which&calculates&the&
ratio&of&the&number&of&bits&of&sequential&I/O&per&second&capable&of&being&delivered&to&the&processor÷d&by&the&
number& of& instructions& per& second& (see& [AMDAHL]).& For& a&well_balanced& computer& focussed& on& data& intensive&
applications,&Amdahl& argued& that& empirical& evidence& suggested& this& “Amdahl&Number”& should&be& close& to&one.&
Unfortunately,&for&today’s&HPC&systems&this&number&is&O(10_5)&[SZALAY].&Figure&1&shows&the&latency&gaps&between&
the&different&memory&and&storage&levels&on¤t&HPC&systems&–&the&gap&between&DRAM&and&spinning&disks&is&
particularly&dramatic.&
&
At&the&Exascale,&the&performance&demands&of&such&high&levels&of¶llelism&(likely&to&be&of&the&order&of&100_500&
million&computational&threads)&require&massive&increases&in&bandwidth&and&I/O&intensity,&whilst&at&the&same&time&
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&3&References&are&given&in&Appendix&1&at&the&end&of&the&second&part&of&this&document.&
HPC systems today HPC systems of the future
CPU
Memory NVRAM
Spinning storage disk
Register
Cache
Memory & Storage Latency Gaps
Storage tape
1x
100,000x
10x
10x
10,000x
DRAM
Storage SSD
CPU
Register
Cache
1x
10x
10x
DRAM
Spinning storage disk
Storage disk - MAID
Storage tape
10x
100x
100x
1,000x
10x
socket socket
socket
socket
socket
socket
DIMM
DIMM
DIMM
IO
IO
backup
IO
backupbackup
Figure(1:(Memory(and(storage(latency(gaps,(comparing(today's(HPC(systems(and(potential(future(system(architectures.(