ngwe soe zin, andrew blakers australian national university centre of sustainable energy system evan...
TRANSCRIPT
Ngwe Soe Zin, Andrew Blakers
Australian National Australian National UniversityUniversityCentre of Sustainable Energy SystemCentre of Sustainable Energy System
Evan Franklin, Vernie Everett
Purpose of the work Background of the Project Silicon Solar Cells for VHESC program
• Cell Design• Design Considerations• Target Efficiency• Modelling and Characterisation• Metal Plating• IV Test Data• Characterisation of Recombination• Conclusion
Ultra-High efficiency solar cell devices are a major step forward in the development of low-cost PV technology
Commercial applications, energy security, green house gas reductions, industry development
Military applications, pollution reduction
Potential trigger to revolutionise global electricity generation
Solar cell efficiencies are approaching their practical efficiency limits
Single junction: 25% eff. in Si or GaAs (85% of practical efficiency)
Tandem: 38% for 3-stack underconcentration (70% of practical efficiency)
Very High Efficiency Solar Cell (VHESC) program works towards six-junction tandem solar cell stack approach
VHESC integrates optics, interconnects, and cell designs
Benefits: Increased “design space” Increased theoretical efficiency Introduces options for new architectures Greater device design flexibility Reduced spectral mismatch losses Increased materials choices
VHESC cells will be used in the mobile battery charging application
High Eg 2.40 eV
GaInP 1.80 eV
GaAs 1.43 eV
Si 1.12 eV
0.95 eV
0.70 eV
14.9%
16.6%
13.9%
9.7%
5.0%
4.1%
13.8%
14.3%
11.7%
7.8%
3.8%
2.9%
13.8%
14.3%
12.0%
8.5%
4.0%
3.0%
6J Solar Cell Band Gap
Thermodynamic Efficiency
Practical Efficiency Limit
Practical Efficiency Limit
6-junction Solar Cell at 20 X 100 X
Totalη = 64.2%
Totalη = 54.3%
Totalη = 55.6%
IE
EE
Bar
nett
et a
l 200
6
Der
atin
g of
th
erm
odyn
amic
eff
icie
ncy
2.5 mm
0.3 mm
0.15 mm
0.5 mm
5.5 mm
0.75 mm 0.75 mm6.5 mm
1.9 mm
0.3 mm
Emitter Region (n+)
Base Region (p)
Metal Contact
• Bifacial Cell• N Contact at the Front• P Contact at the Back
1. Illumination• Light of energy <1.42eV to Silicon• Light of energy <1.1eV to underlying
cells• BSR not an option• Cell thickness should be 0.5-2mm for
reasonable conversion efficiency for 875-1100nm
2. Recombination• Thermal oxidation for Surface
Recombination• Cutting cells individually from the
host wafer for Edge Recombination• Contact is <1% of total surface area
for Contact Recombination
3. Anti-Reflection• Optimisation of oxide and nitride
thickness to reduce reflection loss of i. 1% in air ii. 3% under encapsulation
4. IQE• Diffusion length >> Cell thickness
for more than 90% IQE
5. Resistive Losses• 500µm thick cell will absorb 87% of
the light (875-1100nm) in the top half of the cell
• Current sharing in bifacial cell will minimise resistive losses partially
• Electron current at the rear of diffused emitter will be small
6. Lateral Diffusive Losses• Electron resistive loss is more
concerned than that of hole since Rs of 500µm 1Ωcm << Rs of Emitter Diffusion
• For estimated resistive loss of <5%, n++ contacts will be at both edges and ends of the cell (similar configuration for p++ contacts)
1.9mm
2/72.0 cmW
1.9 mm
-
+
2/0.2 cmW
GaInP/GaAs
High Eg Cell
Silicon
Input Power Before Silicon Material (875-1100nm)
=
Target Efficiency =
=
5.2%
5.2% =
Output Power of Cell
Isc x Voc x FF==6mA x 630mV x 78%
Input Power Before High Band-Gap Materials
Modelled Current-Voltage for 2.5x6mm Silicon Solar Cell
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Voltage(mV)
Cu
rren
t(m
A)
Modelled IQE for 2.5x6mm Silicon Solar Cell
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900 1000 1100 1200
Wavelength(nm)
Per
cen
t(%
)
Main Parameters Used for Modelling• Active Area for 15mm• Illumination at 1 sun intensity• Bifacial Emitter as Active Region• Heavy Phosphorous and Boron Diffusions
Isc Voc IQE (800-1000nm)
4.17mA 630mV up to 90%
QSSPC technique was used to characterise effective carrier lifetime and emitter saturation current.
Carrier lifetime after all high temperature step was maintained at around 560µs (~ implied-Voc of 640mV)
Surface recombination was also remained low at around 25 fA/sq cm
metallisation of small contact with dimension of 200µm x 5.5mm
evaporated metal contacting method needs
Fabrication of selective mask with opening only to contacts can tedious
Alignment of mask to contact can be error-prone Misalignment can cause shading loss and
shunting
Light-induced plating for n++ contacts
Electrolyte plating for p+ contacts
Both plating performed concurrently
Optical Microscope Measurement
n++ Contact
p+ ContactLight-Induced Plating
~1µm/min at 120V
Electrolyte ~1µm/min for 0.05A and 0.03V
Assuming the conditions:• Current generated by light enters in the
emitter equally• Current enters the metal bus bar from one
end and extracted from the other end
Power Loss (%)
AFM
Rate of Plating
Silicon Etch
Laser Scribe
TMAH Etch RCA Clean
LPCVD
Si
Etch for n+
Si
SiNn+
Diffusion
n+
n+
Strip SiN
n+
n+
Oxidation & LPCVD
n+
Etch for n++
n+
n+
Diffusion
n+
n+
Oxidation
n+
n+
Etch for p+
n+
n+
Diffusion
n+
n+
n+
n+
Oxide RemovalMetallisation
n+
n+
#31-A10-S1-Portion#3-Cell02
-5.00E-03
0.00E+00
5.00E-03
1.00E-02
1.50E-02
2.00E-02
2.50E-02
3.00E-02
-3.00E-01 -2.00E-01 -1.00E-01 0.00E+00 1.00E-01 2.00E-01 3.00E-01 4.00E-01 5.00E-01 6.00E-01 7.00E-01 8.00E-01
Voltage (mV)
Cur
rent
(mA
)
Dicing
#31-A10-S1-Portion#3-Cell02
-5.00E-03
0.00E+00
5.00E-03
1.00E-02
1.50E-02
2.00E-02
2.50E-02
3.00E-02
-3.00E-01 -2.00E-01 -1.00E-01 0.00E+00 1.00E-01 2.00E-01 3.00E-01 4.00E-01 5.00E-01 6.00E-01 7.00E-01 8.00E-01
Voltage (mV)
Cur
rent
(mA
)
#31-A10-S1-Portion#3-Cell05
-5.00E-03
0.00E+00
5.00E-03
1.00E-02
1.50E-02
2.00E-02
2.50E-02
-3.00E-01 -2.00E-01 -1.00E-01 0.00E+00 1.00E-01 2.00E-01 3.00E-01 4.00E-01 5.00E-01 6.00E-01 7.00E-01 8.00E-01
Voltage (mV)
Cur
rent
(mA
)
Intensity Voc(mV) Isc(mA) FF (%)Cell01 565 3.4 70Cell02 566 3.36 75Cell05 569 3.38 79
Tested by flash-tester under 1 sun illumination Demonstrates the absence of shunt and good fill-factor Low Voc and Isc could be due to recombination at the emitter and cell edge (cells diced out of
host wafer) Recombination due to cell edge unlikely since active region is at least 1mm away from cell edge
Recombination at the emitter region is suspected Experiment on dielectric using as etch mask and diffusion barrier
1st Group of Wafer 2nd Group of Wafer1 Grow Nitride Grow Oxide2 Measure Lifetime Measure Lifetime3 Strip Nitride in HF Strip Oxide in HF4 Cleaved Wafers Cleaved Wafers5 Diffusion Diffusion6 Grow Oxide Grow Oxide7 Grow Nitride Grow Nitride8 Measure Lifetime Measure Lifetime
1st Group of Wafer1 Grow Oxide2 Measure Lifetime3 RIE4 Cleaved Wafers5 Diffusion6 Grow Oxide7 Grow Nitride8 Measure Lifetime
Experiment on dry etching (RIE) if it has impact on lifetime Results were compared against the earlier results
Samples deposited with nitride as etch mask or diffusion mask results in low lifetime compared to oxide
Implied Voc was also observed lower for Sample using nitride as a etch mask
Using nitride directly on top of silicon as etch mask or diffusion barrier may induce stress and thermal mismatch
Samples etched by RIE to form emitter region has suffered drastic lifetime loss among all samples
Ion damage caused by RIE on the silicon causes lifetime loss significantly
Cells fabricated present the absence of shunting and good fill-factor
Low Voc and Isc for cells
Possible factors causing low Voc and Isc were identified
Subsequent batch of cell fabrication could increase the cell efficiency sharply
