nmo sp mos characteristics

Ceferino Kevin A. Tan BSECE - 4 September 24, 2015

Step 1

Connect the nMOS and pMOS as shown in figure 1.2(a). Simulate the Ids-Vgs characteristic curve as in figures 1.2(b)-(c).

nMOS

CODE

nmos_tan1.lib 'C:\synopsys\rf018.l' TT

m1 g g 0 0 nch l=0.18u w=0.60uvgs g 0 .7213041.op.dc vgs 0 1 0.001.probe i1(m1)

.end

LISTING FILE .OP OUTPUT

subckt element 0:m1 model 0:nch.12 region Saturati id 32.9995u ibs -8.675e-21 ibd -15.1293f vgs 721.3041m vds 721.3041m vbs 0. vth 541.4210m vdsat 148.3134m

vod 179.8831m beta 1.9143m gam eff 969.4764m gm 234.9491u gds 8.5681u gmb 67.1965u cdtot 796.9544a cgtot 1.0469f cstot 1.5677f cbtot 1.5445f cgs 729.1400a cgd 216.7042a

Figure 1 Ids-Vgs graph for the nMOS with channel width 0.6µ and length 0.18µ in the given setup. We can achieve a drain current equivalent to 33µA when the gate-source voltage is close to 0.721V.


pMOS

CODE

pmos_tan1

.lib 'C:\synopsys\rf018.l' TT

m1 g g 0 0 pch l=0.18u w=2.4uvgs g 0 -.72

.op

.dc vgs -1 0 0.001

.probe i1(m1)

.endLISTING FILE .OP OUTPUT

subckt element 0:m1 model 0:pch.8 region Saturati id -33.2241u ibs 5.398e-21 ibd 7.1680a vgs -720.0000m vds -720.0000m vbs 0. vth -508.2986m

vdsat -191.9895m vod -211.7014m beta 1.2565m gam eff 663.8051m gm 251.6020u gds 7.9359u gmb 85.1659u cdtot 3.0644f cgtot 4.0869f cstot 6.3123f cbtot 6.0030f cgs 3.1344f cgd 776.6167a

Figure 2 Ids-Vgs graph for the pMOS with channel width 0.24µ and length 0.18µ in the given setup. We can achieve a drain current equivalent to -33µA when the gate-source voltage is close to -0.72V.


Step 2

Disconnect the gate and drain of the MOS of figure 1.2(a). Then assign different values of Vgs to its gate terminal. Simulate the Ids-Vgs characteristic curve as in figure 1.3(a)-(b).nMOS

CODE

nmos_tan2.lib 'C:\synopsys\rf018.l' TT

m1 d g 0 0 nch l=.18u w=.6u

vgs g 0 0.7vdd d 0 1.47.op.dc vdd 0 5 0.001.probe i1(m1).altervgs g 0 0.9.alter vgs g 0 0.8

.altervgs g 0 0.6.altervgs g 0 0.5.end


subckt element 0:m1 model 0:nch.12 region Saturati id 33.0223u ibs -8.681e-21 ibd -3.2499n vgs 700.0000m

vds 1.4700 vbs 0. vth 539.2926m vdsat 139.8795m vod 160.7074m beta 1.9179m gam eff 969.4764m gm 245.2458u gds 5.9861u gmb 68.2022u cdtot 725.2631a cgtot 1.0422f cstot 1.5586f cbtot 1.4728f cgs 719.8199a cgd 216.6093a

Figure 3 Ids-Vds graph for the nMOS with channel width 0.6µ and length 0.18µ in the given setup. The Vgs

values(in volts) for each curve are 0.9, 0.8, 0.7, 0.6, 0.5 (top to bottom). The black(middle) curve is our curve for when Vds = 1.47V.


pMOS

CODE

pmos_tan2


m1 d g 0 0 pch l=.18u w=2.4uvgs g 0 -.7vdd d 0 -1.61.op.dc vdd -5 0 0.001.probe i1(m1)

.altervgs g 0 -0.9.alter vgs g 0 -0.8

.altervgs g 0 -0.6.altervgs g 0 -0.5.end


subckt element 0:m1 model 0:pch.8 region Saturati id -32.9872u ibs 5.360e-21 ibd 41.8342p vgs -700.0000m vds -1.6100

vbs 0. vth -504.2928m vdsat -181.5771m vod -195.7072m beta 1.2606m gam eff 663.8051m gm 264.0577u gds 4.3941u gmb 87.2154u cdtot 2.6987f cgtot 4.0720f cstot 6.2832f cbtot 5.6397f cgs 3.1011f cgd 776.1626a

Figure 4 Ids-Vds graph for the pMOS with channel width 2.4µ and length 0.18µ in the given setup. The Vgs

values(in volts) for each curve are -0.9, -0.8, -0.7, -0.6, -0.5 (bottom to top). The black(middle) curve is our curve for when Vds = -1.61V.


Step 3Follow step 2, change the channel length. Simulate the Ids-Vds characteristic curve as in figure 1.4(a)-(b).

nMOS

CODEnmos_tan3


m1 d g 0 0 nch l=.18u w=.6uvgs g 0 0.7vdd d 0 1.47.op.dc vdd 0 5 0.001.probe i1(m1)

.alterm1 d g 0 0 nch l=0.38u w=.6u.alter m1 d g 0 0 nch l=0.33u w=.6u

.alterm1 d g 0 0 nch l=0.28u w=.6u.alterm1 d g 0 0 nch l=0.23u w=.6u.end


subckt element 0:m1 model 0:nch.12 region Saturati id 33.0223u ibs -8.681e-21 ibd -3.2499n vgs 700.0000m

vds 1.4700 vbs 0. vth 539.2926m vdsat 139.8795m vod 160.7074m beta 1.9179m gam eff 969.4764m gm 245.2458u gds 5.9861u gmb 68.2022u cdtot 725.2631a cgtot 1.0422f cstot 1.5586f cbtot 1.4728f cgs 719.8199a cgd 216.6093a

Figure 5 Ids-Vds graph for the nMOS with channel width 0.6µ and length 0.18µ operating in the saturation region. The channel length values(in micrometers) for each curve are 0.18, 0.23, 0.28, 0.33, 0.38 (top to

bottom). The black(top) curve is our curve for when Vds = 1.47V.


pMOS

CODE

pmos_tan3.lib 'C:\synopsys\rf018.l' TT

m1 d g 0 0 pch l=.18u w=2.4uvgs g 0 -.7vdd d 0 -1.61.op.dc vdd -5 0 0.001.probe i1(m1)

.alterm1 d g 0 0 pch l=0.38u w=2.4u.alter m1 d g 0 0 pch l=0.33u w=2.4u

.alterm1 d g 0 0 pch l=0.28u w=2.4u.alterm1 d g 0 0 pch l=0.23u w=2.4u.end


subckt element 0:m1 model 0:pch.8 region Saturati id -32.9872u ibs 5.360e-21 ibd 41.8342p vgs -700.0000m

vds -1.6100 vbs 0. vth -504.2928m vdsat -181.5771m vod -195.7072m beta 1.2606m gam eff 663.8051m gm 264.0577u gds 4.3941u gmb 87.2154u cdtot 2.6987f cgtot 4.0720f cstot 6.2832f cbtot 5.6397f cgs 3.1011f cgd 776.1626a

Figure 6 Ids-Vds graph for the pMOS with channel width 2.4µ and length 0.18µ operating in the saturation region. The channel length values(in micrometers) for each curve are 0.38, 0.33, 0.28, 0.23, 0.18(top to

bottom). The black(top) curve is our curve for when Vds = -1.61V.


Step 4Set |Vgs| to a value smaller than |Vt| to operate the MOS in subthreshold region. Simulate the Ids-Vgs characteristic curve as figure 1.5(a)-(b).

nMOS

CODE

nmos_tan4.lib 'C:\synopsys\rf018.l' TTm1 d g 0 0 nch l=.18u w=.6uvgs g 0 0.3vdd d 0 1.47

.op

.dc vgs 0 0.4 0.001

.probe i1(m1)

.altervdd d 0 1.97.alter vdd d 0 0.97

.alter

.end


subckt element 0:m1 model 0:nch.12 region Cutoff id 35.0827n ibs -9.236e-24 ibd -6.6644p vgs 300.0000m vds 1.4700 vbs 0.

vth 539.2712m vdsat 42.9562m vod -239.2712m beta 1.9383m gam eff 969.4677m gm 925.8289n gds 14.6406n gmb 267.8080n cdtot 725.2269a cgtot 669.1441a cstot 943.6689a cbtot 1.4663f cgs 218.1501a cgd 217.7001a

Figure 7 Ids-Vgs graph for the nMOS with channel width 0.6u and length 0.18u operating in the subthreshold region. Note that y-axis is in logarithmic scale. The different Vds values (From top to

bottom, in V) are 1.97, 1.47, and 0.97.


pMOS

CODE

pmos_tan4


m1 d g 0 0 pch l=0.18u w=2.4u

vgs g 0 -0.3vdd d 0 -1.61

.op

.dc vgs -0.5 0 0.001

.probe i1(m1)

.alter

vdd d 0 -2.11.alter vdd d 0 -1.11

.end


subckt element 0:m1 model 0:pch.8 region Cutoff id -32.8190n ibs 5.335e-24 ibd 185.6572f vgs -300.0000m vds -1.6100

vbs 0. vth -504.2860m vdsat -41.9259m vod 204.2860m beta 1.2906m gam eff 663.8050m gm 827.7176n gds 14.5883n gmb 281.4369n cdtot 2.6985f cgtot 2.4089f cstot 3.6739f cbtot 5.6325f cgs 790.8560a cgd 783.8404a

Figure 8 Ids-Vgs graph for the pMOS with channel width 2.4µ and length 0.18µ operating in the subthreshold region. Note that y-axis is in logarithmic scale. The different Vds values (From top to

bottom, in V) are -1.11, -1.61, -2.11.


Question

Question 1: If we increase the W/L of the device in step 1, what changes will occur to the curve of figures 1.2(b)-(c)?

For both the nMOS and pMOS, increasing the width-length ratio would cause a much steeper slope for the Ids-Vgs graph for when |Vgs|>|Vth|.

Figure 9 The effect of increasing the W/L for the nMOS in the configuration of step 1. Note that the top curve has W=0.90µ while the bottom curve has W=0.6µ.

Figure 10 The effect of increasing the W/L for the pMOS in the configuration of step 1. Note that the top curve has W=2.4µ while the bottom curve has W=2.7µ.

Thus, in general, a larger W/L ratio would result in a device that has a larger change in drain current with increasing gate-source voltage Vgs. Also, it is apparent that a device with a larger W/L would require less input voltage Vgs to cause for the same amount of current to flow.


Question 2: When the dimensions Wn/Ln equal Wp/Lp, does |Idsp|/|Idsn| equal µp/ µn?

For this question, we will assume that the nMOS model has the exact inverse characteristics as the

pMOS model, and we will also consider the equation of ID at the saturation region/linear region:

For nMOS,

|Idsp|= 12

µpcox

℘Lp (VDS – VTH)2

Similarly, for pMOS,

Idsn= 12

µncoxW nln

(VDS – VTH)2

It is important to note that Idsn and Idsp are opposite in direction, but if we must consider each to be an

inverse model of the other, then the magnitudes of these currents must be equal.

Since we are considering each model to have an inverse characteristic as the other, and we are only

concerned with W, L and µ values, we can discard the other terms treating them as equal.

This gives us the equation:

¿ I dsp∨ ¿I dsn

¿ =

µ p℘Lp

µnWnln

And if

℘Lp =

Wnln

,

Then

|I dsp|I dsn

= µ pµn

Question 3: What is the relationship between the channel length and the slope of the curve in figure 1.4(a)-(b)?

As shown in figures 5 and 6, increasing the channel length of either the nMOS or the pMOS would result in our drain current magnitude |Id| to have a much smaller increment for increasing magnitude values


of |Vds|. This would imply that our drain current will be more stable for increasing values of Vds within the saturation region. In other words, we would have a “flatter” saturation region curve.


Question 4: When the MOSFET operates in subthreshold region, what is the relationship between Vgs and the slope of the curves of figures 1.5(a)-(b)? What device, either pMOS or nMOS, has the larger slope? Why?

In the linear scale, it is apparent that the drain current is far too small for us to notice any change in it with respect to the gate-source voltage Vgs, hence we use the logarithmic scale to observe these changes.

It is therefore wise to say that for varying Vds values, one fact remains the same: the drain current(on a logarithmic scale) of a MOSFET is varies with different Vgs values, still, not linearly, but exponentially.

If we were to compare the slopes of the pMOS and the nMOS for this region, considering the signs and not only the magnitudes, the nMOS would have a larger slope than the pMOS since the pMOS has a negative slope. This means that an nMOS will have increasing current for increasing values of Vgs (in subthreshold)

nmo sp mos characteristics

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