no slide titleusers.encs.concordia.ca/~asim/coen 451/lectures/l1.1_slides.pdf · concordia vlsi...

114
CONCORDIA VLSI DESIGN LAB 1 ASIC DESIGN Asim J. Al-Khalili---Concordia University

Upload: dinhminh

Post on 12-Apr-2018

216 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

1

ASIC DESIGN

Asim J. Al-Khalili---Concordia

University

Page 2: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

2

Objectives •What technologies are there?

•Why CMOS?

•Where are we?

•How far we can go

•What is the worldwide view of

microelectronics ?•What are the different

implementation methods?

Page 3: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

3

The First Transistor 1948

Page 4: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

4

Milestones of IC

Development

Beginning of Semiconductor Evolution 1948

Passive and Active Components from Semiconductor Materials 1958

Planar Transistors 1959

Planar Passive and Active Devices 1961

Small Scale Integration (SSI)1964

Medium Scale Integration (MSI) 1968

Large Scale Integration(LSI) 1971

Very Large Scale Integration (VLSI) / Ultra Large Scale Integration (ULSI) 1980s

System On Chip (SoC) 2000s and is continuing to get larger and larger

Page 5: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

5

WORLD OF SILICON

DOGS EAT DOGS

IC applications are in every aspects of our lives:

Computers

Toys

Consumer electronics

Household items

Automotive

Industrial equipments

Military

Communications

Advertising and Displays

Space and Exploration

Etc.

Page 6: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

6

Electronic Circuit Explosion

IC Technology Advances

MORE CIRCIUTS ON CHIP

LOW MANUFACTURING COSTSMORE COMPLEX MANY NEW PRODUCTS ELECRONIC PRODUCTS NEVER BEFORE POSSIBLE

NUMBER OF CIRCUITS TO BE DESIGNED

SKY ROCKETED

Page 7: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

7

Emerging-in-car systems

Page 8: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

8

The Internet Big Bang

Page 9: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

EVEN ATMs

9

Page 10: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

10

The Incredible Shrinking

Transistor

1970’s

1980’s 2000 2014

Page 11: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

11

Reduction in Feature Size

Physical parameter

Constant-

Electric Field

Scaling Factor

Generalized

Scaling Factor

Generalized

Selective

Scaling Factor

Channel length,

Insulator thickness1/ 1/ 1/d

Wiring width,

channel width1/ 1/ 1/w

Electric field in

device1

Voltage 1/ / /d

On-current per

device1/ / /w

Doping d

Area 1/2

1/2

1/w2

Capacitance 1/ 1/ 1/w

Gate delay 1/ 1/ 1/d

Power dissipation 1/2

2/

2

2/wd

Power density 1 2

2w/d

Reduce transistor and wiring by

Page 12: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

12

The First Computer

The BabbageDifference Engine(1832)

25,000 parts

cost: £17,470

©Prentice Hall/Rabaey

Using finite difference it is possible to replace multiplication, division and subtraction

by addition, So in calculating the value of a polynomial we may use addition only .

Adding two numbers using gearwheels is easier to implement than doing it by

multiplication or division.

Page 13: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

13

ENIAC - The first electronic computer

(1946)

Prentice Hall/Rabaey

20,000 Vacuum Tubes, it cost $500,000

It could Add, Subtract and store 10-digit decimal numbers in memory

It weighted 27 tons, had a size of 80 ft* 8.5 ft* 3 ft, and it required a room of 680 ft2

Consumed 150KW

Page 14: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

BUT NOW, a small cell phone

By the millions, more powerful, more functions, less

weight, less power consumption, less heat generation

Page 15: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

15

Intel 4004 Micro-Processor 1971

Prentice Hall/Rabaey

4-bit CPU

2,300 transistors

Area of 3 by 4 mm

Employed a 10 μm

silicon-gate

92,000 instructions/s

740 KHz Clock 16 pin

Page 16: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

16

Intel Pentium (IV) microprocessor

2002

Prentice Hall/Rabaey

A 'Northwood' core

Pentium 4 processor (P4A)

Northwood core at 2.2 GHz

2nd cache 512 KB 55

million transistors, 130 nm

Technology

Page 17: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

17

Number of

Logic Gates

(Moore’s Law)

Logic Block

Area (Moore’s

Law)

Number of

Logic Gates

(Max = 10M)

Logic Block Area

(MAX = 10M)

1M 0.909 1M 0.909

2M 0.923 2M 0.923

4M 1.0 4M 1.0

8M 1.091 8M 1.091

24M 1.32 10M 0.55

64M 1.42 10M 0.22

192M 1.782 10M 0.09

Double Logic Gates Every Two Years ( Moore’s Law )

Maximum Macrocell Size beyond 2005 ( 10 M gates )

1990 2001 2003

22005 2008 2011 2014

100

90

80

70

60

50

40

30

20

10

0

Year

MOORE’S LAW

Page 18: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Intel announces 14 new Ivy Bridge

Processors

May. 31, 2012 (8:31 am) By: Matthew Humphries In: Chips, Chips Picks, Geek Pick, News

Intel launched the 22nm Ivy Bridge processors that uses

quad-core chips

Since then it added another 14 processors to the line-up, only this time

the chips are mainly dual-core parts catering to a number of different

market segments and platforms. .

Of the 14 new processors, 6 are classed as desktop chips with power

use (TDP) ranging from 35-77 watts. These consist mainly of new

quad-core chips, but one dual-core desktop chip is also listed (i5-3470T).

CPU frequency ranges from 2.6GHz to 2.9GHz and maxing out at 3.4GHz

using Intel Turbo Boost on the Core i7 chip. .

Page 19: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

IBM Creates New Memory Technology

100 Times Faster Than Flash

by Bryan Vore on July 01, 2011

IBM revealed its new phase-change memory (PCM) tech thatcould drastically change computing and gaming.IBM says that PCM is able to write and retrieve data 100 times faster than Flash memory. It also lasts much longer, surviving 10 million write cycles compared to the 3,000cycles of Flash that the averageconsumer can use.IBM claims that PCM will herald a "paradigm shift“ when it hits the market in 2016. .

Page 20: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

IBM Promises Internet 400 times faster

A new technology from IBM promises hyper-fast and energy

efficient connections to the Internet,as fast as 400 gigabits per second.

Scientists in IBM Switzerland just unveiled a prototype tiny chip for an energy

efficient analog-to-digital converter (ADC), that’s 5,000 times faster than the

average U.S. connection, or 400 times faster than Google Fiber.

This is fast enough to download a 2-hour ultra-high-definition movie (about 160

gigabytes) in seconds!

The latest version of the chip, developed by IBM with researchers from Ecole

Polytechnique Fédérale de Lausanne in Switzerland, is only a prototype right

now and was presented at the International Solid-State Circuits Conference

(ISSCC) in San Francisco.

Page 21: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Latest New iTwin tech torrent onto our hard

drives and memory sticks 2011-12

Latest New iTwin tech torrent onto our hard drives and memorysticks 2011-12 Stuck together, the iTwin twins look like a double-endedUSB flash memory stick. However, there’s no real storage available ineither. Instead, this natty gadget creates a sort of wormholethrough the internet, joining together the two computers that the halvesof the iTwin are plugged into

Page 22: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

SD-GU064G2 SD-GU032G2 SD- GU016G2

Capacity 32GB 64GB 16GB

Maximum read speed 95MB/ sec

Maximum write speed 60MB/ sec

Shipped in April 2014, with prices ranging from $120 to $300.

TOSHIBA SD Memory

Page 23: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Toshiba develops, manufactures 19nm generation NAND Flash Memory with

world's largest density and smallest die size128 Gb capacity in a 3-bit-per-cell chip on a 170mm2 die23 Feb, 2012

TOKYO—Toshiba Corporation (TOKYO: 6502) today announced breakthroughs in NAND flash that secure major advances in chip density and performance. In the 19 nanometer (nm) generation, Toshiba has developed a 3-bit-per-cell 128 gigabit (Gb) chip with the world's smallest[1] die size—170mm2—and fastest write speed[2]—18MB/s of any 3-bit-per-cell device. The chip entered mass production earlier this month .

Page 24: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

What's the largest memory stick that you can buy?

It is 256GB. It is a Memory Stick/Flash Drive/USB/Small Little Finger. It is

Very Expensive.128GB$1,499.99Item# SDCFXP-128G-A91SanDisk Extreme® Pro™ CompactFlash®

128GB Card with VPG

.

.

Jun 19, 2012 SANDISK I

Kingston 1TB USB3.0

DataTraveler HyperX

$899 Valid from Aug 05, 2014

Page 25: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Is 14nm the end of the road for silicon chips?

• Atoms are very small, but they still have a finite size. The atoms used

in silicon chip fabrication are around 0.2nm. A human hair diameter

is around 150 micron. A transistor in a 14 nm is around 80 nm.

• A process that Intel use with Ivy Bridge — the high-κ dielectric layer

is just 0.5nm thick; just two or three atoms!

• NOW no manufacturing technique is so accurate, since a single, out-

of-place atom can ruin an entire chip, it is going to be extremely

difficult to manufacture circuits that are both reliable and cost

effective.

Page 26: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Chipmakers are working hard to reach the 5nm node, but, the industry has several

challenges to overcome.

Presently, the leading transistor candidates for 5nm are the usual suspects— III-V

finFETs; gate-all-around; and nanowires. But the tunnel field-effect transistor

(TFET) is also considered for its low power and low voltage, about 0.5 –volt

Putting TFETs and finFETs into production is difficult and may need III--‐V

materials, nanowires and other complex technologies.

System Design Engineering community,

Wed, April 30 2014,

What foundary support is needed for any chip maker looking to develop 14/16 nm

finFET ? a discussion with Steve Carlson, Director, office of Chief Strategy Officer,

Cadence Design.

http://chipdesignmag.com/sld/blog/2014/04/30/deeper-dive-wed-april-30-2014/

What is in store for us

Page 27: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CHALLENGES MOUNT FOR INTERCONNECT> By Mark LaPedus

There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect.

ROUTING CONGESTION RETURNSBy Ed SperlingRouting congestion has returned with a vengeance to SoC design, feuled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors.

Page 28: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Example of Industrial foundry

GLOBALFOUNDRIES provides advanced semiconductormanufacturing excellence with leading-edge (28nm),mainstream (65nm and 45nm) and mature (0.35um to0.11um) technology, on both 200mm and 300mm wafers.GLOBALFOUNDRIES has fabrication in Dresden, New York andSingapore, with a network of design and support centers inSilicon Valley, China, Japan, Germany, Singapore, Taiwan andthe U.K.WWW.GLOBALFOUNDRIES.COM

LEVERAGING THE PASTBy Ann Steffora Mutschler

“It is easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques,

Page 29: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

3D design opens up architectural possibilities forengineering teams to realize much betterperformance and far less power consumption.

The greatest power savings in 3D designs areachieved at the architectural level, and that maymean jumping in at the deep end.

Hot topic: Thermal integrity's effect on 3D-IC design and analysis.

[email protected]>

3D design

Page 30: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

What Comes After FinFETs?By Mark LaPedus

The semiconductor industry is currently making a major transition from

conventional planar transistors to finFETs starting at 22nm.

The question is what’s next? In the lab, IBM, Intel and others have demonstrated

the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of

steam, there are no less than 18 different next generation candidates that could

one day replace today’s CMOS-based finFET transistors.

Mayberry said the eventual winners and losers in the next-generation

transistor race will be determined by cost, manufacturability and

functionality. “The best device is the one you can manufacture,” he said.

In fact, the IC industry is already weeding out the candidates. In 2005,

the Semiconductor Research Corp. (SRC), a chip R&D consortium

, launched the Nanoelectronics Research Initiative (NRI), a group that is

researching futuristic devices capable of replacing the CMOS transistor

in the 2020 timeframe. NRI member companies include

GlobalFoundries, IBM, Intel, Micron and TI.http://extensionmedia.c.topica.com/maapRorab9Upkcc03nbcaeht4A/

Page 31: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

posted on April 28, 2013 byStaff Writer

Top FPGA Companies For 2013

http://sourcetech411.com/2013/04/top-fpga-companies-for-2013/fpga_market_262x193/

These two companies comprise approximately 90% market share (Xilinx 47%, Altera 41%) in 2012 with combined revenues in excess of $4.5B and a market cap over $20B.

Page 32: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

New materials and processes for advanced interconnects

Although on chip interconnects have not been scaling at the same speed as other

parts of the chip, new capabilities enabled by graphene and CNTs, among other

materials, could soon change that.

http://marketing.electroiq.com/ct.html?ufl=b&rtr=on&s=x9w5u6,a0tz,5ke,km42,2w

dj,fvk2,ca13

3D memory for future nanoelectronic systems

3D memory will generally cost more than 2D memory, so generally a system must demand

high speed or small size to mandate 3D.

Communications devices and cloud servers need high speed memory. Mobile and portable

personalized health monitors need low power memory. In most cases, the optimum solution

does not necessarily need more bits, but perhaps faster bits or more reliable bits.http://marketing.electroiq.com/ct.html?ufl=b&rtr=on&s=x9w5u6,a0tz,5ke,8tkl,1r3y,fvk2,ca13

When it comes to memory manufacturing, consolidation is king.

Today only three major DRAM manufacturers remain MICRON, SAMSUNG, and SK

HYNIX

Spectrum Jan 2014

How about interconnect and Memory

Page 33: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Compound Semiconductors Join the race to sustain

Moore’s Law

Engineers at Imec and IBM have independently

developed processes for making the next decade’s

leading chips. The process involves using wafers and

certain exotic materials compound semiconductors with

ingredients from columns III and V of the old periodic

table . The mixing materials holds the key to

maintaining the traditional performance improvements

associated with Moore’s Law and the shrinking of

Transistors.Spectrum IEEE Jan 2014

Page 34: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

All optical transistors

“The Max Planck Institute of Quantum Optics has taken a step

towards devising the long-awaited optical transistor. The

technology could pave the way towards long-haul data

transmissions using an all-optical network.

Researchers from Max Planck have devised a type of optical

transistor using a cloud of ultra-cold rubidium atoms.”.

http://semiengineering.com/manufacturing-bits-august-5/

Page 35: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Worldwide Semiconductor Revenue Grew 5 Percent in 2013,

According to Final Results by Gartner

• Intel Retained the No. 1 Position for the 22nd Year in a Row

Total worldwide semiconductor revenue reached $315 billion

in 2013, up 5 percent from 2012, according to Gartner, Inc.

February Semiconductor Sales Up 11.4 Percent Compared

to Last Year.

More Than One Fourth of Industry Wafer Capacity Dedicated

to <40nm Process Geometries.

• Semiconductor Market Forecast to Contract by 0.1 Percent

in 2012 - First Decline in ThreeYears

State of Semiconductor Revenue

Page 36: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

https://www.youtube.com/watch?v=eh3dA8xnZ4Y

Graphene The wonder Material

Page 37: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

http://www.ted.com/talks/ayah_bdeir_building_blocks_that_blink

_beep_and_teach

TED on Little Bits

Page 38: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

http://www.ted.com/talks/ayah_bdeir_building_blocks_that_blink

_beep_and_teach

Electronic Building Blocks

Page 39: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

https://ca.finance.yahoo.com/news/microchips-implanted-healthy-people-sooner-

152916800.html

Personal Chip Implant

Page 40: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

We have seen nothing YET the best days are still aheadBrain ImprovementFor millions, the brain has not changed, but how we use it is changed. BUT NOW :• Genetically it is possible to alter the brain to create a super brain .• The future comes with new innovation (brain power)• We can upgrade our brain (With implants)• Increase memory (with implants)• Increase sensors (with implants)• Communication between Brain-Brain directly rather than converting chemical –

electrical-sounds-pressure waves-mechanical (mouth)-pressure movements (ear) –electrical- chemical, we should be doing it directly

• The most important development in the world has been technology start with steam engine, ie replacing human muscle with machine, which is more powerful… So what happens if we increase our brain power, then what we can do !!

https://www.youtube.com/watch?v=Z8HeFNJjuj0

Smarter DevicesDigital Technology as it gets smarter is eating up our jobs ( example : copier.. translators, Articles written by machines, driverless cars, trucks.. )

Economies do not run on energy, labor , or capital The future is with innovation

Page 41: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

41

AIMs

What the customers want: High Quality

Low Cost

Small Size/Weight

What the Employer wants Design the:

Best

Cheapest

In shortest time

Follow the Spec or better.

What you (chip designer) should do: Design a chip with:

High speed

Small area

Low power

Testable and reliable

Delivered in a short time

Page 42: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

42

Instructor Name: Asim Al-Khalili

Office: EV5.126

Tel: 514 848-2424 ext.3119, FAX 848 2802

Email [email protected]

Web http://www.ece.concordia.ca/~asim

Time: Mondays-Wednesdays 16:15-17:30

Class Room: MB- 1-301

Office hours: Wednesdays 2:00- 3:30

Course Outline

Reference Materials

Assignments

Lectures Information

Announcements

Tools

Project

Useful Files

Important Dates:

Midterm Exam: ,Monday 13st Oct,2014

Final Exam: Exam: To be announced

Project Delivery: Monday 15th Dec. 2014, at 2:00 pm. To be handed to

me in my room or the Secretary at front desk.

Web Information

Page 43: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

43

The following topics will be covered:

Week_1 Introduction to ASIC design and review materials.

Week_2 MOS transistor characteristics.

Week_3 DC analysis of CMOS logic family.

Week_4 RC time models, interconnect models.

Week_5 Transient analysis, propagation delay models.

Week_6 CMOS gates and Static logic families.

Week_7 Memory elements. Clocking strategies.

Week_8 CMOS process and layout generation.

Week_9 Layout techniques.

Week_10 I/O drivers and circuit protection.

Week_11 Circuit Optimization and secondary effects.

Week_12 Dynamic logic families.

Week_13 Design for Testability, Packaging, PLD, Synthesis issues.

Laboratory: H915. The lab is conducted as an open concept, with no schedule.

Information on lab usage will be provided in class.

Grading: 5% Assignment Midterm 15% 20% project, 60% Final Exam

Text: “CMOS Digital Integrated Circuits, Analysis and Design” (Recommended )

By Sung-Mo Kang and Yusuf Leblebici,3rd Edition, Published by McGraw-Hill

“Principles of CMOS VLSI Design” By N. H. Weste & K. Eshraghian

2nd Edition, Published by Addison Wesley

“ Application Specific Integrated Circuits”, By M. J. S. Smith,,Addison Wesley

Page 44: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

44

Device

Physics

Device

Electronics

Transistor Circuits

Combinational and

sequential Logic Circuits

Regular and irregular

Subsystems

System related issues including

reliability, DFT

Covered

in COEN

451

Page 45: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

45

Course Project

The course requires:

•design, Design Verification

•Layout, Layout Verification, DRC

•Post Layout Simulation,

•Characterization

•IN/OUT placement

An example of students projects follows:

Page 46: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Scientific Process or method: Sir Francis Bacon Formulation of a question: Why the apple falls down and not up?

Hypothesis: based on knowledge obtained while formulating the

question

Prediction: This step involves determining the logical consequences of

the hypothesis

Testing /experimentation: This is an investigation of whether the real

world behaves as predicted by the hypothesis.

Analysis: This involves determining what the results of the

experiment show and deciding on the next actions to take

Theory

Page 47: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

LearningIf you're going to learn anything, you need two kinds of prior knowledge:

knowledge about the subject at hand, like math, sciences, or programming

knowledge about how learning actually works, ie understanding of the cognitive strategies

that allow people to learn well.

Suggestions to help you learn:

Force yourself to recall.

In your mind repeat what you have read and see if you can recall what you have just read.

Flashcards are useful in this, since they force you to supply answers.

Connect the new thing to the old things in your brain.

When you do that you are creating new web-lines, in your web of knowledge(Connections

between Neurons) that will stick in your brain.

Reflect.

At the end of your learning session reflect in your mind what you have learned.

Henry Roediger and Mark McDaniel, psychologists at Washington University in St. Louis and coauthors of "Make It Stick: The Science Of Successful Learning”

Page 48: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Life• When passing a flower, stop and smell it and look at it and

appreciate it. Life moves on, so stop and look at the good things around you.

• Be Happy with what you can do and ignore the things that you did not succeed to do.

• Have a good social life and surround yourself with people that have the same wave length and hobbies so that you can be yourself amongst them .

• Keep your hopes alive and keep moving forward by looking forward to what you want to achieve. Keep doing new things and learn new things.

• Enjoy the present, consider every breath is a present

Page 49: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

Tools

Cadence unveiled two new tools. The first is a rapid prototyping

platform that the company claims will shorten bring-up time by 70%,

with 4X improvements in capacity, with IEEE 1801 support for low-

power verification through its emulation platform.

The second is a single and multi-corner custom/analog extraction tool,

which it claims will improve performance by 5X. The tool has been

certified for TSMC’s finFET process.

Page 50: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

50

The Future for Feature Size

Page 51: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

51

2001

2000

1999

0 100 200 300 400 500 600 700 0

10

20

30

40

50

Junction Depth (nm)

Sheet Resistance (/sq)

800

60

2002

2003

2004 2005

2008

2011

2014

The Future of Junction Depth

Page 52: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

52

Power density Evolution

Feature size (µm)

Watts/cm2

Page 53: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

53

Power Consumption

Page 54: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

54

Gate

Over

Drive

Supply Voltage

Vth

1980 1985 1990 1995 2000 2005 2010 20150

1

2

3

4

5

Year

VoltsThe Future for Supply Voltage

Page 55: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

55

Optical Communications

Page 56: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

A day made of Glass

http://www.youtube.com/watch?v=X-GXO_urMow&playnext=1&list=PL00407EB774FA759B&feature=results_main

Page 57: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

57

Logic Unit

Bu

s C

on

trol

Memory

Clock Generation

Reg

iste

rLogic Unit

ControlLogic

Bonding pads

A Typical CHIP

Page 58: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

58

Design Abstraction Levels

Prentice Hall/Rabaey

n+n+

S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Page 59: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

59

CMOS System Design

Top-down Design:

Design starts at System Specification and works its

way to bottom, ie. circuit level

Bottom-up design:Design starts at the basic circuits and works

upwards towards system level structure

Page 60: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

60

RTL SYNTHESIS

RTL NETLIST

LOGIC SYNTHESIS

GATE-LEVEL

NETLIST

PHYSICAL SYNTHESIS

MASK-LEVEL

LAYOUT

RTL

DESCRIPTION CREATION

Register-level

Floorplanning

Sequential Synthesis

Logic Optimization,

Technology

Mapping, Test

Generation

Physical

Floorplanning

Placement Signal

Routing, Clock

Layout, Power &

Ground Routing

VERIFICATION

Simulation

Functional Verification,

Timing Verification,

Simulation

Parastic Extraction;

Power Integrity, Clock

Skew, and Noise

Analyses; Peliability

Analysis

THE DESIGN FLOW

Page 61: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

61

Verify at every step

LayoutDeviceCircuit

Logic

Structural

CP

U

ME

MO

RY

Functional

Page 62: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

Design Strategies

Hierarchy

– A repeated process of dividing large

modules into smaller sub-modules until the

complexity of sub-modules are at an

appropriately comprehensible level of detail.

– Parallel hierarchy is implemented in all

domains.

Page 63: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

ÔRegularity

l Divide the hierarchy in to similar building

blocks whenever possible.

l Some programmability could be added to

achieve regularity.

ÔModularity

l Well defined behavioural, structural and

physical interface.

l Helps: divide tasks into well defined

modules, design integration, aids in team

design.

ÔLocality

l Internals of the modules are unimportant

A Structured Design

Page 64: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

IC Design Methodology

Requirement specification

– most important function which impacts the

ultimate success of an IC relates to how firm

and clear the device specifications are.

– Device specification may be updated

throughout the design cycle.

– Main items in the specifications are:

functional intent: brief description of the device,

the technology and the task it performs.

Packaging specification

– device port number

– package type, dimension, material

Page 65: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

high-level block diagram: all major

blocks including intra block connections

and connections to pin-outs indicating

direction and signal flow.

Intra block signal function: description

of how blocks interact with each other

supported with timing diagram where

necessary.

· Internal block description of internal

operation of each block. Where

necessary, the following to be

included: timing diagram, state

diagram, truth table.

Functional Description

Page 66: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

l I/O specifications

· pin-out diagram

· I/O functional description

· loading

· ESD requirements

· latch-up protection

l D.C. specifications

· absolute maximum ratings for: supply

voltage, pin voltages

· main parameters: VIL and VIH for each

input, VOL and VOH for each output,

input loading, output drive, leakage

current for tri-state operation,

quiescent current, power-down current

(if applicable)

Specifications

Page 67: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

l AC specifications

· inputs: set-up and hold times, rise and

fall times

· outputs: propagation delays, rise and

fall times, relative timing

· critical thinking

l Environmental requirements

· operating temperature, storage

temperature, humidity condition (if

applicable)

Testing

Specification, continued

Page 68: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

Device Specification

] Functional intent: briefly describe the

device, the technology, and the circuits it

will replace as well as the task it will

perform.

^ Design concept

Î pin-out diagram: describe the device using a

block diagram of the external view of the chip -

basically, a box with all the I/O pins labelled and

numbered

Î I/O description: use a chart to define the I/O

signals shown in the pin-out diagram

Page 69: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

Example:

Pin # Pin Name I/O Type Function

P1 VDD Power

Supply

Power

Supply, +5V

dc with

respect to

VSS

P2 TXCLK Input Transmit

Clock, 5.12

MHz rate

P3 TXP1 Output Transmit

output –

channel 1,

+ve polarity

Page 70: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

internal block diagram: draw blocks for

major functions, show all connections

including: connection to all pin-outs,

connections between blocks, and

direction of signal flow

Inter-block signal function: describe

how the blocks interact with each other

and support this with timing diagrams

where necessary

· internal block description: describe the

internal operation of each block. When

necessary, include: timing diagrams,

state diagrams, and truth table

Functional Specification

Page 71: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

Operating characteristics

Absolute maximum stress ratings.

Example:

Parameter Symbol Min. Max. Unit

Storage T Ts -65 +150 OC

Operating T TA -40 +85 OC

Supply V VDD -0.5 7 V

Input V VI -0.3 VDD + 3 V

Supply I IDD 5 mA

Page 72: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

l Operating power and environmental

requirement:

· power supply voltage

· operating supply current (specify

conditions, e.g., power up, power

down, frequency, output conditions)

· storage temperature

· operating temperature

· humidity conditions (if applicable)

Requirements

Page 73: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

Input characteristics. Example chart:

(V reference is VSS = 0, temperature range is

0oC to 70oC)

Pins Symbol Para-

meterMin nom Max Units Comments

TXDAT2

TXDAT2VIL Input

low V-0.3 0.4 0.8 V

TXCK

TXFRMVIH Input

high V2.0 2.4 VCC +

0.3V

ENB1

ENB2

ICK

LFPM

CSBL

CI Input C

to VSS10 pF

Imputs

protected

against

static

damage

IIL Input

low I+/- 10 A Vin =

0V

IIH Input

high I+/- 10 A Vin =

5.25V

RX1N1

RX1N2VIP Input

peak V

VDD +

0.3V

AC

coupled

input

Page 74: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

ÔRegularity

l Divide the hierarchy in to similar building

blocks whenever possible.

l Some programmability could be added to

achieve regularity.

ÔModularity

l Well defined behavioural, structural and

physical interface. Helps: divide tasks

into well defined modules, design

integration, aids in team design.

ÔLocality

l Internals of the modules are unimportant

to any exterior interface.

A Structured Design

Page 75: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

75

Aim of CMOS system Design

High Density

Fast Switching Time

Low Power Dissipation

Testable Design

Regular and Modular Design

Page 76: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

76

System Performance

This is related to several factors

including:

Algorithm design

Design strategy

Circuit implementation

Floor plan

Interconnect strategy

Input/Output drives and coupling

Clock distribution

Interfacing

Page 77: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

77

Standard DevicesGeneral purpose use --not optimized to a specific application

* Fixed or programmable

* Available in various complexities:

SSI, MSI, LSI, VLSI, and ULSI

* Function: standard logic, MPU, memories, DSP, analog

functions

* Available in a variety of packages

* Technology: bipolar, nMOS, CMOS, BiCMOS, GaAs

* Occupy larger areas and consume more power compared to

other types of ICs

Page 78: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

78

Full CustomHAND CRAFTED DESIGNG

* STRUCTURED DESIGN

HIERARCHIAL: TOP DOWN DESIGN,

BOTTM UP DESIGN

* EXTENSIVE VERIFICATION

* MIXED DIGITAL AND ANALOG

* TIME CONSUMING AND EXPENSIVE

* REQUIRES EXTENSIVE DESIGN EXPERIENCE

* COST EFFECTIVE FOR LARGE PRODUCTION

VOLUMES

Page 79: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

79

GATE ARRAY

CONSISTS OF TRANSISTOR ARRAYS

* CUSTOMER DEFINES INTERCONNECTION BETWEEN

TRANSISTORS

* VENDOR PROVIDES INTERCONNECTION

TOPOLOGIES TO FORM LOGIC FUNCTIONS

* 1 TO 6 LEVELS OF METALIZATION

* AVAILABLE IN DIFFERENT TECHNOLOGIES

* 2000 TO 5,000,000 GATE LOGIC COMLEXITIES.

* 2 TO 4 WEEKS DESIGN LEAD TIME

Page 80: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

80

STANDARD CELLS

*PREDESIGNED AND PRECHARACTERIZED CELLS

* AVAILABLE IN VARIOUS CELL COMPLEXITIES:

MACROCELLS --VARIABLE HEIGHTS

MICROCELLS--STANDARD HEIGHTS

* DESIGN PHILOSOPHY SIMILAR TO OFF THE SHELF COMPONENTS

* MORE EFFICIENT SILICON UTILIZTION COMPARED

* MEDIUM DESIGN TIME

* LOWER COST

* COST EFFECTIVE FOR LARGE PRODUCTION VOLUMES*

Page 81: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

81

CELL TOPOLOGY

STANDARD CELLS ARE AVAILABLE AS FIXED HEIGHT OR

VARIABLE HEIGHT.

*FIXED HEIGHT CELLS:

--MAJORITY OF CELLS ARE IMPLEMENTED USING

-- FIXED HEIGHT, BUT VARIABLE WIDTH LAYOUT

-- CELLS ARE STACKED IN ROWS

* VARIABLE HEIGHT CELLS :

--FOR MORE COMPLEX FUNCTIONS SUCH AS MEMORY, ALU,

MICROPROCESSOR

* COST EFFECTIVE FOR LARGE PRODUCTION VOLUMES

Page 82: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

82

-- Project of ASIC Design --

Instructor: Dr. A.J.AL-Khalili

Submitted by

Ji, Haiying Zhang, Haiqing

Submitted Date: 29 April, 2002

Page 83: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

83

Ove rvie w

Logic Design Specification: exhibiting our logic design of every unit: half adder/subtracter,

one-bit counter, 4-bit counter. Logic circuit simulation result is presented. The stage mainly

worked on the Synopsys development platform within UNIX.

Circuit Design Specification: fully covering the most of our work about every CMOS logic

circuit unit: NAND and NOR gates, D flip-flop etc. All parameters of circuits are decided. And

there are some the circuit plots and waveforms generated by Cadence development tools that

test and verify every part of our CMOS circuit design.

Layout and Simulation: With Cadence layout tool, we drew the layouts of all circuit units

according to the design parameter from the last design stage. Perform DRC. Extract the design

and simulate it again and characterize the two gates. To perform DRC on the final design,

extract it and simulate it again to obtain the performance measures. The waveforms related the

design are shown and analyzed.

Packaging: The procedure to place and rout the complete chip including all I/O drivers and

PADs is presented.

Analyzing and Summary: The test results were analyzed carefully and helped us got

appropriate conclusion. Give a complete specification for the circuit. It is summary of our

work. It manifests our great gain of designing and developing work experience and important

realization from this course.

Appendix: this is needful supplement showing our coding work in logic design stage and

perfect layout picture drawn with Cadence layout tools.

Page 84: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

84

Logic Design

Port Function

clk DFF Driving Clock, 1-0: input -

output

clr “1” clear all port

udctrl 1: up counting

0: down counting

input 1 or 0

sout 0000--1111

brwcry Borrow or carry signal; for up

linking

4 –Bit

Up/Down

Counter

CLK

CLR

input

output(3:0)

udctrlbrwcry

Page 85: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

85

Up/ Down c ont ro lling-Half adde r and s ubt rac t e r de s ign

Half-Adder and Half-Substracter function:

Sout =A’B+B’A

Carry=AB

Borrow=BA’

The Up/Down Control signal is added to the unit. It just controls which one should be output either the carry or

borrow.

Borcar=B(UD’A’+UD*A) (UD: up/down control)

When UD=1, output carry, the unit works as a half adder. When UD=0, output borrow, it works as a half

substracter.

Page 86: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

86

One-Bit Up/ Down controlling Counter des ign

Combining a One-Bit D Flip-Flop, we implement the One-Bit Up/Down controlling Counter.

In1 S

udcontrol

In2 Bor/Car

D Q

CLR

CLK

Input

Control

Data i

Bor/Car

The ‘Data i’ is the counter output; bor/car can be the input for next level to form the several

bits counter.

Page 87: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

87

4 -Bit Up/ Down c ont ro lling Counte r Logic Circ uit Plan and Sim ulat ion

Using four One-Bit Up/Down controlling Counters, we implement the 4-Bit Up/Down controlling

Counter unit shown as following figure.

Page 88: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

88

We tested and verified the design within Synopsys simulation platform on the Unix

(Sun-Solaris). The waveform is shown as Figure 3-6.

Figure 3-6

Page 89: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

89

Circuit Design

D flip-flop c irc uit de s ign

Page 90: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

90

Parameter minimu

m

Typical Maximum Unit

fMAX maximum clock frequency ------ ------ 1670 MHz

tPLH propagation delay time, low-to-high

output from clear

------ ------ ------ Ns

tPHL propagation delay time, high-to-low

output from clear

0.1 0.1 0.1 Ns

tPLH propagation delay time, low-to-high

output from clock

0.18 0.2 0.22 Ns

tPHL propagation delay time, high-to-low

output from clock

0.17 0.2 0.2 Ns

Width of clock or clear pulse, tw 0.3 0.3 ------ Ns

Setup time, tsu 0.1 ------ ------ Ns

Data hold time, th 0.08 ------ ------ Ns

Supply voltage, VDD ------ 3.3 ------ Volt

Parameters for positive-edge-triggered D flip-flop.

Page 91: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

91

Timing waveforms of DFF

Page 92: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

92

Half Adder/Subtracter Circuit

Page 93: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

93

Half Adder/Subtracter Circuit waveforms

Page 94: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

94

Half Adder/Subtracter Timing parameters

Parameter Typical Unit

tPLH propagation delay time, low-to-high sout from data input 0.34 ns

tPHL propagation delay time, high-to-low sout from data input 0.38 ns

tPLH propagation delay time, low-to-high sout from udctrl 0.24 ns

tPHL propagation delay time, high-to-low sout from udctrl 0.26 ns

Sout rise-time, tr 0.1 ns

Sout fall-time, tf 0.1 ns

Borcar fall-time, tr 0.1 ns

Borcar fall-time, tf 0.1 ns

Supply voltage, VDD 3.3 Volt

Page 95: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

95

4-bit synchronous up/down counter design

4-bit synchronous up down counter implementation

Page 96: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

96

waves feature for the 4-bit synchronous up down counter

Page 97: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

97

Timing parameters for the 4-bit synchronous up down counter

Parameter Typical Unit

tPLH propagation delay time, low-to-high sout from clock input 0.34 ns

tPHL propagation delay time, high-to-low sout from clock input 0.43 ns

tPLH propagation delay time, low-to-high sout from udctrl 0.68 ns

tPHL propagation delay time, high-to-low sout from udctrl 0.60 ns

Sout rise-time, tr 0.38 ns

Sout fall-time, tf 0.36 ns

Borcar fall-time, tr 0.1 ns

Borcar fall-time, tf 0.1 ns

Supply voltage, VDD 3.3 Volt

Page 98: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

98

Layout and Simulation

NAND Gate Layout

Page 99: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

99

simulation waveforms of NAND gate

Page 100: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

100

Simulation characteristics of the 2-input NAND gate in complementary CMOS.

DC characteristics

Active

area

Total

area

Static

current

VOH VOL VIH VIL NML NMH

18.76

um2

132.5

um2

0 3.3

volts

0 volt 1.42

volts

0.87

volts

0.87

volts

1.88

volts

AC characteristics

tPLH

min

tPHL

min

tP

min

tPLH

max

tPHL

max

tP

max

tr

min

tf

min

tr

max

tf

max

Average

power

Peak

Power

0.15

ns

0.03

ns

0.09

ns

0.18

ns

0.05

ns

0.115

ns

0.15

ns

0.14

ns

0.176

ns

0.15

ns

0.43 mw 0.5

mw

Page 101: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

101

NOR Gate Layout

Page 102: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

102

Waveform of the 2-input NOR gate in complementary CMOS.

Page 103: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

103

DC characteristics

Active

area

Total

area

Static

current

VOH VOL VIH VIL NML NMH

24.87

um2

148.32

um2

0 3.3 volts 0 volts 1.57

volts

0.95

volts

0.95

volts

1.73

volts

AC characteristics

tPLH

min

tPHL

min

tP

min

tPLH

max

tPHL

max

tP

max

tr

min

tf

min

tr

max

tf

max

Average

power

Peak

Power

0.18

ns

0.05

ns

0.115

ns

0.2

ns

0.07

ns

0.135

ns

0.2

ns

0.15

ns

0.24

ns

0.16

ns

0.45 mw 0.6

mw

Simulation characteristics of the 2-input NOR gate in complementary CMOS

Page 104: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

104

Transmission Gate Layout

Page 105: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

105

Inverter Gate Layout

Page 106: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

106

DFF Layout

Page 107: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

107

Half Adder/Substrater Layout

Page 108: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

108

4-bit synchronous up/down counter layout

Page 109: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

109

Simulation waveforms of 4-bit synchronous up/down counter layout

Page 110: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

110

Simulation characteristics of 4-bit synchronous up/down counter layout

DC characteristics

Active

area

Total

area

Static

current

VOH VOL VIH VIL NML NMH Input

leakage

current

2685

um2

16000

um2

0 3.3 volts 0

volt

1.5 volts 0.9 volts 0.9 volts 1.8 volts 2 uA

Prerequisite for switching function

Maximum

frequency fma

Minimum

CLK width

Minimum

CLR width

Set up time

tsu uctrl to

CLK

Set up time tsu

CLR to CLK

Hold time th

uctrl to CLK

Hold time th CLR to

CLK

280 MHz 3.5

ns

1.6

ns

0.8

ns

0.3

ns

0

ns

0.15

ns

Switching characteristics

tPLH tPHL tPudctrl to output tPLH tPHL tPCLK to output tPLH tPHL tP CLR to output

0.7 ns 0.7 ns 0.7 ns 0.665ns 0.72 ns 0.693 ns -------- 0.8 ns 0.8 ns

Page 111: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

111

Package

I/O structure of the 4-bit synchronous up down counter.

Ø Input padsIn our chip we have three input pads:

CLK, CLR, and udctrl. We use the pads of

PADINC in hcells library, then make the

connection with the correspondent input in

the counter circuit using metal1dg layer.

Ø Output padsIn our chip we have five output pads:

output<0>, output<1>, output<2>, output<3>,

and brwcry (borrow carry). The first four

outputs are the counting results, and the

brwcry output pad provides a function of

forming cascaded counter using this counter.

Notes: -udctrl-- up/down control signal; CLK-- clock

signal; CLR-- clear signal -CLR is a high- active

signal, so there is no tPLH from CLR to output.

Page 112: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

112

Pad Layout of the 4-bit synchronous up down counter.

Page 113: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

113

Analyzing & Summary

From the three development stages, logic design, circuit design and layout simulation, we are

able to acquire the conclusion easily. The logic design simulation is the ideal wave that we want

to get. The circuit design simulation verifies our logic design correct and in this stage it also

help us decide the appropriate parameters. The layout is based on our circuit design parameter.

Its simulation result proves to our design work successful.

What should be advanced is the fact that there is some discrepancy between the two results

from circuit design simulation and layout simulation. As the shown in the

Figure 5-5 and Figure 4-10, all the time performance parameters from layout simulation are

higher those from circuit design simulation. Actually it is just right result that we have

predicted. The layout is closer to real product. However, the circuit design mainly simulates the

ideal model; some effect resulting from whole circuit can not be calculated accurately.

In short, our work is proved to be significant. Through the project we have learned more

system development knowledge and strengthened the ASIC design skills. The achievement from

that also manifests our team is successful and cooperative.

In addition, we understand the challenge projects in the future work and how to face and solve

them.

Again, we express our appreciation for our tutor Dr. A.J.AL-Khalili.

Page 114: No Slide Titleusers.encs.concordia.ca/~asim/COEN 451/Lectures/L1.1_Slides.pdf · CONCORDIA VLSI DESIGN LAB 4 Milestones of IC Development Beginning of Semiconductor Evolution 1948

CONCORDIAVLSI DESIGN LAB

114

Verify at every step

LayoutDeviceCircuit

Logic

Structural

CP

U

ME

MO

RY

Functional