noise

No Slide TitleEE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
EE 201A
Noise Modeling
Electrical Engineering Department
MEMS Research Laboratory Joe Zendejas and Jack W. Judy
Efficient Coupled Noise Estimation for On-Chip Interconnects
Anirudh Devgan
IBM Research Division, Austin TX
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Motivation
Difficult to control from chip terminals
Expensive to correct (refabrication)
Linear reduction techniques can be applied for linearly modeled circuits
i.e. moment matching methods
Inefficient for noise verification and avoidance applications
Noise Estimation
The paper presents an electrical metric for efficiently estimating coupled noise for on-chip interconnects
Capacitive coupling between an aggressor net and a victim net leads to coupled noise
Aggressor net: switches states; source of noise for victim net
Victim net: maintains present state; affected by coupled noise from aggressor net
Circuit Schematic
Let’s analyze the case for one aggressor net and one victim net
Switching signal
V2,1
V2,n
V1,1
V1,n
Circuit Equations
In Laplace domain:
Circuit Equations
Aggressor net:
Victim net:
Transfer Function
Transfer function:
Simplifications (details later):
Simplified transfer function:
Simplifications
A12 = 0
No resistive (or DC) path exists from the aggressor net to the victim net
A21 = 0
No resistive (or DC) path exists from the victim net to the aggressor net
B2 = 0
No resistive (or DC) path exists from the voltage/noise source to the victim net
Maximum Induced Noise
H(s=0) = 0
Maximum induced noise can be computed
Assume Vs is a finite or infinite ramp
Maximum Induced Noise
Final value theorem:
Ramp input u(s):
Circuit Interpretation
Switching slope
Circuit Computations
(matrix method)
Step 2: Compute
Requires circuit analysis of the victim net
(by inspection)
Replace aggressor net’s capacitors with open circuits
(by inspection)
Negligible loss: no resistive path to ground
(by inspection)
Step 2: Compute
Convert steady state derivative on the aggressor net to a current on the victim net
i : index of node on the victim net
j : index of node on the aggressor net
(by inspection)
Replace capacitors with coupling currents
The voltage at each node corresponds to that node’s maximum induced noise
(by inspection)
Compute by inspection in linear time
(by inspection)
Step 3: Compute
3RC Circuit example:
Computation Costs
Step 1:
Coupling currents from step 2 determined from a linear superposition
Experiment
Rise time of 200 ps or 100 ps
Power supply voltage of 1.8 V
Conventional circuit simulation vs. proposed metric
Run-time comparisons for various circuit sizes
Accuracy Results
10 nodes, 200 ps rise time
Accuracy Results
Sheet1
Node
% Error
1
0.0147
0.0168
7.73%
2
0.0277
0.0319
13.10%
3
0.0392
0.0454
13.65%
4
0.0492
0.0572
13.98%
5
0.0578
0.0673
14.11%
6
0.0651
0.0757
14.00%
7
0.0709
0.0824
13.95%
8
0.0752
0.0875
14.05%
9
0.0782
0.0908
13.87%
10
0.0797
0.0925
13.83%
Sheet2
Sheet3
Accuracy Results
Metric estimation is more conservative than circuit model’s
Fast rise times don’t allow circuit to reach ramp steady state noise
Loading of interconnect normally does not allow for very small rise times
Metric accuracy should be acceptable for many applications
Run-time Results
Arnoldi-based model reduction used a matrix solution to compute circuit response
Requires repeated factorizations, eigenvalue calculations, and time exponential evaluations
Sheet1
Node
360.55s
.35s
Sheet3
Conclusions
The proposed metric determines an upper bound on coupled noise for RC and over-damped RLC interconnects
Metric becomes less accurate as rise time decreases
The proposed metric is much more run-time efficient than circuit modeling methods
MEMS Research Laboratory Joe Zendejas and Jack W. Judy
Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Department of Computer Science, UCLA
Magma Design Automation, Inc.
2 Results Way, Cupertino, CA 95014
Motivation
Increased coupling capacitance between nets
Longer propagation delay
Crosstalk cannot be ignored
Aggressor / Victim Network
Aggressor
Victim
2- Model
Rd: Victim drive resistance
Rise time
victim / aggressor
coupling capacitance
2- Model Parameters
Aggressor
Victim
Analytical Solution
Analytical Solution part 2
s-domain output voltage
Transform function H(s)
Analytical Solution part 3
Output voltage
Simplification of Closed Form Solution
Closed form solution complicated
Dominant-pole simplification
Dominant-Pole Simplification
Elmore delay of victim net
Intuition of Dominant Pole Simplification
vout rises until tr and decays after
vmax evaluated at tr
Extension to RC Trees
Similar to previous model with addition of lumped capacitances
Results
95% of nets have errors less than 10%
Spice Comparison
peak noise noise width
Effect of Aggressor Location
As aggressor is moved close to receiver, peak noise is increased
Ls varies from 0 to 1mm
Lc has length of 1mm
Le varies from 1mm to 0
Optimization Rules
Rule 1:
If RsC1 > ReCL and tr << tv
Driver sizing will not reduce peak noise
Rule 2:
Noise-sensitive victims should avoid near-receiver coupling
Optimization Rules part 2
Rule 3:
Preferred position for shield insertion is near a noise sensitive receiver
Rule 4:
Rule 5:
And upper bound
Conclusions
2- model achieves results within 6% error of HSPICE simulation
Dominant node simplification gives intuition to important parameters
Design rules established to reduce noise
References
Anirudh Devgan, “Efficient Coupled Noise Estimation for On-chip Interconnects”, ICCAD, 1997.
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