ECE1371 Advanced Analog CircuitsLecture 10

NOISE IN SC CIRCUITS

Richard Schreierrichard.schreier@analog.com

Trevor Caldwelltrevor.caldwell@utoronto.ca

ECE1371 10-2

Course Goals

• Deepen Understanding of CMOS analog circuit design through a top-down study of a modern analog system

The lectures will focus on Delta-Sigma ADCs, but you may do your project on another analog system.

• Develop circuit insight through brief peeks at some nifty little circuits

The circuit world is filled with many little gems that every competent designer ought to recognize.

ECE1371 10-3

Project Presentations2008-04-07Project ReportMatching & MM-Shaping12TC2008-04-14

Switching Regulator11RS2008-03-31S&T CNoise in SC Circuits10TC2008-03-24

Amplifier Design9TC2008-03-17Amplifier Design8TC2008-03-10

Raz 12, J&M 10SC Circuits7TC2008-03-03J&M 7Comparator and Flash ADC6RS2008-02-25

Reading Week – No Lecture2008-02-18CTMOD2; Proj.S&T 4, 6.6, 9.4, BAdvanced 5RS2008-02-11

ISSCC – No Lecture2008-02-04Pipeline DNLJ&M 11,13Pipeline and SAR ADCs4TC2008-01-28

Q-level simJ&M 14, S&T BExample Design: Part 23RS2008-01-21

Switch-level simS&T 9.1, J&M 10Example Design: Part 12RS2008-01-14Matlab MOD2S&T 2-3, AIntroduction: MOD1 & MOD21RS2008-01-07

HomeworkRefLectureDate

ECE1371 10-4

NLCOTD: Gain Booster CMFB• Need CMFB for Gain Booster

One option is to use standard CT CMFB (Lecture 9)Is there an easier way with less circuitry?

IN IN

OUT OUT

VB4

VB3

VB1 VB1

VB4

VB3

VB2

M11

M2M1

M4M3 M4M3

M6M5

M8M7

M10M9

M12

EFF

B2

ECE1371 10-5

Highlights(i.e. What you will learn today)

1. How to analyze noise in switched-capacitor circuits

2. Significance of switch noise vs. OTA noisePower efficient solutionImpact of OTA architecture

3. Design example for modulator

ECE1371 10-6

Review• Previous analysis of kT/C noise

(ignoring OTA/opamp noise)Phase 1: kT/C1 noise (on each side)Phase 2: kT/C1 added to previous noise (on each side)Total Noise (input referred): 2kT/C1

Differentially: 4kT/C1

ECE1371 10-7

Review• SNR

Total noise power: 4kT/C1

Signal power: V2/2SNR: V2C1/8kT

• SNR (single-ended)Total noise power: 2kT/C1 (sampling capacitor C1)Signal power: V2/2 (signal from -V to V)SNR: V2C1/4kT

ECE1371 10-8

Thermal Noise in OTAs• Single-Ended Example

Noise current from each transistor isAssume

2 4n mI kT g2 / 3

ECE1371 10-9

Thermal Noise in OTAs• Single-Ended Example

Thermal noise in single-ended OTAAssuming paths match, tail current source M5 doesnot contribute noise to outputPSD of noise voltage in M1 (and M2):

PSD of noise voltage in M3 (and M4):

Total input referred noise from M1 - M4

Noise factor nf depends on architecture

32

1

83

m

m

kTgg

1

83 m

kTg

3,

1 1 1

16 1613 3

mn eq f

m m m

gkT kTS ng g g

ECE1371 10-10

OTA with capacitive feedback• Analyze output noise in single-stage OTA

Use capacitive feedback in the amplification / integration phase of a switched-capacitor circuit

n,eq

ECE1371 10-11

OTA with capacitive feedback• Transfer function of closed loop OTA

where the DC Gain and 1st-pole frequency are

Load capacitance CO depends on the type of OTA –for a single-stage, it is CL+C1C2/(C1+C2), while for a two-stage, it is the compensation capacitor CC

1 21 1 /G C C

,

( )1 /

OUT

n eq o

V GH sV s

1mo

O

gC

ECE1371 10-12

OTA with capacitive feedback• Integrate total noise at output

Minimum output noise for =1 is

Not a function of gm1 since bandwidth is proportional to gm1 while PSD is inversely proportional to gm1

22,

0

2

1

( ) ( 2 )

163 44

3

OUT n eq

of

m

fO

V S f H j f df

kT n GgkT nC

43 f

O

kT nC

ECE1371 10-13

OTA with capacitive feedback• Graphically…

Noise is effectively filtered by the equivalent brick wall response with a cut-off frequency of fo/2Total noise at VOUT is the integral of the noise within the brick wall filter (area is simply fo/2 x 1/ 2)

ECE1371 10-14

Sampled Thermal Noise• What happens to noise once it gets sampled?

Total noise power is the sameNoise is aliased – folded back from higher frequencies to lower frequenciesPSD of the noise increases significantly

1OUT

2

Ln,eq

O,S

IN

S

ECE1371 10-15

Sampled Thermal Noise

• Same total area, but PSD is larger from 0 to fS/2

Low frequency PSD is increased by

2 2, 4 1( )

4 / 2 / 2 3 / 2n eq OUT

Vout fS S O S

G S V kTS f nf f C f

312

dB

S S

ff f

o

Vout

AliasedNoise

s

Vo,s

2,n eqG S

ECE1371 10-16

Sampled Thermal Noise• 1/f3dB is the settling time of the system, while

1/2fS is the settling period for a two-phase clock

PSD is increased by at leastIf N = 10 bits, PSD is increased by 7.6, or 8.8dB

• This is an inherent disadvantage of sampled-data compared to continuous-time systems

But noise is reduced by oversampling ratio after digital filtering

3 ( 1)ln2dB

S

f Nf

1/ 2( 1)2

SfNe

( 1)ln2N

ECE1371 10-17

Noise in a SC Integrator• Using the parasitic-insensitive SC integrator

• Two phases to consider1) Sampling Phase

Includes noise from both 1 switches 2) Integrating Phase

Includes noise from both 2 switches and OTA

ECE1371 10-18

Noise in a SC Integrator• Phase 1: Sampling

Noise PSD from two switches:Time constant of R-C filter:PSD of noise voltage across C1

( ) 8Ron ONS f kTR

12 ONR C

1 28( )

1 (2 )ON

CkTRS f

f

Ron1 ON 1

Ron2

ONRon ON 1

C1

ECE1371 10-19

Noise in a SC Integrator• Phase 1: Sampling

Integrated across entire spectrum, total noise power in C1 is

Independent of RON (PSD is proportional to RON,bandwidth is inversely proportional to RON)After sampling, charge is trapped in C1

21, 1

1

84

ONC sw

kTR kTVC

ECE1371 10-20

Noise in a SC Integrator• Phase 2: Integrating

• Two noise sources - switches and OTANoise PSD from two switches:

Noise PSD from OTA:

Noise voltage across C1 charges to 2VRon – Vn,eq

( ) 8Ron ONS f kTR

,1

16( )3vn eq f

m

kTS f ng

ECE1371 10-21

Noise in a SC Integrator• What is the time-constant?

Analysis shows that

For large RL, assume that

Resulting time constant

2

1

1/1

LIN

m L

sC RZg R

1 1(2 1/ )ON mR g C1

1IN

m

Zg

Ron ON 1

C1

OUT

2

Lm1

IN

ECE1371 10-22

Noise in a SC Integrator• Total noise power with both switches and OTA

on integrating phase

Introduced extra parameter

,21,

1 1 1

1

( )4

163 4(2 1/ )43 (1 )

vn eqC op

f

m ON m

f

S fV

nkTg R g C

nkTC x

21, 2

1 1

1

( )4

84(2 1/ )

(1 )

RonC sw

ON

ON m

S fV

kTRR g C

kT xC x

12 ON mx R g

ECE1371 10-23

Noise in a SC Integrator• Total noise power on C1 from both phases

Lowest possible noise achieved if

In this case,

What was assumed to be the total noise was actually the least possible noise!

2 2 2 21 1, 1, 1 1, 2

1 1 1

1

43 (1 ) (1 )

4 / 3 1 21

C C op C sw C sw

f

f

V V V VnkT kT x kT

C x C x Cn xkT

C x

x21

1

2C

kTVC

ECE1371 10-24

Noise Contributions• Percentage noise contribution from switches

and OTA (assume nf=1.5)

0 2 4 6 8 100

20

40

60

80

100

x=2RONgm1

Noi

se F

ract

ion

(%)

SwitchOTA

ECE1371 10-25

Noise Contributions• When gm1 >> 1/RON (x >> 1)…

Switch dominates both bandwidth and noiseTotal noise power is minimized

• When gm1 << 1/RON (x << 1)…OTA dominates both bandwidth and noisePower-efficient solution

Minimize gm1 (and power) for a given settling time and noise

Minimized for x=0

1 21

4 1 23m f

C

kTg n xV

ECE1371 10-26

Maximum Noise• How much larger can the noise get?

Depends on nf… (table excludes cascode noise)

6.33.kT/C1

4.33.kT/C1

3.67.kT/C1

3.kT/C1

MaximumNoise (x=0)

4

2.5

2

1.5

nf

FoldedCascode

FoldedCascode

Telescopic/Diff.Pair

Telescopic/Diff.Pair

Architecture

VEFF,1=VEFF,n

VEFF,1=VEFF,n/2

VEFF,1=VEFF,n

VEFF,1=VEFF,n/2

Relative VEFF’s

5.01

3.36

2.63

1.76

+dB

ECE1371 10-27

Separate Input Capacitors• Using separate input caps increases noise

Each additional input capacitor adds to the total noiseSeparate caps help reduce signal dependent disturbances in the DAC reference voltages

2 11

1 1

4 / 3 1 2 1 ...1

afC

Cn xkTVC x C

1I

O

2

1 2

12

1aDAC

2

1

ECE1371 10-28

Differential vs. Single-Ended• All previous calculations assumed single-ended

operationFor same settling time, gm1,2 is the same, resulting in the same total power [0dB]Differential input signal is twice as large [gain 6dB]Differential operation has twice as many caps and therefore twice as much capacitor noise (assume same size per side – C1 and C2) [lose ~1.2dB for nf=1.5, x=0… less for larger nf]

• Net Improvement: ~4.8dB

ECE1371 10-29

Differential vs. Single-Ended• Single-Ended Noise

• Differential Noise

• Relative Noise (for nf=1.5, x=0)

2 2 2 21, 1, 1, 1 1, 2

1 1 1

1

4 2 23 (1 ) (1 )

4 / 3 2 41

C diff C op C sw C sw

f

f

V V V VnkT kT x kT

C x C x Cn xkT

C x

21,

1

4 / 3 1 21

fC se

n xkTVC x

21,21,

4 / 3 2 4 44 / 3 1 2 3

C diff f

fC se

V n xn xV

ECE1371 10-30

Noise in an Integrator• What is the total output-referred noise in an

integrator?Assume an integrator transfer function

where and

1

1( )1 (1 ) (1 )

kzH zk z

1

2

CkC

1A

1I

O

2

1 2

12C1

OUT

ECE1371 10-31

Noise in an Integrator• Total output-referred noise PSD

where

and

Since all noise sources are sampled, white PSDs

To find output-referred noise for a given OSR

21( ) ( ) ( ) ( )INT C OUTS f S f H z S f

2

/ 2x

xS

VSf

2 43OUT f

O

kTV nC

21

1

4 / 3 1 21

fC

n xkTVC x

/(2 )2

0

( )Sf OSR

INT INTV S f df

ECE1371 10-32

Noise in a Modulator• How do we find the total input-referred noise in

a modulator?1) Find all thermal noise sources2) Find PSDs of the thermal noise sources3) Find transfer functions from each noise source to

the output4) Using the transfer functions, integrate all PSDs

from DC to the signal band edge fS/2.OSR5) Sum the noise powers to determine the total

output thermal noise6) Input noise = output noise (assuming STF is ~1 in

the signal band)

ECE1371 10-33

Noise in a Modulator• Example:

fS = 100MHz, T = 10ns, OSR = 32SNR = 80dB (13-bit resolution)Input Signal Power = 0.25V2 (-6dB from 1V2)Noise Budget: 75% thermal noiseTotal input referred thermal noise:

IN OUT

2 ( 6 ) / 10 20.75 * 10 (43.4 )SNRTHV V

ECE1371 10-34

Noise in a Modulator1) Find all thermal noise sources

21

43no fA

A OA

kTV nC

21

1

4 / 3 1 21

fA Ani

A A

n xkTVC x

22

43no fB

B OB

kTV nC

22

1

4 / 3 1 21

fB Bni

B B

n xkTVC x

2 323

1 1 1 1

2 21 (1 2 1)ffn

f f f f

CCkT kTVC C C C

ECE1371 10-35

Noise in a Modulator2) Find PSDs of the thermal noise sources

For each of the mean square voltage sources,

3) Find transfer functions from each noise source to the output

Assume ideal integrators1

1( ) ( )1A BzH z H zz

2

/ 2x

xS

VSf

( ) 1STF z1 2

21( ) (1 )

1 2 ( ) ( )NTF z z

H z H z

ECE1371 10-36

Noise in a Modulator3) Find transfer functions from each noise source

to the outputFrom input of HA(z) to output…

From output of HA(z) to output…

21

21 2

2

( ) 2 ( ) ( ) ( )

2 ( ) ( ) 21 2 ( ) ( )

iNTF z H z H z NTF z

H z H z z zH z H z

1

1 12

( ) 2 ( ) ( )2 ( ) (1 )(2 )

1 2 ( ) ( )

oNTF z H z NTF zH z z z

H z H z

ECE1371 10-37

Noise in a Modulator3) Find transfer functions from each noise source

to the outputFrom input of HB(z) to output…

From output of HB(z) to output (equal to transfer function at input of summer to output)…

2

1 12

( ) ( ) ( )( ) (1 )

1 2 ( ) ( )

iNTF z H z NTF zH z z z

H z H z

1 22 ( ) ( ) (1 )oNTF z NTF z z

ECE1371 10-38

10-3 10-2 10-1-60

-40

-20

0

20

Normalized Frequency

Mag

nitu

de (d

B)

Signal Band

|NTFi1|

|NTFo1|

|NTFi2|

|NTFo2|

Noise in a Modulator3) Find transfer functions from each noise source

to the outputMost significant is NTFi1

ECE1371 10-39

Noise in a Modulator4) Using the transfer functions, integrate all PSDs

from DC to the signal band edge fS/2.OSRUse MATLAB/Maple to solve the integrals…

/(2 )222 1

1 10

21

( )/ 2

5 2 sin/ 2 2

Sf OSRni

i iS

S Sni

S

VN NTF f dff

f fVf OSR OSR

/(2 )222 1

1 10

21

( )/ 2

7 2 9sin cos sin/ 2

Sf OSRno

o oS

no S S S

S

VN NTF f dff

V f f ff OSR OSR OSR OSR

ECE1371 10-40

Noise in a Modulator4) Using the transfer functions, integrate all PSDs

from DC to the signal band edge fS/2.OSR

(Some simplifications can be made for large OSR)

22 22 sin

/ 2S Sni

iS

f fVNf OSR OSR

2 22 2 3

23 sin cos

/ 2no n S S

oS

V V f fNf OSR OSR OSR

4 sinSfOSR

ECE1371 10-41

Noise in a Modulator5) Sum the noise powers to determine the total

output thermal noiseAssume xA = xB = 0.1 and nfA = nfB = 1.5

With an OSR of 32, first term is most significant (assume A = B = 1/3)

2 22

3 31 1

2.9 1 2 2.93 3TH

A A OA B

kT kT kTVC OSR C OSR C OSR

4 4

5 51

2 85 5B OB f

kT kTC OSR C OSR

2 2 4 4

1 1

9.1 10 6.0 10 2.9 10THA OA B

kT kT kTVC C C

ECE1371 10-42

Noise in a Modulator6) Input noise = output noise (assuming STF is ~1

in the signal band)

=> C1A = 200fF

Assuming other capacitors are smaller than C1A,then subsequent terms are insignificant and the approximation is valid

If lower oversampling ratios are used, other terms may become more significant in the calculation

2 2 2

1

9.1 10 (43.4 )THA

kTV VC

ECE1371 10-43

Noise in a Pipeline ADC• Similar procedure to modulator, except

transfer functions are much easier to compute

• Differences…Input refer all noise sourcesGain from each stage to the input is a scalarNoise from later stages will be more significant since typical stage gains are as low as 2Sample-and-Hold adds extra noise which is input referred with a gain of 1Entire noise power is added since the signal band is from 0 to fS/2 (OSR=1)

ECE1371 10-44

Noise in a Pipeline ADC• Example

If each stage has a gain G1, G2, … GN

S/H stage noise will add directly to Vni1

2 2 2 2 22 2 1 2 2 3

1 2 2 2 2 2 21 1 2 1 2

no ni no ni noNi ni

N

V V V V VN VG G G G G G

ECE1371 10-45

NLCOTD: Gain Booster CMFB

ECE1371 10-46

What You Learned Today1. Noise analysis for switched-capacitor circuits

2. Contributions of both switch noise and OTA noise

Finding a power efficient solutionSignificance of OTA architecture

3. modulator design example

ECE1371 10-47

Some Project Guidelines• General:

1) Corners: Do not need to simulate2) Noise analysis: use calculations to size the

capacitors, but use Cadence to find OTA noise3) Clock Generator: don’t need to design non-

overlapping clock generator, but buffer the ideal clocks and take into account the buffer size for power calculations (if you have other clock phases – not just 1 and 2 – you should indicate how you would generate these)

4) Biasing: Ideal voltage source for VDD/VSS and reference ladder edges; Ideally one current source from which all currents are derived (at least use only one current source per circuit block)

ECE1371 10-48

Some Project Guidelines• Presentation: 15-20 minutes

12 Slides (1 title, 11 content)Focus on major design issues and circuit blocks (what you consider the most important design decisions)

• ReportWe should be able to replicate your circuit with the information provided in the reportGive transistor sizes, preferably annotated on figuresTry to avoid Cadence schematics (if you use them, make them more readable without all the unnecessary annotations)