non-ideal base current in bipolar transistors at low temperatures

130 IEEI! TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. I , JANUARY 1987

Non-Ideal Base Current i.n Bipolar Transistors at LSW Temperatures

Abstract-Bipolar transistors have traditionally been considered not useful in low-temperature applications. This assumption, however, is based upon an incomplete physical understanding of bipolar device physics at low temperatures. This paper shows experimentally that ,-e- combination mechanisms play a substantially larger role in determn- ing base current at low temperatures than at room temperature. The results are explained and quantitatively modeled using cornventior~al Shockley-Read-Hall theory, with the addition of the Poole-FrenLel high field effect. It is concluded that trap levels in the silicon bandg:ip due to bulk traps or interface states are very important in determinhlg bipolar transistor base currents at low temperatures. Non-ideality factors larger than 2 are often observed. Such trap levels will have to lye carefully controlled if low-temperature operation of bipolar transistors is to be considered.

I. INTRODUCTION

C MOS IS CONSIDERED to be the major technology for VLSI in the 1980's because of its low power con-

sumption and speed. However, difficulties do occur as device dimensions shrink below 1 pm. In particular, short- channel effects, hot-carrier degradation, and latchup sus- ceptibility are some of the major concerns. Interconnect delays also become increasingly serious as chip size increases. Cooled CMOS operation has recently been sug - gested as a way to alleviate most of these problems [1]-- [7]. Liquid-nitrogen (LN2) operation provides more ab- rupt turn-on characteristics and hence the possibility 0:'

greatly reduced supply voltages; improved device speec due to higher carrier mobility; a decrease in interconnect delay because of improvements in metal conductivity; improved reliability because most such problems are temperature activated (electromigration for instance); and fi- nally, virtual elimination of latchup because of reduced bipolar gains. For these reasons, there has been considerable recent interest in operating CMOS VLSI computer systems at LN2 temperatures or perhaps in intermediate temperatures between LN2 and room temperature (RT) [5] , [SI. However, in order to optimize the technology for lower temperatures, further investigation of device behavior at lower temperatures is necessary.

Manuscript received June 18, 1986; revised September 5 , 1986. This work was supported by the JSEP under Contract DAAG29-84-K-0047.

J . C. S . Woo and J . D. Plummer are with the Integrated Circuits Lab- oratory, Stanford University, Stanford, CA 94305.

J. M. C. Stork is with the IBM Thomas J . Watson Research Center, Yorktown Heights, NY 10598.

IEEE Log Number 8611322.

BICMOS has also recently gained considerable interest due to its superior speed over CMOS with almost the same level of power consumption. However, it has long been recognized that bipolar transistors suffer serious degradation in current gain at lower temperatures [9]. The dom- inant explanation has been bandgap narrowing in the heavily doped emitter. Other effects such as Shockley- Read-Hall (SRH) recombination can also cause serious degradation of bipolar gain [ 101. Overall, however, there has been very little investigation of bipolar transistors at LN,. It would be an added advantage if BICMOS could operate at lower temperatures if cold electronics are to be used in the future. Thus a better physical understanding of bipolar transistors at lower temperature is important from both the latchup and BICMOS points of view. In this paper, non-ideal base currents in bipolar transistors are investigated at LN2 and RT. It is shown that SRH theory is able to predict the experimentally measured non-ideal base currents provided high field effects are included. It is concluded that recombination currents are much larger at LN, especially for traps with energy levels 0.2 eV or more from the midgap.

11. THEORY AND MODEL There has been very little work on the low-current be-

havior of bipolar transistors at low temperatures. Gonza- lez-Bris et al. studied bipolar behavior at low-temperatures and suggested that non-ideal base currents were due to metal precipitates. However, since the concentration of metal impurities is normally very low in modern integrated circuits, metal impurities are likely dissolved in the silicon and not precipitated. Thus, SRH recombination theory should be able to explain the data. Experiments that we describe later have also shown that non-ideal base currents can have non-ideality (n) factors larger than two. It is well known that simple SRH theory does not give n factors larger than two. However, in the emitter-base space-charge region, large electric fields exist. Thus, SRH recombination can be aided by the Poole-Frenkel effect in that region [ 121. We develop below an expression for recombination currents including this effect and show that it fits experimental data at both LN2 and RT, including data with n larger than 2.

For traps with a single energy level, SR,H recombination current is given by

0018-9383/87/0100-01~~0$01.00 O 1987 IEEE

WOO et al.: NON-IDEAL BASE CURRENT AT LOW TEMPERATURES 131

where xp and x, are the depletion edges; A is the cross- sectional area; and E, and Ei are the trap energy and the by a hole, the barrier for emission of holes to the valence midgap level, respectively. Hole and electron lifetimes band is not lowered by the electric field [12]. However, are given by at very high electric fields, such as under reverse bias,

tunneling through the barrier may be enhanced [ 131. Sim- 1 rp = ~ (2) ilarly , for a trap that is acceptor like, we have

f f p v h N t

where up, a,,, Vth, and N, are the hole capture cross sec- and C,, is not affected by the electric ffield. Since PZ and p tion, electron capture cross section, thermal velocity of in ( 1 ) vary exponentially with potential, the most impor- the carriers, and the trap density, respectively. For a dis- tant contribution to the integral is when the integrand U tribution of traps, D,(E), ( 1 ) is written as

and N , in (2) and ( 3 ) is replaced by D,(E). To include electric field effects, consider a single trap

level in the emitter-base space-charge region. The trap can be either donor-like (i.e., neutral when occupied by an electron) or acceptor-like (i.e., negatively charged when occupied by an electron). For example, if the trap is donor-like, it behaves like a Coulombic well. Thus in the presence of a high electric field, the electron emission coefficient e,, is enhanced due to the Poole-Frenkel effect [ 121, as illustrated in Fig. 1.

where

p = 9 7r€

(6)

€ is the electric field, and E is the high-frequency dielectric constant, which should have a value between the free- space dielectric constant and the silicon static dielectric constant. Note that is identical to the factor used in Shottky-barrier lowering except for a factor of 2, since in the case of the Poole-Frenkel effect, there is no image charge since the trap is fixed in space. By detailed bal- ance, the capture rate C, must also be enhanced by the same amount in the presence of large electric fields, so that

Thus, C,, increases with electric field to the one-half power. Since the trap is neutral when it is not occupied

is maximum. From ( 1 )

U = n; (exp (qViE/kT) - 1)

(9) rp(n + n3 + T A P + PJ

where n, = ni exp (E, - Ei/kT) and p , = ni exp (Ei - Er/kT). When U is maximum, two cases can occur. The first is when both n and p dominate n, and pt . The second is when either n, or p , is the dominating term in the de- nominator. The first case occurs when E,, the trap energy level, is bounded by the electron and hole quasi-Fermi levels q4& and q4& as shown in Fig. 2. The second case occurs when E, is outside the bound of q4h and q4fp. Such traps are not important except when E, is close to either q+& or q+& since otherwise either n, or p , will be ex- tremely large, making U small. Also, for traps of the second type, Urnax has an n factor of roughly one since in this case only the numerator has a strong dependence on the applied voltage. For traps inside the bound of qq5fn and 4% f

132 IEEE T<ANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 1, JANUARY 1987

NORMAL BARRIER +\ CONDUCTION BAND

\ BOrrOM OF

BARRIER .. I '\, UNAFFECTED

\ BARRIER

\ \, BOrrOM OF VALENCE BAND

Fig. 1. The Poole-Frenkel effect on a trap. Because of the electric field, the effective barrier height is decreased by A&. (Solid lines without applied bias; dashed lines with bias.) (After Yeargan and Taylor [17].)

+Depletion R e g m 4

I ! N +

Fig. 2. Position of traps relative to the quasi-Fermi energies at the point where maximum recombination occurs in the space charge region of a forward biased p-n junction. Trap 1 is bounded by +, and +fp whereas trap 2 and trap 3 are not.

Equation (1) can be written as

Z = qA X Urn,, x W*

traps that normally fall outside of q&,, and qq5h at room temperature will be bounded by qq5h and qc$fp at low temperatures. For instance, traps having a trap level about 0.25 eV above or below midgap will not -be important at room temperature since at 0.5 V of forward bias, diffusion current will almost certainly dominate. However, at low temperatures, these traps will be very important. With a distribution of traps, the current is given by (4). In this case an n factor anywhere between 1 and greater than 2 can be achieved. This is because the traps close to but beyond qq5& and qq5& will give an n factor slightly larger than one whereas traps that are bounded by q+,, and q4h give an n factor somewhat larger than 2. Thus, depending on the trap energy distribution, an n factor anywhere between l and larger than 2 can be observed.

111. SIMULATION METHOD In order to study the SRH recombination current at dif-

ferent temperatures, a one-dimensional Poisson equation solver, which was modified from MOSCAP [ 141, was employed. The simulator used a standard finite difference method with the boundary conditions that the potentials outside the space-charge region were fixed by charge neu- trality. The physical constants at different temperatures were taken from [ 141. In the simulator, electron and hole concentrations were approximated by [ 141

where W* is an effective width defined by (12). As the with applied forward base emitter voltage increases, the potential becomes flatter around Urn,, since the electric field de- E(x) = l + 0.2709 exp (-0.8173~). (16) CI-eaSes. Consequently, n and p also increase less rapidly, $* is the normalized potential and is defined to be (& -

without the Poole-Frenkel effect incorporated, the recom- stead of simple Boltzmann statistics is important at low bination current cannot give an factor larger than 2. temperatures, especially if the dopant concentrations are However, with a high electric field and since the trap must high, because the ~~~i energies can then get close to or either be done like or acceptor like, (1 1) becomes even penetrate into the majority carrier bands. The ion-

which implies w" is larger at larger bias. Therefore, E,)/kTwhere ,Vi is the midgap. Such an approximation in-

ni exp (qVL?E/(2kT)) urnax

2- exp (-q@ 1121112/(2kT))

ni exp (qVS,l(2kT>> exp (4P E l(2kT)) 112 112 - -

2 5 . (13)

Since 8 is a positive function of (q5bi - V ) , Urn,, will have an exponential dependence on I/ less than q/(2kT), which will therefore give an n factor larger than two.

The temperature dependence of Urn,, can be understood as follows. As the temperature is lowered, ni decreases exponentially. Therefore, in order for observable current to flow, the applied base-emitter bias must be substantially larger at lower temperatures. This means that q5$, - r& in the space-charge region is large. Therefore,

ized dopant concentrations are given by

where g D and gA are the donor and acceptor degeneracy factors and have values 2.0 and 4.0, respectively. These two equations were used except in the regions with dopant concentrations greater than 2.0 X lo", where impurities were assumed fully ionized since the impurity bands


I L I I I Fig. 3 . Lateral device structures used to study bipolar transistors at small

currents and low temperatures. Both vertical p-n-p and lateral n-p-n transistors were measured. The dimensions a and b range from 2 to 10 pm.

would penetrate into the majority carrier bands at these doping levels [ 151. The quasi-Fermi levels in the depletion region were assumed constant with a difference equal to the applied bias. This is a good approximation because the current density was small in the simulation. The total SRH recombination current was calculated with a numer- ical integration of (4) with both the space and trap distribution quantized.

IV. EXPERIMENTS A standard CMOS process was used to produce the de-

vice structures shown in Fig. 3, which were used to study the low-temperature behavior of bipolar transistors at low currents. The n+ and p+ regions were implanted with As and B, respectively. A field implant was used in the p- substrate with a surface concentration of 8.0 X 1016/cm3. The bulk concentrations of the p- and n-regions were 8.0 X 10'4/cm3 and 1 .O X respectively. The dimensions of a and b ranged from 2 to 10 ,urn. Both the vertical p- n-p and lateral n-p-n transistors were characterized from LN2 to 350 K. The measurements were done with a base to collector reverse bias of 0.2 V. The temperature sta- bility during the experiments was better than kO.5 K. The collector currents showed ideal characteristics at all temperatures with an IZ factor equal to 1 within 5 percent, which was also used to confirm the temperature readings during the measurements. The vertical p-n-p transistors showed ideal behavior from liquid-nitrogen temperature (LN,) to 350 K. The gain decreased from 200 to 2 from room temperature (RT) to LN2. The lateral n-p-n transistor was also close to being ideal (Le., the n factor of the base current was - 1 in the measurement) at RT. How- ever, it showed a large non-ideal base current at LN, as shown in Fig. 4. Transistors with different a and b values had identical base currents up to A. The base resis- tance is large, but it had little effect in the small current regime discussed here.

Since only the lateral device showed non-ideal behavior in its base current, surface effects (interface traps at the oxide-silicon interface) were strongly suggested as being responsible for the phenomenon. It should be pointed out, however, the effects described here can be due to either surface or bulk traps. Figs. 5 and 6 show the measured n- factors in the n-p-n base current and the applied V,, necessary to produce Z, = 1 nA. The n-factor at LN2 is 2.5. Note that an n-factor of 1 at very low bias means that the

10'2 / 10-'2 I I I I I I I I I

0.8 0.88 0.96 1.04 1.12 1.2

VBE(V)

(a)

0 -0.16 -0.32 -0.48 -0.64 -0.80

VEE (V) (b)

Fig. 4. Gummel plot of the lateral n-p-n transistor at RTand LN,. The base current shows a large nonideal Component at LN,.

diffusion component is dominating in the entire measurement range and the non-ideal behavior is not observable at these currents.

Additional data is provided by the low-temperature characteristics of advanced self-aligned vertical bipolar transistors fabricated at IBM Yorktown. These devices were made with polysilicon contacts to the emitter and base regions and are intended for high-performance bipolar logic applications. The bipolar gain for these devices versus collector current at different temperatures is shown in Fig. 7. It can be seen that these are high-gain transistors at room temperature and the gain decreases as the temperature is lowered, which is expected [9]. Fig. 8 shows the Z-V characteristics of the base current of one of these n-p-n transistors over the temperature range of 80-390 K. Measurements of this type on devices with different perimeter to area ratios have shown that the non- ideal part of Is is related to the perimeter area, in contrast to the diffusion component of the base current. This sug- gests that the nori-ideal current is due to traps at the Si- SiOz interface. At room temperature, the base current has a substantial non-ideal recombination component with a non-ideality factor around 2, which increases to approxi- mately 2.5 at LN, as shown in Fig. 9.

134 IEEli TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 1, JANUARY 1987

2.8 Simulation

50.0 100.0 150.0 200.0 250.0 300.0 350.0

Temperature

3

Fig. 5. n factor of the non-ideal component of base current versus temperature for the lateral n-p-n transistor in Fig. 3 (a = 2 pm, b = 2 ptn). (n = 1 .O means that the base current shows ideal behavior for the entin: measurement range.)

- 0.0

0

0

100.0 150.0 200.0 250.0 300.0 550.0 i

Temperature 3

Fig. 6. The emitter to base bias when the base current is 10 nA versus temperature for the n-p-n transistor in Fig. 3 (a = 2 ptn, b = 2 prn).

2 I I I I 1 I 393 0 (K)

I -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1

Log (1,) (amp)

Fig. 7. Bipolar gain 0 versus collector current I , for a self-aligned vertical n-p-n transistor.

.2 .4 .6 .8 1.0 1.2

Vbe (volt)

Fig. 8. I B versus V,, at different temperatures for the self-aligned vertical n-p-n transistor.

Since interface states were strongly suspected as caus- ing the non-ideal behavior in both the lateral and higher gain vertical devices, a distribution of traps similar to that commonly observed in MOS structures was used in the simulator previously described to try to model these results. Studies of the Si-Si02 interface have suggested that a U-shaped distribution of traps is commonly observed [ 101 such as that shown in Fig. 10. C-V measurements on the wafers used in these experiments confirmed this shape for the trap distribution (QJ. Using this trap distribution and (4), the non-ideality factor and VBE values corresponding to the experimental conditions for the lateral devices in Figs. 5 and 6 were calculated. The results are also shown in Figs. 5 and 6. The agreement between the measurements and the simulations is very good. For T larger than 250 K, the calculated results begin to diverge from the measurements. This is to be expected since diffusion


1.6 1 L I I I I I I I I I I I l I I I l

40 80 120 160 200 240 280 320 360

Temperature (K)

Fig. 9. n factor of the non-ideal component of the base current versus temperature for the device as described in Figs. 7 and 8.

10’0 -

10s -

I

(ev)

Fig. 10. Interface trap density versus energy used in the simulations. A standard U-shape distribution was used.

currents are the dominating currents at these temperatures. It is likely that even better agreement between ex- periment and theory in the SRH dominated region could be achieved by adjusting the shape of the trap distribution in the simulator. Similar agreement has been obtained with a somewhat flatter U-shape distribution of interface traps for the vertical n-p-n transistor described above and in Figs. 7-9. Since the technologies used in the vertical and lateral devices were very different, the shapes of the distribution of interface traps needed to match the experimental results were expected to be different.

Both Fig. 3 and Fig. 8 show that the slope of the base current at low bias is not constant. This can be understood

1

(eV)

Fig. 11. Interface trap density distributions for different annealing conditions. Curve (a): non-annealed. Curve (b): annealed at 220°C for 1 min. Curve (c): annealed at 260°C for 1 min. Curve (d) : annealed at 300°C for I min.

E“ -0.4 -0.2 0.0 0.2 0.4 Ec

by noting the behavior of G in (13). As V,, approaches $bi, the built in potential of the base-emitter junction, the change in 8”’ becomes very large, i.e., €’” varies super- linearly with V,, and the change ‘in €’I2 becomes more rapid as V,, increases. Thus (13) would predict an in- creasing n factor with respect to VBE, which was observed.

To further test this model, additional experiments and calculations were done on lateral transistor structures similar to those previously described, but with different interface state densities. It is well known that the forming gas annealing step commonly used at the end of device

136 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 1, JANUARY 1987

. " 0 -0.16 -0.32 -0.48 -0.64 -0.80

VBE(V)

(a)

-0.32 -0.48 -0.64 -0.80 VBE(V)

(C)

0 -0.16 -032 -0.48 -0.64 -0.80 VBE (V)

( 4

Fig. 12. Measurements of bipola;. transistors with different annealing conditions at room temperature. (a) Non-annealed sample. (b) Annealed at 220°C for 1 min. ( e ) Annealell at 260°C for 1 min. (d) Annealed at i ,

300°C for 1 min.

processing reduces interface states dramatically. Mea- surements on unannealed or partially annealed devices should, therefore, produce dramatically different results if the Si-Si02 interface recombination is responsible for the effects observed here.

Fig. 11 shows Di, distributions on unannealed, partially, and fully annealed MOS capacitors. Quasi-static C-V measurements were used to extract the midgap Di, values [16]; the U-shaped distribution is assumed in the simulator calculations as was previously done. (These measurements were actually done on different wafers than the transistors described below since suitable structures were not available on the transistor wafers. The results are believed to accurately represent Dit distributions in the transistor structures, however, since identical anneal times and temperatures were used in both set of wafers.) Fig. 12 shows measurements of transistors at room temperature annealed under conditions similar to Fig. 11. It is apparent that the non-annealed devices show large non- ideal base current components, whereas the fully annealed samples show very ideal behavior. This is ex-

pected since for the unannealed sample, the number of traps incorporated between qc&, and q4fi, in the space- charge regions is large, whereas the corresponding number of traps for the annealed sample is small. Figs. 13 and 14 show the measured n-factors of the recombination currents and the VBE values need to produce an Z, of 0. l nA. Also shown in the figures are the corresponding results from simulation using the Dit distributions in Fig. 11 as inputs. Again the agreement is good. Note that the n factors for the unannealed and partially annealed samples show unusual behavior. This is modeled in the simulations by the shape of the trap distribution close to the band edges. The partially annealed samples have a steeper U- shape distribution of interface traps, which produces the drop in the B factor as the temperature is reduced below 100 K. Even with n factors around 1.5 at LN2, the recombination current is large and therefore significant. Also, for the partially annealed cases of curves (c) and (d ) at high temperatures, the diffusion component dominates even at very low bias and the non-ideal behavior is not observed.


2.2 I o Measurement (a) 0 Measurement (b) 0 Measurement (c) A Measurement Id) i . .

1.2 -

I I

“O I 0.8 L I , I , I J

50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 Temperature iKI

Fig. 13. n factors of the non-ideal component of the base current versus temperature for the transistors annealed as shown in Fig. 11. (n = 1 .O means that the base current shows ideal behavior for the entire measurement range.)

1 .o

o Measurement (c)

0

0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0

Temperature (K)

Fig. 14. VBE at a base current of 10 nA versus temperature for the transistors annealed as shown in Fig. 11.

V. CONCLUSION It has been shown that non-ideal base currents can be

much more important in bipolar devices at LN2 than they are at RT. Such effects can be modeled successfully using standard SRH theory, if high field effects are included. The specific n-p-n lateral and vertical devices studied here appear to be dominated by surface recombination in the base-emitter space-charge region. Because of this, the

magnitude of the non-ideal base current is strongly dependent upon the magnitude and shape of the interface state distribution at the Si-Si02 interface. It is possible that other vertical devices may show similar behavior due to bulk traps if the density of traps due to heavy metals is significant. Many of the metals commonly found as impurities in silicon have energy levels in the bandgap around 0.2 to 0 . 3 eV above or below midgap and hence would be very important at low temperatures where applied biases are higher. The results of this work suggest that very careful attention must be paid to both bulk and interface traps if bipolar devices are to be operated at low temperatures, particularly if low-current operation is con- templated.

ACKNOWLEDGMENT

The authors acknowledge helpful discussions with J. Watt and A. Henning.

REFERENCES

[ l ] R. W. Keyes, E. P. Harris, and K. L. Konnerth, “The role of low temperatures in the operation of logic circuitry,” Proc. IEEE, vol. 58, pp. 1914-1932, 1970.

[2] F. H. Gaensslen, V. L. Rideout, E. J . Walker, and J . J . Walker, “Very small MOSFET’s for low-temperature operation,” IEEE Trans. Electron Devices, vol. ED-24, pp. 218-229, 1977.

[3] F. H. Gaensslen and R. C . Jaeger, “Behavior of electrically small deoletion mode MOSFETs at low temperature,” Solid-State Elec- tron., vol. 24, pp. 215-220, 1981.

141 A. Kamear. ”Miniaturization of Si MOSFET’s at 77 K,” IEEE Trans. c 1

ElectronYDkvices, vol. ED-29, pp. 1226-1228, 1982. [5] S. Hanamura, M. Aoki, T. Masukara, 0. Minato, Y. Sakai, and T.

Hayashida, “Operation of bulk CMOS devices at very low temperatures,” in Dig. Tech. 1983 Symp. VLSI Technol., pp. 46-47, 1983.

[6] J . W. Schrankler, J . S. T. Huang, R. S . L. Lutze, H. P. Vyas, and G. D. Kirchner, “Cryogenic behavior of scaled CMOS devices,” in IEDM Tech. Dig., pp. <74-577, 1984.

[7] S . K. Tewksbury, “n-channel enhancement-mode MOSFET characteristics from 10 to 300 K,” IEEE Trans. Electron Devices, vol. ED- 28, pp. 1519-1529, 1981.

[8] I. Kato, H. Oka, S. Hijiya, and T. Nakamura, “1.5 pm gate CMOS operated at 77 K , ” in IEDM Tech. Dig., pp. 601-603, 1984.

[9] W. P. Dumke, “The effect of base doping on the performance of Si bipolar transistors at low temperatures,” IEEE Trans. Electron De- vices, vol. ED-28, pp. 494-500, 1981.

[lo] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.

[ l l ] C. Conzalez-Bris and E. Muiioz, “Temperature dependence of non- ideal component of base current im micropower n-p-n transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1503-1505, 1984.

[12] A. G . Milnes, Deep Impurities in Semiconductors. New York: Wiley-Interscience, 1973.

1131 G. Vincent, A. Chantre, and D. Bois, “Electric field effect on the thermal emission of traps in semiconductor junctions,” J. Appl. Phys., vol. 50, no. 8 , pp. 5484-5487, 1979.

[I41 F. H. Gaensslen and R. C. Jaeger, “Temperature dependent thresh- old behavior of depletion mode MOSFET’s,” Solid-State Electron., vol. 22, pp. 423-430, 1979.

[15] D. S. Lee and J. G. Fossum, “Energy-band distortion in highly doped silicon,” IEEE Trans. Electron Devices, vol. ED-30, pp. 626-634, 1983.

[16] M. L. Reed and J . D. Plummer, “Kinetic studies of silicon-silicon dioxide interface trap annealing using rapid thermal processing,” Proc. MRS, 1985.

[17] J . R. Yeargan and H. L. Taylor, “The Poole-Frenkel effect with compensation present,” J . Appl. Phys., vol. 39, no. 12, pp. 5600- 5604, 1968.

138 IEEE TRPNSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 1, JANUARY 1987

Jason C. S. Woo (S’81) was horn in Hong Kong, Dr. Plummer is a member of Tau Beta Pi, Sigma Xi, American Physical on September 29, 1958. He received the B.A.Sc. Society, and the Electrochemical Society. He has received three best paper degree in engineering science from the University awards at the International Solid-state Circuits Conference, and was the of Toronto, Canada, in 1981 and the M.S. degree Technical Program Committee Chairman for the 1980 ISSCC. from Stanford University in 1982. He is presently working toward the Ph.D. degree in electrical engineering in the area of low-temperature device physics at the Stanford University Integrated Cir- cuit Laboratory.

James D. Plummer (M’71-SM782-F’8S) was born in Toronto, Canada, on December 3, 1944. He received the B.S. degree in 1966 from the Uni. versity of California, Los Angeles, and the M.S and Ph.D. degrees, both in electrical engineering, from Stanford University in 1967 and 1971, respectively.

He is presently a Professor in the Electrical En- gineering Department, and the Director of the Ir- tegrated Circuits Laboratory at Stanford Unive,- sity. His current research interests center on has;c

modeling of semiconductor processes including oxidation, epitaxy, and icn implantation, on the physics and technology of scaled bipolar and MCS devices, and on high-voltage devices and integrated circuits. He is the 81-

thor of numerous technical papers in these areas.

Johannes M. C. Stork (S’79-M’82) was born in Soest, The Netherlands, in 1954. He received the Ingenieur degree in electrical engineering from the Delft University of Technology, Delft, The Neth- erlands, in 1978 and the Ph.D. degree from Stan- ford University, Stanford, CA, in 1982. His thesis work at Stanford involved the device physics and technology of bipolar structures for VLSI.

During the academic year 1977-1978, he worked at the Philips Research Laboratories, Briarcliff Manor, NY, on the modeling of charge

storage in MNOS devices. Since 1982, he has been employed in the bipolar activities at the IBM Thomas 3 . Watson Research Center, Yorktown Heights, NY. His most recent activities focus on the analysis and design of exploratory devices for high-performance bipolar VLSI.

non-ideal base current in bipolar transistors at low temperatures

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