nonideal effects report
TRANSCRIPT
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ECE626 Project
Switched Capacitor Filter Design
Hari Prasath Venkatram
Contents
I Introduction 2
II Choice of Topology 2
III Poles and Zeros 2
III-A Bilinear Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
IV Dynamic Range and Chip Area Scaling 5
V Cascade of Biquads 10
V-A Linear Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V-B High-Q section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V-C Low-Q section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V-D Opamp-Macro-Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VI Charge Injection and Switches 15
VI-A Switch Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15VI-B Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15VI-CChoice of WL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17VI-D Choice of Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17VI-E Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VI-F Clock-Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18VIIOffset 20
VII-AFirst Order Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VII-BBiquad Low Q - Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VII-CHigh-Q Biquad Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VII-DFilter Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VIIISlew-Rate 22
IX Finite Gain 24
X CDS 27
XI Finite Bandwidth 27
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I. Introduction
The Low pass switched-capacitor filter design is discussed. The first section discusses the choice oftopology to achieve the filter specification with minimum components and in a most economical way.Second section discusses about the derivation of H(z) and the location of poles and zeroes in z-domain.Section three discusses about dynamic range scaling and area scaling performed on this filter. Sectionfour discusses about the macro-model implementation of the filter. Section five discusses about the
various non-ideal effects in the switched-capacitor filter. Section six discusses the choice of opamp-topology and the design of the opamp stage. Section seven concludes the report.
II. Choice of Topology
The specification for the low-pass filter is
Parameter ValueSampling Frequency 100 MHz
DC Gain 0 dBPassband 0-5 MHz
Ripple in Passband 0.2 dBStopband 10 -50 MHz
Gain in Stopband -50 dBMinimum Capacitor 0.05 pF
The order of Butterworth filter required to meet this specification is 11.
The order of Chebyshev filter required to meet this specification is 6.The order of Elliptic filter required to meet this specification is 5.The most economical filter is elliptic filter.
III. Poles and Zeros
The Bilinear transform is used for the design of sampled-data filter from the analog counterpart.The bilinear transform relationship between s domain and z domain is
s =2
Ttan(
T
2)
This translates to the following pass-band and stop-band specification for the analog 5th order ellipticfilter. Sampling frequency is 100 MHz.
pass = 200 tan(
20
) Mrad/s
stop = 200 tan(
10) Mrad/s
To give some margin, the filter was designed for 0.1 dB passband ripple and 51 dB stopband atten-uation. The transfer function of the fifth order s domain filter is
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0.5 1 1.5 2 2.5 3 3.5 4
100
80
60
40
20
0
Normalized Frequency axis in rad/s
Magn
itu
de
indB
5th
Order Elliptic Filter in sdomain
0.5 1 1.5 2 2.5 3 3.5 4
3
2
1
0
1
2
3
Normalized Frequency axis in rad/s
Phase
in
radians
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0.1
0.05
0
Fig.1.5th
OrderEllipticFilterinsdomain
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0.1 0.08 0.06 0.04 0.02 0 0.02
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.020.0420.070.10.140.2
0.3
0.55
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.020.0420.070.10.140.2
0.3
0.55
PoleZero Map
Real Axis
ImaginaryAxis
Fig.2.
Pole-Zeroinsdomain
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A. Bilinear Transform
Trapezoidal intergration is a better approximation in integration. This approximation is used toderive the bilinear s-to-z transformation.
sa =2
T
z 1
z + 1
This mapping was used to map s-domain poles to z-domain poles. The following tabular columnlists the s-domain and z-domain poles. The s-domain poles are normalized to 2/T.
Poles & Zeros s-domain z-domainp1,2 -0.02027 0.1695i 0.9075 0.31699ip3,4 -0.06725 0.1179i 0.85130.20455ip5 -0.0974 0.8224z1,2 0.4337i 0.68334 0.73009i
z3,4 0.2833i 0.85133 0.52462iz5 -1
The quality factor of s-domain poles are 4.2 and 1 respectively for the two complex poles. The poleand zero closer to each other were used for forming the biquadratic section.
The z-domain transfer function is
H(z) =0.003286z5 0.0068z4 + 0.004133z3 + 0.004133z2 0.0068z + 0.003286
z5 4.34z4 + 7.675z3 6.898z2 + 3.147z 0.5828
The frequency response of the z-domain filter is shown in the following figure. The fifth-order transferfunction was designed as a cascade of a linear section and two second order sections. The transferfunctions of the linear and second order sections are given below. The poles and zeros closer to eachwere used to form the biquadratic section.
H1(z) = 0.1486z + 1
z 0.822446
H2(z) = 0.1486 z2
1.70266z + 1z2 1.81517z + 0.924196
H3(z) = 0.1486z1 1.3666z + 1
z2 1.70274z + 0.76667
IV. Dynamic Range and Chip Area Scaling
The dynamic range scaling is performed to maximize the swing at each node of the filter. Thisis performed by scaling the capacitors connected to the output of each opamp by peak gain of thecorresponding stage with respect to the input. All the capacitors that are either switched or connectedpermanently to the output of the opamp is scaled by this factor. [1]
After performing dynamic range scaling for each output node, area scaling is performed at the inputterminal of each opamp. The smallest capacitor connected to the input of the opamp is scaled such
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1400
350
300
250
200
150
100
50
0
Normalized Frequency ( rad/sample)
Phase
(d
egrees
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1120
100
80
60
40
20
0
20
Normalized Frequency ( rad/sample)
Magn
itu
de
(dB)
5th
Order zdomain Elliptic Filter using Bilinear Transform
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.090.1
0.05
0
Fig.3.5th
OrderEllipticFilterinzdomain
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1 0.5 0 0.5 1
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
Real Part
Imagi
nary
Part
ZDomain Pole Zero Map
Fig.4.
Pole-Zeroinzdomain
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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 107
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Frequency in Hertz(Hz)
Magnitudevoi
vi
Individual Responses before DR Scaling
1 2 3 4 5 6
x 106
0.6
0.8
1
1.2
1.4
1.6
Fig
.5.
MagnitudeRespons
ebeforeDynamic-Range
Scaling
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0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 107
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency in Hertz(Hz)
Magnitudevoi
vi
Dynamic Range Scaled Ouput
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
x 106
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1
Fig.6.
Dynamic
RangeScaledOutput
V Cascade of Biquads
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V. Cascade of Biquads
A linear section and two biquadratic sections were used for simulating the z-domain transfer function.Since one of the poles has a Quality factor of 4.2, a high-Q biquad structure was used for this section.The following section explains the transfer function and the macro-model level implementation. Thefirst section is a low-pass filter to reject high frequency noise. The high-Q structure is placed in themiddle. This order was chosen to reduce sensitivity to power supply noise and fundamental noise.
A. Linear Section
The linear section was implemented as follows [2].
H1(z) = 0.1486z + 1
z 0.822446
The Linear section was implemented with the following structure. The dynamic range scaled andarea scaled capacitor values are shown in the figure 7.
B. High-Q section
The high-Q biquad was used for the pole with quality factor of 4.2. The transfer function imple-mented using this structure is shown in the figure 8 [2].
H2(z) = 0.1486
z2 1.70266z + 1
z2 1.81517z + 0.924196
The amount of capacitance spread is higher in a low-Q structure. This is because of the fact thatthe large damping resistor Q
0. This can be eliminated in the high-Q structure. The general transfer
function for the high-Q biquad is as follows.
H3(z) = (K3)Z
2 + (K1K5 + K2K5 2K3)z + (K3 K2K5)
(1)z2
+ (K4K5 + K6K5 2)z + (1K5K6)
The above two expressions were compared to derive the values of Ki. Dynamic range scaling and Areascaling was performed for the 5th order filter and the capacitor values are shown in the figure. Forclarity, single-ended version is shown. The implementation was done differentially.
C. Low-Q section
The low Q section was placed in the end. The transfer function implemented using this structure is
shown in the figure 9.
H3(z) = 0.1486z2 1.3666z + 1
z2 1.70274z + 0.76667
The low-Q biquad is derived from its continuous-time counterpart Tow-Thomas Biquad. The resistorsl d ith it h d it d th t t i d f i l ti th b t f
C C
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+
Vinp
Vo1p
1
1
2
22
1C2
CA1
C3
Vinn C1
Vinp
1
1
22
C2
Vinn
C1
2
1C3
CA
Vo1p1
CAC2C1 C3Cap
Initial
DR
Area
(pF)
1 0.1807 0.3615 0.2158
1.6742 0.1807 0.3615 0.3614
0.4632 0.1000 0.1000 0.050
All Capacitor values in pF
Fig. 7. Linear Section
Comparing the above two expressions, the values ofKi, were determined and dynamic range scaling and
area scaling was performed. The corresponding Low-Q strucuture used in the 5th
order elliptic filter isshown in the following figure. Single-ended version is shown for clarity. However, implementation wasdone in differential version. The Fifth-Order filter used for simulation with switch-sharing is shown inthe figure 10
D. Opamp-Macro-Model
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+
+
+
+
Voff
Voff
Vo1
Vo2
1
1
1
2
2
2
5
4
6
3 C
1
C2
K1
K
3
K4
K5
K6
C1
C2
F)
AllC
apacitorvaluesare
inpF
0.1
338
0.1
486
0.3
301
0.3
30
1
0.2
295
1.0
0
1.0
0
0.2
241
0.2
489
0.3
144
0.3
05
6
0.2
186
0.9
256
0.9
521
0.0
512
0.0
50
0.0
50
0.0
719
0.0
61
3
0.2
117
0.1
912
Fig.8.High-QSection
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+
+
+
+
Voff
Voff
Vo1
Vo2
1
1
1
2
2
2
2
1
5
4
6
3 C
1
C2
K1
K3
K4
K5
K6
C1
C2
F)
0.4
252
0.1
939
0.2
887
0.2
887
0.3
042
1.0
0
1.0
0
0.4
049
0.1
846
0.2
887
0.5
105
0.3
042
1.7
67
1.0
0
0.0
70
0.0
50
0.0
50
0.1
382
0.0
823
0.3
061
0.2
707
AllCapacitorvaluesare
inpF
Fig.9.Low-QSection
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von
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vinn
vinp
vdiffgmvdiff
gmvdiff
R C
R C
+
vop
von
vop
Vcm
VcmfbVcmfb
Rc
Rc
Fig. 11. Opamp Macro-Model
and bandwidth.
VI. Charge Injection and Switches
A. Switch Sizing
Considering the model shown in the figure 13 for a typical switch. The voltage at the end of 1 is
v(nT) = vin(nT)(1 e
T
4RonC )
This voltage on the capacitor is discharged during 2 into the virtual ground [1]. The charging of thefeedback capacitor follows the similar expression. Hence the overall transfer function is
H(z) = (1 eT
4RonC )2Z1
1 Z1
For the error to be less than 0.1%, RC product should be less than T15
. The largest capacitor is 0.6pF. Switches were designed with minimum channel length. The sampling frequency is 100MHz.
Ron 1
15fc0.6 1012
1.5k
B. Charge InjectionThe relation between Ron and qch is
Ronqch =L2
L2
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0 0.5 1 1.5
100
90
80
70
60
50
40
30
20
10
0
Normalized Frequency in rad/s
Mag
nitu
de
indB
Matlab and Cadence Response
0.05 0.1 0.15 0.2 0.25 0.3
0.1
0.05
0
Matlab Response H(z)
Cadence MacroModel Response
50 dB Line
Fig.12.
Matla
bandCadencePlots
C
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VinRon Ron
Ron Ron
C
VinC
1
2 1
1
1
2
2
2
+
C
+
Fig. 13. Switch-Model
Substituting the values for fc,L and and assuming that half of the channel charge flows into thecapacitor, we get
Verror =7.5 (0.18)2 100 106
273.8 108
= 0.825mV
C. Choice ofWL
The ON-resistance of the switch and the calculation of the switch size is shown below. The value ofON-Resistance calculated before was used.
Ron =1
CoxWL
(Vgs Vtn)
W
L=
1
2.738 8.5 105(1.8 0.4) 3
W 0.54m
D. Choice of Switch
1.8V supply and 0.18 TSMC model was used for simulations. To maximize the signal input to channel charge and clock-feedthrough was approximately 1.2 mV. The transient simulation shows the
d t l f 1 V f th b t t it h i d d t f th i l H B t t it h
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pedestal of 1 mV for the bootstrap switch independant of the signal. Hence, Bootstrap switches wereused for the filter to minimize the distortion. The third harmonic distortion was at 89 dB below thefundamental for a in-band signal tone.
E. Harmonic Distortion
The harmonic distortion at the output of each switch was simulated. The sampling frequency is
100MHz. The switches were sized according to the sampling bandwidth requirement. A single toneat 3
64 fs and 100mV peak amplitude with a common mode of 0.9 V was given at the input of each
switch. 64-point DFT was performed at the output of each switch. The following tabular columnshows the distortion performance of each switch.
Switch 1st(dB) 2nd(dB) 3rd(dB) 4rd (dB) 5th(dB)NMOS + Dummy -20 -47.2 -58.23 -70.432 -81.7Trans + Dummy -20 -65.2 -86.5 -94.6 -94.8
Bootstrap + Dummy -20 -86.08 -109.7 -118.8 -114.1The following figure 16 shows the transient response of the five switches considered and the effect
of charge injection and clock feedthrough. This can be seen as a pedestal in the hold-mode. Thisindicates the amount of charge injection resulting from channel charge and the clock-feedthrough.The boot-strap switch has the least amount of charge-injection. The pedestal value is 1.2mV and isindependant of the input voltage.
F. Clock-Generator
The following non-overlapping clock generator was used for generating the clock-phases.
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Vin Vin
Vin Vin
Vdd
Vdd
Cboot
C
C
CC
C
1
1
1
1
1
1
11b 1b
1b
1b
1b
1b1b
1b
Vin
Sampling Switch
Clk
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1
22b
1b
Fig. 15. Non-Overlapping Clock Generator
VII. Offset
The Effect of offset was simulated with Vin=0 and a input referred opamp offset voltage of 1 mV.
The following estimates were used in determining the effect of the offset of each stage of the filter [1].A. First Order Stage
During Steady state, the charge entering the virtual node due to the capacitors which are switchedmust be zero. Hence
VoffC2 + (Vo1 Voff)C3 = 0
Vo1 = Voff1(C2
C3+ 1)
Assuming 1 mV offset and using the values of C2 = 362f F,C3 = 215f F, The value of the steady stateoutput voltage due to offset is 2.65 mV. This can be observed from the simulation result also.
B. Biquad Low Q - Stage
The effect of input referred offset voltage was simulated with Vin=0 and an input referred opampoffset voltage of 1 mV. The following estimates were used in determining the effect of the offset.
VoffK1 + (Vo1 Voff)K4C1 = 0
Vo1 = (K1K4
+ 1)Voff
= 2.475mV
For the intermediate node of the low-Q biquad, the effect of the offset is derived as follows,
VoffK5 + (Vo1 Voff)K6 = Vo2K5
V (V V )K6
V
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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 107
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
Time in second(s)
V
oltage(
V)
Sample and Hold Output and Charge Injection
1.06 1.07 1.08 1.09 1.1 1.11
x 107
0.904
0.906
0.908
0.91
0.912
0.914
0.916
InputNMOS
TRANSGate + Dummy
TRANSGate
Bootstrap +Dummy
NMOS +Dummy
Bootstrap
Fig.16.TransientOutputResponse
K V + K V K C 0
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K1Voff + K4Vo2 K4C1 = 0
Vo2 = (1 +K1K4
)Voff
= 1.432mV
Vo1 = Voff
= 1mV
Transient simulation was performed with input referred offset and the steady state output voltages areshown in the figure. The simulated steady state values and the estimated values match.
D. Filter Offset Voltage
The following equations were derived for the steady filter output voltage with input referred offsetin each opamp. The derivation is from the first order section.
Vo1 = (1 +C2C3
)Voff = 2.67mV
Vo2 = Voff = 1mV
Vo3 = VoffK1,2K4,2
(Vo1 Voff) = 0.4mV
Vo4 = (V
o5 V
off)
K6,3
K5,3 V
off= 0.05mV
Vo5 = VoffK1,3K4,3
= 2.475mV
Ki,j represents the coefficient i in the section j.
VIII. Slew-Rate
The slew rate is caused by the opamps maximum current output. Thus, the rate at which the
output node is charged is fixed at a particular rate. For a sinusoidal input, the rate of increase of theinput is
SR =dvin
dt= Vpin
The maximum slew-rate occurs at maximum passband frequency and peak amplitude. Therefore, themaximum step in one time period is
v = VpinT
v
t=
VpinT
aT/2
3x 10
3 Transient Output of Individual Stage with Opamp Offset
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0 0.5 1 1.5 2 2.5 3
x 106
4
3
2
1
0
1
2
3
Time in second(s)
OutputVoltage(V)
2
1
0
1
2
3
4
5x 10
3
Transie
ntSettlingOutputVoltage(V)
Filter Transient with Opamp Offset Voltage
2.6 mV
0.4 mV
0.05 mV
1 mV
2.475 mV
Vinp1 1
C2 C3
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+
Vo1p
1
2
22
CA
1Vinn C1
Fig. 18. Slew-Rate Estimation
Slew-Rate - Method 2
The Linear section has the worst-case slew-rate limitation. Consider the linear section shown in thefigure 18. Assuming the opamp has 20% of one-clock phase to slew and maximum input of 1 V, Theworst-case slew-rate is derived as follows,
qin = vin(C1 + C2)
vout =
C1 + C2
C3 + CAvin
SRmax =0.2vin
0.5 0.2 T /2
SRmax = 400V/ s
Slew-Rate Fundamental(dB) 3rd(dB) 5th(dB)50V/s 2 -22 -34
100V/s 2 -40 -50150V/s 2 -75 -85200V/s 2 -78 -87
The distortion for slew-rates greater than 150V/s is limited mostly by the switch-non linearity. Togive a safety margin of 30V/s, The slew-rate required for the opamp is 180V/s.
IX. Finite Gain
The Effect of finite gain was analyzed with respect to the integrator [3], [4]. The effect of finite DCgain on the poles of the filter is considered. The Integrator transfer function with finite DC gain isgiven by
H(z) =C1Z
(C2 +C1+C2A0
)Z C2(1 +1
A0)
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0.5 1 1.5 2 2.5
x 10
7
100
90
80
70
60
50
40
30
20
10
0
Frequency in Hertz
Magn
itu
de
indB
Distortion due to SlewRate
SR = 50 V/ s
SR = 100 V/ s
SR = 150 V/ s
SR =200 V/ s
Fig.19.
Distor
tionduetoSlew-Rate
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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 107
90
80
70
60
50
40
30
20
10
0
Frequency in Hertz(Hz)
Magn
itude
Response
indB
Effect of Finite Gain(1001000) and Bandwidth 500MHz
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
0.6
0.4
0.2
0
Increasing Adc
Fig.20.F
initeGainEffect
Assuming the DC gain as 1000 and highest pole frequency as 5 MHz, the normalized pre-distortionvalue needed is pi
20000. The pre-distorted poles are given by
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Pole Ideal Pre-Distorted1,2 -0.0168 0.1650i -0.0160 0.1650i3,4 -0.0575 0.1151i -0.0570 0.1151i5 -0.0848 -0.0840
The effect of finite DC-gain changes s to s+. The effect of this can be analyzed in the biquad.The Denominator in the biquadratic transfer function changes to
s2 + (0Q
+ 1 + 2)s + (2 +
01Q
+ 12)
The new pole Q can be compared with ideal transfer function.
0Q = 0
Q + 1 + 2
1
Q=
1
Q+
1
0AT(
C1C2
+C1C2
)
The effect of DC-gain will be large in a high Q. The elliptic filter has two biquads. The quality factoris approximately 1 and 5. Hence the pass-band deviation due to the finite gain can be derived as
1 2 1A0
Rp = 1 +2Q
A0
For the given passband ripple of 0.2 dB, the minimum DC-gain required for the high-Q biquad is 54 db approximately. To have some margin due to variation in DC-gain, 60 dB DC-Gain was chosen
for the opamp used in the filter. The finite-dc gain affects the passband poles with high-Q. This canbe clearly observed in the figure. 20. The effect of scaling with finite opamp gain is shown in thefigure. 23. We can see that the dynamic range scaled system is more close to ideal response whencompared with unscaled filter response.
The predistorted and ideal response is shown in the figure. 22.
X. CDS
The finite gain error and phase error in the integrator can be minimized using CDS or CLS. The
CDS integrator shown in the figure 21 has a constant gain error and is independant of the frequency [5].The integrator and the charge transfer expression are given in the figure 21
XI. Finite Bandwidth
The finite bandwidth effect with a single-pole finite DC gain amplifier.
C2
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+
C3
C1
Vin
2
1
1
1
2
1
1
C1 C2 C3
Vin(n-1) +V0(n-1)/A V0(n-1)(1+1/A) V0(n-1)
V0(n-1/2)(1/A)2 V0(n-1)(1+1/A) V0(n-1/2)(1+1/A)
1 Vin(n) +V0(n)/A V0(n)(1+1/A) V0(n)
C
Fig. 21. CDS- Integrator
Integrator. Single-pole amplifier is assumed with finite DC Gain.
Vo(Z)
Vi(Z)=
Z1
1 Z1
Vo(Z)
Vi(Z)=
(1 )Z1
1 (1 1Ad
)Z1
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0 0.5 1 1.5 2 2.5 3 3.5120
100
80
60
40
20
0
20
Normalized Frequency in rad/s
Magn
itu
de
indB
Ideal and Predistorted Response
0.05 0.1 0.15 0.2 0.25 0.3
0.1
0.05
0
0.05
Fig.22.
Predistorteda
ndIdealResponse-Passband
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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 107
80
70
60
50
40
30
20
10
0
Frequency in Hertz(Hz)
Magn
itude
Response
indB
Effect of Finite Gain(1000) in DR scaled and unscaled Response
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
0.15
0.1
0.05
0
Ideal
Scaled
Unscaled
Fig.23.
Predistorteda
ndIdealResponse-Passband
C2
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VinC1
1
2 1
2
+A
Fig. 24. Finite Bandwidth Effect
XII. Opamp Design
Folded-cascode opamp was chosen for the opamp-design. In-order to maximize the output swingand to minimize the any extra compensation capacitors, folded cascode opamp was chosen [6]. The
figure 26 shows the magnitude response of the top-level simulation of the 5th order elliptic filter withbootstrap switches and folded-cascode opamp. The Ideal response and the macro-model response withfinite gain and bandwidth limitations are also shown for comparison. The opamp designed has thefollowing specifications.
Parameter ValueDC-Gain 57.8 dB
Unity Gain Bandwidth 500 MHzLoad Capacitance 1 pFSlew-Rate 180V/s
Common-mode 0.9 V
The above specifications were derived from the finite-DC gain and bandwidth requirements for thefilter specification. The open-loop gain and bandwidth characteristics of the amplifier is shown in thefigure. 27.
From the bandwidth requirement, the input pair transconductance is calculated.
gm,inCL
= 2 500 106
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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 107
80
70
60
50
40
30
20
10
0
10
Frequency in Hertz(Hz)
Magni
tude
Response
indB
Effect of Finite Gain(1000) and Bandwidth 50MHz 500MHz
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
0
0.5
1
1.5
2
Increasing Bandwidth
Fig.25.
FiniteBandwidthEffect
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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 107
90
80
70
60
50
40
30
20
10
0
Frequency in Hertz(Hz)
Magn
itu
de
indB
5th
Order Elliptic Filter with Folded Cascode Opamp
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
0.15
0.1
0.05
0
Ideal
Bootstrap Switch + FoldedCascode Opamp
Bootstrap Switch + MacroModel Opamp
50 dB Line
DCGain = 0.9954
Fig.26.Top-LevelSimulationofFilter
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100
101
102
103
104
105
106
107
108
109
1010
20
0
20
40
60
Frequency in Hertz
Open
Loop
Ga
inindB
Open Loop Amplifier Gain and Phase
100
101
102
103
104
105
106
107
108
109
1010200
150
100
50
0
Gain
Phase
46
Phase Margin
57.8 dB DC Gain
Fig
.27.
Open-LoopAmplifierGainandPhaseCharacteristics
Vdd
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Vdd
Vb1
Vb2
2.5 K
55 A
2.8 K
Vb3
Vb4
V+
V-
M0 M1
M3 M4
M5 M6
M7
Vb2
Vb4Vb4
VcmfbVcmfb
VopVon
Vop
Von Vcm
1/gm21/gm2
CcCc
M25
M8
M9
M10
M12M11
M13 M14
M15 M16 M17
M18M19 M19
M23 M24
M20
M21
Transistor Sizes in m
M3,M5,M4,M6 26(0.5/0.5) M7,M8,M25,M0,M1,M13-16 80(0.5/0.5)M9,M10 468(0.5/0.5) M11,M12 234(0.5/0.5)
Common-mode Feedback branch Current density is 1/5th of the differential branch
- - - -
the filter is maximized. The opamp was design using 0.18 TSMC model at 1.8 V supply. The totalbias current consumption is 1.1 mA.
The impulse-response and step response of the transistor level filter(Opamp + Bootstrap Switch) isd ith Id l filt i th fi 30 Th t i t i l ti ith 2 V i t t 500 kH i
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compared with Ideal filter in the figure 30. The transient simulation with 2 Vpp input at 500 kHz isshown in the figure 31. The clippin near 1 V is due to limitation of the swing at around 1.4 V and at0.5 V of the folded cascode amplifier.
References
[1] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. Wiley Series on Filters, 1986.[2] D. A. Johns and K. Martin, Analog Integrated Circuit Design. Wiley, 2005.[3] G. C. Temes, Finite amplifier gain and bandwidth effects in switched-capacitor filters, IEEE JOURNAL OF SOLID-STATE
CIRCUITS., vol. 15, pp. 358361, 1980.[4] K. Martin and A. S. Sedra, Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters,
IEEE Transactions on Circuits and Systems., vol. 28, pp. 822829, 1981.[5] G. C. T. K. Haug, F. Maloberti, Switched-capacitor integrators with low finite-gain sensitivity, Electronic Letters, vol. 21,
pp. 11561157, 1985.[6] R. Gregorian, Introduction to CMOS Op-Amps and Comparators. Wiley, 1999.
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2 4 6 8 10 12 14 16
x 107
0.04
0.02
0
0.02
0.04
0.06
0.08
0.1
Time in second(s)
Trans
istor
Level
Filter
Respo
nse
(V)
Impulse response of Transistor Level Filter
2 4 6 8 10 12 14 16
x 107
0.04
0.02
0
0.02
0.04
0.06
0.08
0.1
Time in second(s)
Idea
lFilter
Response
Impulse response of Ideal Filter
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1 2 3 4 5 6 7 8 9 10
x 107
0.2
0.4
0.6
0.8
1
Time in second(s)
StepRe
sponseofTransistorLeve
lFilter(V)
Step Response of Ideal Filter and Transistor Level Filter
1 2 3 4 5 6 7 8 9 10
x 107
0
0.2
0.4
0.6
0.8
1
Time in second(s)
StepRes
ponseofIdealFilter(V)
Fig.30.
ImpulseR
esponse
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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 105
1.5
1
0.5
0
0.5
1
1.5
Time in Second(s)
TransientResponse
Transient response of 2Vpp
Input sinusoid at 500 kHz with Transistor Level Opamp + Switch
InputFilter Output
Fig.31.
TransientResponse