nonlinear characterization and modeling through pulsed iv ...small-signal iv model non-linear...

Nonlinear Characterization and Modeling Through Pulsed IV/S-Parameters

http://www.maurymw.com/index.php

– Introduction

– Core device model extraction

– Model Enhancement

– Model Validation

OUTLINE


Types of Large-Signal Transistor Models

Compact

model

Behavioral

model

Physic

model

Physical insight

Operating rangeConvergence

Extrapolation

Accuracy

Easy modeling

processUsability for Circuit design


Commercial compact FET models

• Mostly used models for GaN HEMTs

FET modelsNumber of parameters

Electro-thermal effect

TrappingEffects

Original DeviceContext

Curtice3 [1] 59 No No GaAs FET

CFET [2] 53 Yes No HEMT

EEHEMT1 [3] 71 No No HEMT

Angelov [4] 80 Yes No HEMT/MESFET

AMCAD HEMT1 [5] 65 Yes Yes GaN HEMT

• AMCAD GaN HEMT1 is the only model here with a complete extraction flow

based on pulsed IV/RF measurements


Small-Signal IV ModelNon-linear

capacitancesThermal model

Trappingeffects

y = 0.0029x + 0.6375

y = 0.0049x + 0.6889

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200

T°C

Rs, R

d

Rs

Rd

y = -0.0008x + 1.1543

1.02

1.04

1.06

1.08

1.1

1.12

1.14

1.16

1.18

0 50 100 150 200

T°C

Idss

Rg

Lg

Cpg

Ls

Cpd

Ld

Rs

Rd

Ri

Cds

τ

Gm

Gd

Cgs

Cgd

Rgd

Dgs=f(Vgs)

Dgd=f(Vgd)

Ids=f(Vgs,Vds)

Cgs=f(Vgs)

Cgd=f(Vgd)

Rs=f(T)

Rd=f(T)

Dgs=f(Vgs,T)

Dgd=f(Vgd,T)

Ids=f(Vgs,Vds,T)

Ids=f(Vgs_trap,Vds,T)

Various effects are successively added

Compact FET model extraction flow


Parameter extraction methodology


– Introduction




OUTLINE



Pulsed IV / S parameter

Multibias set of linear models

Nonlinear model

1st step: bias-dependant S

parameters

Core device model

2nd step: large

signal fitting

Measurements

Modeling


Pulsed IV measurements

Several quiescent bias point

Short pulse : Quasi-isothermal conditions

Low duty cycle : Constant mean temperature

Quiescent bias point : Thermal conditions fixed


Modelling Process

Small-Signal

Rg

Lg

Cpg

Ls

Cpd

Ld

Rs

Rd

Ri

Cds

τ

Gm

Gd

Cgs

Cgd

Rgd

Bias Bias

Pulsed S parameter measurements




The first & most important point :

• Pulsed S parameter measurements must not

be noisy

• Small S2P measurement variation = strong

influence over the linear model extraction :

optimization algorithm

Dynamic range in pulsed mode > 90dB for Duty Cycle ~ 5%

IVCAD

Requirements :


Pulsed S-parameter Measurements

Pulsed S-parameter measurements must not be noisy at low duty cycle with narrow pulse width

Pulse detection methods

Wideband detection Narrowband detection

• No pulse desensitization

• Increased noise with narrow pulse width due

to wider IF bandwidth

• Limited pulse width by maximum available IF

bandwidth

• Narrower minimum pulse width than

wideband pulse

• Reduced dynamic range with low duty cycle

due to pulse desensitization by 20*log(duty

cycle)

IF filterIF filterReceiver samples Receiver samples


PNA/PNA-X Noise reduction techniques and performances

Peak-to-peak noise with wideband detection at 10% duty cycle

Averaging 20 times in calibration and measurements

10 us

(150 kHz)

Pulse

width

(IFBW)

5 us

(280 kHz)

1 us

(1.5 MHz)

500 ns

(3 MHz)

0.03 dB

0.04 dB

0.06 dB

0.09 dB

0.005 dB

0.006 dB

0.012 dB

0.013 dB

No averaging in calibration and measurements


Dynamic range with wideband detection at 10% duty cycle with 10 us, 5 us, 1 us,

500 ns pulse width

Averaging 20 times in calibration and measurements,

1% smoothing on

No averaging in calibration and measurements, 1%

smoothing on



10 us

Pulse

width

5 us

1 us

500 ns

0.009 dB

0.009 dB

0.012 dB

0.011 dB

0.005 dB

0.006 dB

0.012 dB

0.013 dB

Wideband detection with 20 times averaging in

calibration and measurements

Narrowband detection with no averaging in calibration

and measurements

Peak-to-peak noise at 10% duty cycle



Dynamic range with narrowband detection at 500 ns pulse width

No Averaging, 1% smoothing on, 500 Hz IF bandwidthHardware

gating

Crystal

filter

Software

gating

Spectral

nulling

>100 dB at 10%

>100 dB at 5%

90 dB at 1%

85 dB at 0.5%



E836x Legacy PNA N524xA PNA-X N522xA New PNA

Pulse generator External Internal/External Internal/External

Pulse modulator External Internal/External Internal/External

Wideband detection

Max BW/Min PW 35 kHz / 50 us 15 MHz / 100 ns 15 MHz / 100 ns

High level noise* 0.006 dBrms 0.002 dBrms 0.002 to 0.003 dBrms

Dynamic range** 114 to 123 dB 124 to 129 dB 127 dB

Narrowband detection

Min IF gate width 20 ns <20 ns <20 ns

Dynamic range*** 85 dB <105 dB <105 dB

* Specified as trace noise magnitude, at 20 GHz, at 1 kHz IF bandwidth

** Specified performance at 20 GHz, at 10 Hz IF bandwidth

*** Measured performance at 10 GHz at 10 Hz IF bandwidth, 1% duty cycle


Small-Signal IV Model

Rg

Lg

Cpg

Ls

Cpd

Ld

Rs

Rd

Ri

Cds

τ

Gm

Gd

Cgs

Cgd

Rgd

Dgs=f(Vgs)

Dgd=f(Vgd)

Ids=f(Vgs,Vds)

RF RF

DC DC



Pulsed IV parameter measurements• Pulsed IV measurements must be accurate

from low to high voltage/current values

• Accurate IV data =

Reliable current source

Transconductance

Leakage current

Ideality factor schottky diode

IVCAD


How to get accurate pulsed IV measurements ?

PIV system

Pulsed IV parameter measurements



15 bits + sign Drain250V

16 bits

16 bits25V

Gate

+15V

-15V

15 bits + sign

Pulse shape monitoring

20ns time resolution




Measurement Resolution

Voltage Absolute Accuracy

Voltage Range

0,6mV

65mV

15V

0V-15V

0mA

20mA

200mA

1µA

40µA

20mA

9µA

400µA

200mA




0V 25V 250V

Measurement Resolution

Voltage Absolute Accuracy

Voltage Range

0,53mV 4,9mV

50mV 500mV

0A

1A

10A

22µA

2mA

200µA

20mA



Pulsed IV & S parameter measurements


Synchronisation between Pulse IV and pulse S parameters




Synchronisation between Pulse IV and pulse S parameters



Pulsed IV / S parameter


Nonlinear model


parameters

Core device model

2nd step: large

signal fitting

Measurements

Modeling


• Extrinsic parameters

- pad capacitances Cpg, Cpd

- port metallisation inductances Lg, Ld, Ls

- port ohmic resistances Rg, Rd, Rs

• Intrinsic parameters

- channel capacitances Cgs, Cgd

- voltage-controlled current source with

transconductance gm and transit time delay

tau

- ohmic resistances Ri, Rgd

- output capacitance Cds and resistance Rds

Small signal FET modeling

Rs

RdRg

Grille Drain

SourceSource

Rgd

Ri

Cgs

Cgd

CdsGm Rds

Gm = Gm 0 e-jTransistor intrinsèque

Transistorintrinsèque

CpdCpg

Lg Ld

Ls

G

S

D

The small-signal model presents

two parts :

- an intrinsic circuit

- an extrinsic circuit related to the

parasitic elements

An algorithm developped at the

IRCOM lab allows to optimize the

extrinsic elements in order to get

intrinsic parameters that do not

depend on the frequency

Rs

RdRg

Grille Drain

SourceSource

Rgd

Ri

Cgs

Cgd

CdsGm Rds

Gm = Gm 0 e-jTransistor intrinsèque

Transistorintrinsèque

CpdCpg

Lg Ld

Ls

G

S

D

The small-signal model presents

two parts :

- an intrinsic circuit

- an extrinsic circuit related to the

parasitic elements

An algorithm developped at the

IRCOM lab allows to optimize the

extrinsic elements in order to get

intrinsic parameters that do not

depend on the frequency

intrinsic

transistor

intrinsic transistor

Gate Drain

Source


Small signal FET modeling

• Extraction of extrinsic and intrinsic

parameters:

There is only one set of extrinsic parameters

for which intrinsic parameters are independent

from the frequency

For a given set of extrinsic parameters, intrinsic

admittance matrix of the device is extracted

from measured [S] parameters

Multi-biasing extraction of the

linear model

Set min. and max. for each extrinsic parameter- user choice- initiated by cold FET meas.

Optimization algorithm: annealing, fast simulated diffusion(intrinsic parameters calculus)

Fit ?

No

Yes


– Introduction




OUTLINE



Pulsed IV / S parameter measurement results

Specific measurements


Nonlinear modelEnhanced

Nonlinear model


parameters

- diodes

- g-d breakdown

- thermal effects

- charge carrier trapping

3rd step:

setting of

additional

parameters

Core device model

2nd step: large

signal fitting

Model Enhancement


Small-Signal IV ModelNon-linear

capacitancesThermal model

Trappingeffects

y = 0.0029x + 0.6375

y = 0.0049x + 0.6889

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200

T°C

Rs, R

d

Rs

Rd

y = -0.0008x + 1.1543

1.02

1.04

1.06

1.08

1.1

1.12

1.14

1.16

1.18

0 50 100 150 200

T°C

Idss

Rg

Lg

Cpg

Ls

Cpd

Ld

Rs

Rd

Ri

Cds

τ

Gm

Gd

Cgs

Cgd

Rgd

Dgs=f(Vgs)

Dgd=f(Vgd)

Ids=f(Vgs,Vds)

Cgs=f(Vgs)

Cgd=f(Vgd)

Rs=f(T)

Rd=f(T)

Dgs=f(Vgs,T)

Dgd=f(Vgd,T)

Ids=f(Vgs,Vds,T)

Ids=f(Vgs_trap,Vds,T)

Various effects are successively added



• Gate charge is partitioned into gate source and gate-drain charge. Each charge expression is

a function of both VDS and VGS.

• For power amplifier applications, 2D models do not bring a breakthrough in the precision, but

they are much more complex

• 1 dimension capacitances extracted along optimal load-line are preferred due to simplicity.

1D capacitances with equations based on hyperbolic tangents are naturally charge

conservatives

• Output Capacitance Cds is linear – no voltage dependence (weak anyway)

Cgs=f(Vgs)

+ Modeling simplicity. Very good convergence

- Validity of the 1D ?

Cgd=f(Vgd)

Non linear capacitances

33



• Capacitances modeling: 1D vs 2D

Better fit of the 2D

model in wider domain

But the 1D model

has a good behavior

34


Cgd capacitance extracted

along optimal load-line for

power amplification

Cgd • Feedback capacitance Cgd is a strong function of drain voltage.



Cgs • Input capacitance Cgs is a strong function of gate voltage.

The gate-voltage non-linearity also effects model’s harmonic generation

Cgs capacitance extracted

along optimal load-line for

power amplification



Output current source

meas.

model

10 20 30 40 50 600 70

0.2

0.4

0.0

0.6

Vds (V)

Id (

A)

-9 -8 -7 -6 -5 -4 -3 -2 -1 0 1-10 2

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.00

0.50

Vgs (V)

Gm

(S

)

• AMCAD drain current model formulation allows to predict

very accurately the I-V curves, the partial derivatives gm

and gd, the knee voltage and the transconductance

decrease at high current.


Output current sourceIdss ↔ amplitude

Vp0 ↔ pinch-off

Vdsp, A ↔ slope

P ↔ gd

M, P ↔ fitting parameters

AlphaGm, Vgm, BetaGm, Vdm ↔ gm (derivative)


Diodes

• Gate-drain and gate-source diode

equations include forward conduction

of gate current

n)formulatio classical (a. . VdAlpha

eIsID


Breakdown generator

• Gate-drain Breakdown generator

50 100 150 2000 250

0

200

400

600

-200

800

Vds (V)

Ids (

mA

)

50 100 150 2000 250

-200

-100

0

100

-300

200

Vds (V)

Igs (

mA

)

The breakdown phenomena leads to a current from the drain to the gate when the

device is pinched-off and for high values of Vds voltage. In this case, the whole

negative current characterized on the gate is seen in positive on the drain

A polynomial expression with order 4 is necessary to model the cross of breakdown

curves, with varies depending on the process


Thermal effects

• Static and Dynamic self-heating effects

20 40 60 800 100

-0.0

0.2

0.4

0.6

0.8

-0.2

1.0

Vds (V)

Ids (

A)

Static

Dynamic

1

2

25°C

5 10 15 20 25 30 35 400 45

-0.0

0.2

0.4

0.6

0.8

-0.2

1.0

Vds (V)

Ids (

A)

-40°C

5 10 15 20 25 30 35 400 45

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

-0.1

0.9

Vds (V)

Ids (

A)

150°C

5 10 15 20 25 30 35 400 45

0.0

0.1

0.2

0.3

0.4

-0.1

0.5

Vds (V)

Ids (

A)

• Temperature dependence with ambient or chuck temperature


Thermal effects


Thermal impedance extraction – by simulation

Thermal effects


Thermal impedance extraction – by measurements

Thermal effects


AMCAD original current source

Diodes

Non linear Capacitances

Breakdown source

Thermal circuit

Dissipated Power

Extrinsics

Gate access

Drain access

Source access

• Drain current is only temperature dependent model element

Takes into account ambient temperature and self-heating effects

Thermal analog circuit to model self-heating and elevated heat sink temperatures

RC cells

Thermal effects


Trapping effects

AMCAD original current source

Diodes

Non linear Capacitances

Breakdown source

Thermal circuit

Dissipated Power

Extrinsics

Gate access

Drain access

Source access

• Charging and discharging of traps has influence on Ids and leads to current collapse. This is

described in the model by trapping effects modifying the gate command and separated into

gate and drain lag sub-circuits

Igs(T°) Vgs

_intGate- & Drain-lag

Vgs Vds

Cgs

Ri

Rs(T°)

Ls

Cds

Ids (Vgs_int(t-τ), Vds(t), T°)

Cpd

LdRd(T°)RgdCgd

Igd(T°)

RgLg

Cpg

Ibk

Transistor intrinsèque

Igs(T°) Vgs

_intGate- & Drain-lag

Vgs Vds

Cgs

Ri

Rs(T°)

Ls

Cds

Ids (Vgs_int(t-τ), Vds(t), T°)

Cpd

LdRd(T°)RgdCgd

Igd(T°)

RgLg

Cpg

Ibk

Transistor intrinsèque


Trapping effects


Trapping effects

• Charge of the capacitance = Ionized traps

Charge through Rcapture, Emission through Rémission

Diode = dissymmetry of the

capture and emission process

Tuning of the magnitude of the

trapping effects

Fundamental assumption : dissymetry of the capture and emission process

signal reshaping

circuit Port

Vout

Port

Vin

Diode

diode

R

Remission

R

Rcapture

C

C8


Trapping effects

• Bias dependant gate lag -> current reduction over the entire characteristic

Bias dependent drain lag -> current reduction and shifts the knee-voltage to a higher Vds

Model covers knee walkout to avoid

errors in calculation of output power.

5 10 15 20 25 30 35 40 45 50 550 60

0.0

0.1

0.2

0.3

0.4

0.5

0.6

-0.1

0.7

Vds (V)

Ids (

A)

(H

)

H

gate-lag : Id ↘ => Pout ↘

Id ↘Vknee↗

=> Pout ↘drain-lag :


Trapping effects

• Decreasing form of the mean output current only reproduced with traps modeled

-5 0 5 10 15 20 25-10 30

0.20

0.25

0.30

0.15

0.35

Pin( dBm)

Ids (

A)

(H

)Id

s (

A)

(H

) (

H)

H

0.05 0.10 0.15 0.20 0.25 0.300.00 0.35

1

2

3

0

4

Pin (W)

Pout

W

(H)

Pout

W

(H)

(H

)

H

-5 0 5 10 15 20 25-10 30

0.20

0.25

0.30

0.15

0.35

Pin( dBm)

Ids (

A)

(H

)Id

s (

A)

(H

) (

H)

H

0.05 0.10 0.15 0.20 0.25 0.300.00 0.35

1

2

3

0

4

Pin (W)

Pout

W

(H)

Pout

W

(H)

(H

)

H

Ids

(A)

Po

ut (

W)

Ids ↘

Pout ↘

meas

model without traps model

model with traps model

meas

model without traps model

model with traps model


– Introduction




OUTLINE



Pulsed IV / S parameter measurement results

Specific measurements

Power measurements


Nonlinear modelEnhanced

Nonlinear modelFinal Nonlinear

model


parameters

- diodes

- g-d breakdown

- thermal effects

- charge carrier trapping

-load-pull measurements

CW, pulsed

2-tones

time domain

3rd step:

setting of

additional

parameters

4th step:

implementation in

commercial simulator

5th step:

validation and

refinement

Core device model

2nd step: large

signal fitting

Model Enhancement Model Validation


meas.

model

-5 0 5 10 15 20 25-10 30

10

15

20

25

30

35

5

40

10

20

30

0

40

Pin dBm

Pout

(dB

m)

and G

ain

(dB

)

PA

E (%

)

PoutPAE

gain

0 5 10 15 20 25-5 30

0

20

40

-20

60

0

20

40

-20

60

Pin dBm

Po

ut (d

Bm

) a

nd

Ga

in (

dB

)

PA

E (%

)

meas.

model

Pout PAE

gain

Model validation of a 8x75 µm GaN HEMT with

load-pull measurements performed at 6 GHz

for optimum PAE load impedance in class-AB

Model validation of a 8x400 µm GaN HEMT with

load-pull measurements performed at 3 GHz for

the optimum Pout load impedance in class-B

• Large-signal

Model validation


Model validationVNA Based load pull system is preferred for model validation

Specific Architecture

PA

VNATuner f0, 2f0, 3f0

50

DUTT T

Gate

Drain

DC or pulse DC supplies

+ meas Units

CW or pulse RF signal

f0 or f1+f2

Low loss directional

couplers

Tuner f0


Model validation

VNA Based load pull system is preferred for model validation


Power meter based system are wideband measurement system

f0

2.f0 3.f0

VNA based system can be narrowband measurement system

More information

for model

validation or

efficient design

f0

f0

f0

2.f0 3.f0

2.f0 3.f0

2.f0 3.f0


VNA based Load Pull systems

Some Measurement definition

P_in: Power delivered to the DUT by the source

P_out: Power delivered to the load impedance

Power gain is the ratio of the power delivered to the load (Pout) to the

power delivered to the transistor by the source (Pin).


Model validationVNA Based load pull system is preferred for model validation

Specific Architecture

PA

VNATuner f0, 2f0, 3f0

50

DUTT T

Gate

Drain

DC or pulse DC supplies

+ meas Units

CW or pulse RF signal

f0 or f1+f2

Low loss directional

couplers

Tuner f0

Phase

reference


Time domain load pull

measurements

Deembedding in the intrinsic

reference plane

Parasitic extrinsic elements must

be accurately extracted by previous

S parameter measurements

Large signal impact - class AB, 25V, 10 GHz – Comparison with measurements

With non optimal loads :


Testing Model Validity with Pulsed IV Simulations(Using Agilent ADS)

• Is your FET model suitable for high-frequency design?

– Is dynamic behavior included?

– Is it well-fitted for high-frequency, large signals?

– What is the model’s valid range of use?

“Accounting for Dynamic Behavior in FET Device Models,” Microwave Journal, July, 2011: http://cp.literature.agilent.com/litweb/pdf/5990-8706EN.pdf

Download the Pulsed IV Curve Simulation DesignGuide for FETs: http://edocs.soco.agilent.com/display/eesofkcads/Pulsed+IV+Curve+Simulation+DesignGuide+for+FETs


http://cp.literature.agilent.com/litweb/pdf/5990-8706EN.pdf



http://edocs.soco.agilent.com/display/eesofkcads/Pulsed+IV+Curve+Simulation+DesignGuide+for+FETs

http://edocs.soco.agilent.com/display/eesofkcads/Pulsed+IV+Curve+Simulation+DesignGuide+for+FETs

Maury – Agilent – AMCAD Solution


Microwave Journal – March 2012

Technical Feature

“Compact Transistor Models: The Roadmap to First-Pass Amplifier Design Success”


Hiro Maehara

Applications Expert – Agilent Technologies

[email protected]

Tony Gasseling

General Manager– AMCAD Engineering

[email protected]

Steve Dudkiewicz

Director, Business Development – Maury Microwave

[email protected]


nonlinear characterization and modeling through pulsed iv ...small-signal iv model non-linear...

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