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Title Novel Quantum Nanodevice-based Logic Circuits Utilizing Semiconductor Nanowire Networks and Hexagonal BDDArchitecture

Author(s) Kasai, Seiya

Citation Proceedings of 15th International Workshop on Post-Binary ULSI Systems, Singapore, May 17, 2006, pp.43-50,

Issue Date 2006-05-17

Doc URL http://hdl.handle.net/2115/10125

Type conference presentation

Additional Information There are other files related to this item in HUSCAP. Check the above URL.

File Information Presentation.pdf

Hokkaido University Collection of Scholarly and Academic Papers : HUSCAP

Novel Quantum Nanodevice-based Logic Circuits Utilizing Semiconductor Nanowire Networks

and Hexagonal BDD Architecture

Seiya Kasai

Graduate School of Information Science and Technology and Research Center for Integrated Quantum Electronics,

Hokkaido UniversityJapan

15th International Workshop on Post-Binary ULSI Systems, May17, 2006, Nanyan Tech. Univ., Singapore

Collaborators and Supports

Special thanks:

Prof. H. Hasegawa, Prof. Y. Amemiya, Prof. T. Fukui, Prof. T. Hashizume, Prof. T. Sato and Dr. M. Yumoto.

Support:

21st Century COE program, Hokkaido Univ., "Meme-media Technology Approach to the R&D of Next-generation ITs" from MEXT, Japan

Grant-in-Aids for Young Scientists (A) and Exploratory Research from MEXT, Japan

FY2004 Industrial Technology Research Grant Program from NEDO, Japan

Outline

1. Introduction

2. Concept and Implementation of Hexagonal BDD Quantum Circuits

3. Devices, Elemental Circuits and Subsystems

4. Nanoprocessor

5. Summary

Introduction

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Documents

IC tag

“very small devices”

“high performance machines connected

to everything”

Ubiquitous Society ~ Networking Everything

Ubiquitous Hardware for End Users/Objects

Small device : Ultra-Small Knowledge Vehicle

< mm

Antenna Power source

Transceiver Sensor

CPU Memory

• Extremely “Small Size” and “Low Power”• More intelligent than RFID

21st Century COE program, Hokkaido Univ., "Meme-media Technology Approach to the R&D of Next-generation ITs" from MEXT, Japan

How Low Power?

Power consumption• Communication : 10 nJ/bit by RF• Sensor : 1 nJ/sample• CPU : 1 nJ/instruction

Power source ~ mm2 chip• Solar cell : 100 nW Room

• RF : 100 µW d = 1 cm

Only limited tasks

Possible tasks by RF power for 10 ms (= 1 µJ)• 100-bit data transmission or• 300 data sampling for 3 sensors or • 300 data averaging

For Intelligent tasks, “Lower Power” is necessary

2 mm0

40

60

80

100

120

140

2 3 4 5 6

outp

ut c

urre

nt (µ

A)

frequency (GHz)

20

Power: 25 dBm1 cm

RF-DC power converter(rectina)

http://robotics.eecs.berkeley.edu/~pister/SmartDust/in2010

Out of Control, A-Few Electrons in CMOS

CMOS Trends from ITRS10-14

10-15

10-16

10-17

10-18Po

we

r-d

ela

y p

rod

uct

(J)

104

103

102

10

1

Ele

ctro

ns/

bit

1990 2000 2010 2020 2030Year

20

15

10

Sta

tist

ical

flu

ctu

atio

n (

%)

5

0a-few electron domain

• Reduction of power = Reducing electrons/bit• Electrons < 100 causes serious bit error in CMOS

Precise control of a-few electrons is possible by quantum nanodevices

Quantum Nanodevices

To keep CMOS compatible, we should solve problems in straight forward, but very difficult

“cover-up” by alternative logic architecture = hexagonal BDD

Advantage Low powerSmall

Problem

Low temperature operationPoor current drivability, low gainUniformityIntegration

Concept of Hexagonal BDD Logic Quantum Circuits

Hexagonal Binary-Decision Diagram (BDD)

Logic gate architecture

x1x2x3

f

• Logic-function representation: directed graph with hexagonal layout

root

x1

x2

x3

10

x10 1

0 1

0 1

x2

ƒ

x3

information messenger= single/a few electrons

logic graph with hexagonal layout terminal

logic input

quantumnode device

• Information messenger: single or a few electrons• Device: quantum node device switching paths for messengers

Kasai and Hasegawa, IEEE EDL, 23, 2002

BDD Node Device

Xi0 1

entry branch

exit branches

logic inputxi

information messenger

BDD Node Device

Xi0 1

entry branch

xi = “0”

exit branches

BDD Node Device

Xi0 1

entry branch

xi = “1”

exit branches

BDD Circuit Operation

x1

x2

AND

1 0

1 0

1 0

x1

x2

input signal (x1, x2)

x1 x2 AND

0 0 00 1 01 0 01 1 1

ex. AND = X1 • X2

Main Features

1. Ultra-low power operation

path switching function and passive transmission of messengerdon’t require “transfer gain” and “current drivability”

single- or a-few-electron messengers controlled in quantum wayby ultra-low voltage results in low current and low power

2. High-density and large-scale integration

hexagonal network realizes high-density integration of node devices having 3-fold symmetric configuration

xi

xi

xi

xi

xi xi

Hardware Implementation

Compound Semiconductor Hexagonal Nanowire Network + Nano-scale Schottky Wrap Gate (WPG)

Schottky wrap gate (WPG)

AlGaAs

electrons GaAs

WPG structurehexagonal etched nanowire network WPG quantum node devices

• Simple planar structure: design flexibility, easy to integrate

• Tight gate control

• Operation as either “quantum nanodevices” or “normal FETs”

WPG structure:

Quantum wire (QWR) type

WPGnanowire

0 1

Vxi Vxi

quantum wire (QWR)

Single electron (SE) type

quantum dot (QD)

WPGVxi

0

Vxi

1

Compound Semiconductor Meets Hexagonal BDD

• High speed and low power

• Large quantized energy and long mean free path

• Mature nanostructure formation technology

source: Intel, IDF 2006

Main Features

1. Ultra-low power operation

2. Large-scale and high-density integration

3. Correct operation even at RT

WPG can control not only a-few-electrons but many electrons by trade-off with power

4. Vth fluctuation cover-up

cover-up by adjustment of input logic swing

Low T

High T

kTkT

signal

WPG-based Quantum Node Devices

WPG device

I DS

(µA)

0

2

4

6

8

10

12

14

0 200 400 600VDS (mV)

295 K VG = 800 mV700 mV

600 mV

500 mV

400 mV

300 mV

200 mV

W = 560 nmLG = 500 nm

gm = 60 mS/mm @ RT 230 mS/mm @ 80K

VG (mV)-280

0

1

2

3

-360 -3201.6K2.5K3.5K4.2K6K11K19K24K

0

2

4

6

8

10

VG (mV)-200 -100 0 100 200

Cond

ucta

nce

(2e2

/h)

VDS = 0.2 mV

78K65K55K45K35K25K17K9K3.5K

QWR device Single electron device

500 nm

WPG

GaAsnanowire 1000 nm

WPG GaAsnanowire

• Fabricated devices can operate as QWR and SE devices successfully control single or a-few-electrons

Path Switching Operation

QWR type node device1000 nm

WPG

xixi

GaAs nanowire

0-branch 1-branch

time (sec)50

0

0.5

1.0

0 10 20 30 40cond

ucta

nce

(2e2

/h)

0-branch1-branchoutput0

1VDD=0.2mVinput xi

1.7 K

0

5

10

15

0 0.1 0.2 0.4 0.6

outp

ut c

urre

nt (µ

A)

time (ms)

297 KVDD=300 mV

output

input xi

0-branch1-branch

Path switching using quantized conductance

Path switching of many electronsin classical way

Logic Circuits

1 0

01

1

AND

x1

x2

terminal-1

1000 nm root

X1

X2 X2

X1

WPG

AND logic QWR-type Logic operation

quantum regime (1.6 K) classical regime (300 K)

500 nA

0 5 10 15time (sec)

output

VDD = 250 mVx1

x2

20time (sec)

0 5 10 15

VDD = 0.2 mV

5 nA

output

x1

x2

OR logic1000 nm

x1x1

x2

terminal-1

root

WPG

GaAs nanowire

x1

x2

10

1

1

OR

quantum regime (1.6 K) classical regime (120 K)

0 2 4 6 8

x1

x2

output

time (sec)

0.1 nA

x1

x2

output

0 50 100 150 200time (sec)

0.2 nA

• WPG BDD circuits can operate from LT to RT, changing transport mode

SE-type

Subthreshold Characteristics in WPG Devices

GaAs nanowire

AlGaAs

WPG

electron

• Subthreshold slope is ideal in both quantum and classical domains

∂ ln( I )∂VG max

1= ln(10)kT

α S =

• Power-Temp. trade-off : PDP ~ C {kT/e ln(10)}2 ~ T2

Su

bth

resh

old

slo

pe

, S

(m

V/d

ec)

ideal ( = kT ln10 )

W = 850 nm, LG = 430 nm

VDS = 400 mVVDS = 0.2 mV

planar HEMTWPG

experiment

simulation

00 100 200 300

Temp. (K)

60

40

20

100

High Speed Performance of WPG Devices

nanowire x 90

...WPG source

drainLG

10 µm

gate

source source

drain

WPGsource

drain

nanowire500 nm

frequency (GHz)

0

5

10

15

20

25

0.01 0.1 1 10ga

in (d

B)

MAG/MSG

|h21|2

ƒT ƒmax

VDS = 3 VVG = -1 VRT

LG = 110 nmW = 200 nm

Gate Length, LG ƒT ƒmax

630 nm 1 GHz 5 GHz

110 nm 2.5 GHz 9 GHz

• Confirmation of GHz switching capability

bipolar

PDP Scaling

100

10-4

10-8

10-12

10-16

10-20

1930 1950 1970 1990 2010 2020Year

Po

we

r-D

ela

y P

rod

uct

(J)

vacuum tube

nMOS

CMOS

WPG QWRWPG SET

1.6K RT(predict.)

CMOS ITRS projection

• WPG quantum nanodevice can keep PDP scaling

WPG quantumnanodevices

classical limit

Design of Hexagonal BDD-based Subsystems

• Any combinational circuits can be designedRepresentation by principal disjunctive canonical form + Omitting terminal-0

Adder Substractor Comparator

1 0 1 0

1 010 01

0 011

01 0 1

a1

b1

1 0

1 0

1 0

1 01 0

0 1a0

b0

1 0 1 0

1 010 01

0 011

01 0 1

a2

b2

c s2

s0

s1

1

a0 a0

b0 b0b0

a1 a1 a1

b1 b1 b1 b1 b1 b1

b2 b2 b2 b2 b2 b2

a2 a2 a2

1 0 1 0

0 101 10

0 011

10 1 0

1 0 0

110

01

0

1 0 1 0

01 10

0 011

10 1 0 0 1

s2

s0

s1

b2

a2

a1

b1

a0

b0

b1

b0 b0 b0

a0 a0

b1 b1 b1 b1 b1

a1 a1 a1

b2 b2 b2 b2 b2 b2

a2 a2 a2

1

1 0 1 0

0 1

1 0b2

1 0

0 1a2

1 0 1 0

0 1

1 0 1 0

0 1

1 0b1

1 0

0 1a1

1 0 1 0

0 1

1 0

0 1

1 0 1 0

0 1

1 0

0 1

A>B A<BA=B

b0

a0

b0 b0 b0

a0 a0

a1a1

b1 b1 b1b1b1

a2a2

b2 b2 b2b2b2

1

basicunit

A = an an-1 ... a0B = bn bn-1 ... b0

• Smaller device count than that in CMOS logic Ex. full adder unit Hexagonal BDD : 11 devices CMOS logic gate : 24 Trs

-an an-1 ... a0bn bn-1 ... b0sn sn-1 ... s0

an an-1 ... a0 bn bn-1 ... b0cn sn sn-1 ... s0

+

Fabrication and Characterization of Subsystems

QWR-type 2-bit adder

5 µm terminal 1

a1

b1

a0

b0

a1

b1

hexagonalnanowirenetwork

WPG

QWRnodedevice

C S1 S0

b0

a0

BDD 2-bit adder input-output waveforms

experiment (classical)

time (µs)0 400 800

8 kHz

T = 297K

VDD=250 mV∆VG = 400 mV, VGoffse t = 0 mV

S0

S1

C

a1a0

b1b0

G/2

G/4

G/2

0

G/4

G/3

0

time

0

theory

rootnode devicea11 0

b11 0 b11 0

a01 0

b01 0

b11 0

a11 0 a1 10

b10 1 b10 1

a0 10 a0 01

b01 0 b01 0

c1 s0s1

1 terminal

• Fabricated 2-bit adder operated correctly at RT• Fab. process for 45 M devices/cm2 using etched nanowire is available

Large-Scale Integration

s7c

terminal-1

s0

s1

s2

s3

s4

s5

s6

a0b0

a1b1

a2b2

a3b3

a4b4

a5b5

a6b6

a7b7

a0b0

a1b1

a2b2

a3b3

a4b4

a5b5

a6b6

a7b7hexagonalnanowirenetwork

WPG

10 µm

QWR-type 8-bit adder

node density: 25 M nodes/cm2

circuit area: 74 µm x 19 µm device counts: 84

1 0 1 0

1 010 01

0 011

01 0 1

a1

b1

1 0

1 0

1 0

1 01 0

0 1a0

b0

1 0 1 0

1 010 01

0 011

01 0 1

a2

b2

c s2

s0

s1

1

a0 a0

b0 b0b0

a1 a1 a1

b1 b1 b1 b1 b1 b1

b2 b2 b2 b2 b2 b2

a2 a2 a2

x 6

• Large number of devices can be integrated without nanowire crossover 84 QWR-based node devices could be integrated

Nanoprocessor

Nanoprocessor

core of ultra-small and ultra-low power digital systemsfor next-generation ubiquitous IT

• Feature: “1/1000 x size and power consumption of MPU”

But low power and small size are not compatible in CMOS

hexagonal BDD

• Target:

NPU Implementation

System can be implemented fully on a hexagonal nanowire network ?

BDD

sequential

Nanoprocessor system

von Neumann architecture

• Execution core : Hexagonal BDD

Hexagonal BDDHexagonal nanowire network

x1

x2

x3

x2

x3

f

10

x10 1

0 1

0 1

clock

data bus

ROM/RAM addressdecoder

memory address counter

instructiondecoder IR

PCcontroller

ACC B register

ALU

buffer

sensing dataoutput

I DS

(µA)

0

2

4

6

8

10

12

14

0 200 400 600VDS (mV)

295 K VG = 800 mV700 mV

600 mV

500 mV

400 mV

300 mV200 mV

W = 560 nmLG = 500 nm

WPG nanowire FET

GaAs

AlGaAs

electrons

Schottky gate

• Register, counter (sequential) : WPG nanowire FET

Hexagonal BDD-based ALU

8-instruction 2-bit ALU

selector

subsystems

1 0

1 0

1 0

0101 0 1

1 01 0

1 0

10 0 1 01 0 1

1 0

0

1 0 1

101

10

1

0 1

1 0

1 0 1 0

1

0 1

0 1 0

1 0

0 1

0 1

10

1

0

0

0 11

01

1 1 0

1 0 0 1

0

1 1 0

1

1

1

1 0

0 1

00 1

1

0 1

0

1

1

ALU1ALU2

s2

s0

s1

s0s0 s0

s1s1

s2

s0 s0 s0 s0

s1

a1 a1

b1b1

a1

b1

a1

b1b1

a1

b1

a1

b1b1

a1

b1b1

a1

b1

a1

a0

b0b0b0

a0a0

b0 b0

a0 a0

b0

a0 a0

b0

a0

b0

a0

b0

a0

b0

a0

b0

a0

b0

a1

input: A = (a1,a0), B = (b1,b0)selector signal: S = (s2,s1,s0)

8 instructions:S = 111: A+B 100: AND, 110: NOT 101: OR 010: bit left shift 011: bit right shift 000: comparator 001: A-B

Input-output waveforms (simulation)

inpu

t dat

a

0 4 8 12 16 20 24 28 32

A0

A1

s1s0

a1b1a0b0

20 mV

outp

ut

adder NOR B compa-rator

time (µs)

inst

ruct

ion

26.2 µm

13.9 µm

root: ALU2 ALU1

terminal-1

4.5x107 nodes/cm2

WPG nanowire network

• ALU can be designed using small number of devices

• Fabrication of 2-bit ALU on etched nanowire network

BDD 2-bit ALU (8-inst.) device count: 56 CMOS 2-bit ALU (7-inst.) Tr count: 144

Implementation of Sequential Circuits

WPG FET-based RS Flip Flop

Q

GND

VDDQ

S

R

S R Qn+1

1 1 Qn 1 0 0 0 1 1 0 0 –

T = 297 K, VDD = 250 mV

S

R

Q

1 1

0 1

reset

0 1

1 1

set

50 mVQn Qn+1 Qn Qn+1

holdhold

time (s)150 5 10

• Experimental confirmation of correct operation of RS-FF at RT

word selector

word

GND

selector

bit

memory bus

VDD

bit

60 x 44 hexagons

128-bit SRAM layout

• Successful design of SRAM unit

Register and Counter

D-FF design

VDD

Trigger

Q

Q

GND

Data

D-FF input-output waveform(simulation)

3-bit counter operation (simulation)

DataGND

Trigger

Q

Q

VDD

GND

T-FF design

0 0.5 1 1.5 2time (ms)

trigger

input data

Q

Q

200 mV

50 mV

297K

VDD = 400 mV

time (ms)0 0.5 1 1.5 2

C2

C1

C0

VDD = 400 mV

100 mV

100 mV

trigger 100 mV

count up 50 mV

• Correct operation of D-FF, T-FF and counter with small input voltage swing

Hexagonal BDD-based 2 bit Nanoprocessor

program counter

inst. decoder/controller

memory address counter

ROM

address decoder

accumulator (ACC)

B-register

Instruction register (IR)

controllerdata bus

buffer

ALU

4 ALU instructions:S =11: A+B 10: NOR 01: B 00: COMPARATORGND T

D1D0

Q

T

Q

VDD

a0

a0

a1

VDD

Vin

Vout

VDD

Vin

Vout

D0D1D2

c00 1

memory select

c10 1

c30 1

m1m0

c30 1

m5m4

c30 1

m7m6

c30 1

m3m2

c20 1

c20 1

c30 1

m9m8

c30 1

m13m12

c30 1

m15m14

c30 1

m11m10

c20 1

c20 1

c10 1

VDD

Q

VDD

Q

D

GND

TQ

D

GND

Q Q

D

T

Q Q

D

T

Q

Trigger

c0c1

c2

c3

s11 0

ALU1

0s01 s00 1

a11 0

1 b1 0

a10 1

0b1 b11

a11 0

0

a10 1

b10b1 1 0

b01 0

a01 0

1

a00 1

0b01

a00 1

0b0

b11

0s01 s01 0

s11 0

ALU0

1

a00 1

b01 0 10 b0

0 1a0

a10 1

0b10b1 10 1

b00 1

a00

D1 D0

a1

T

GND

VDD

b1

b0

b0

b1Q

T

GND T

D1D0

Q

T

Q

a0

a0

a1

s1s0

i010

i201

i101

i201

i001

i101

i210

i20

1

1

p010

Adr upBus-M

p101

IR tri

p101

Bus-Bf (reset)

i010

10p0

i101

i010

i101

i210

i210

p110

i001

Bf tri

p001

10i1

p010

Adr up

i010

p010

i101

A tri

i201

i201

i010

B tri

i110

i010

10p0

p110

VDDi0

i0

i2

Q

T

GND

i1

i1

Q

T

Q

T

i2

Q

VDD

1PC0

D

T

Q Q

D

T

QPC1

b1 1

VDD

Vin

VoutVDD

Vout

clock

Vin

clock 2

amp

29 x 50 hexagon

• Successful design of 2-bit NPU on 29 x 50-node network

2 bit Nanoprocessor System Operation

• Correct operation of the system was confirmed by simulation

Nanoprocessor Performance

Power consumption = activity factor x device count x PDP x clock

Device counts in system

program counter

inst.decoder

instructionregister(IR)

ALU

ROM/RAM

registerACC

address counter

controller

address decoder

D-FF x 2 bit = 24 (36) T-FF x 2 bit = 52 (84)

T-FF x 3bit = 108 (126) x 4bit = 15 (CMOS:188 trs)

x 3bit = 8 (72)

5 inst x 3bit = 14 (40) 4 inst x 2 bit ~ 32 (72)

D-FF x 2 bit = 24 (36)

(CMOS: 740 Trs) Total 381 devices

(740 Trs (CMOS)) total 381 devices

unit activity factor

BDD address decoder 0.20 ALU 0.11 controller 0.14 inst. decoder 0.13 Sequential ACC 0.09 IR 0.09 register 0.09 add. counter 0.15 prog. counter 0.31

average 0.2

Activity factor

• Power consumptions at 10MHz operation

SE-type BDD: PDP = 10-22 J (sequential:10-20 J) 0.01 nW65 nm CMOS: PDP = 10-16 J 15 nW x 0.001

Chip Size

area = const. x Trs x hp2 = 170 x 740 Trs x hp2

area = 29 x 50 hexagons

node density ~ 1/(4 hp)2

Hexagonal BDD-based 2-bit NPUNode density System area

45 M/cm2 3,200 µm2 fab. process available

1 G/cm2 145 µm2 nanowire network

1.5 G/cm2 85 µm2 nanowire network hp 65

13 G/cm2 11 µm2 hp 22

Tech. node System area

130 nm 2,100 µm2

65 nm 530 µm2 on the market

45 nm 260 µm2

22 nm 62 µm2 end of CMOS

CMOS-based 2-bit MPU

• Hexagonal BDD NPU chip size ~ 0.2 x CMOS MPU

Nanoprocessor Specification

MPU

8 bit

4 bit

2 bit

NPU

10 µm @ hp658 bit

4 bit

2 bit

• Size

• Power0 0.5 1.0 1.5 2.0 2.5 3.0

2 bit

4 bit

8 bit

hp 22CMOS hp 65

QWR (65nm)SET CMOS hp 65

CMOS hp 22QWRSET

Power Consumption (µW)

1

entry

VG0 VG1

VGentry

QD0

Future Options

• High-density integration

high-density nanowire network formation utilizing various materials and processes

• Low power consumptionlow-density electron system and correlations in nanostructures

- reduction of electrons/bit : single electron control in 1D wire- reduction of ∆VG: splitting a conductance peak in SE device

300nm

<110><510>

109 nodes/cm 2

nanometer-size gate for localization of quasi particles

1D Wigner crystal in nanowire peak splitting

0

1

2

3

4

5

6

7

-1800 -1600 -1400Ex

it br

anch

cur

rent

s (n

A)VG0 (mV)

T = 1.5 K

VDD = 1 mVVGentry = -2.4 VVG1 = +0.4 V

1-branch

0-branch

2 K4 K8 K

10 K15 K20 K30 K40 K0

0.5

1

1.5

2

-300 -200 -100 0

W = 540 nm, LG = 400 nmVDS = 0.1 mV

Cond

ucta

nce

(2e2

/h)

VG (mV)

0.7G0 anomaly

InP-based network

Summary

• Novel quantum nanodevice-based logic circuits was presented. “Hexagonal BDD logic quantum circuit” = III-V semiconductor nanowire networks + hexagonal BDD logic architecture

• Hexagonal BDD quantum circuits have possibility to realize ultra-low power and ultra-small digital systems beyond the scaling limits of Si CMOS technology.

• Basic technologies of hexagonal BDD quantum circuit has been established successfully.

• Based on the hexagonal BDD, nanoprocessor (NPU) has been intensively investigated for an ultra-small knowledge vehicle in advanced ubiquitous society.