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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011 1339

Novel Vector Control Method for Three-StageHybrid Cascaded Multilevel Inverter

Saad Mekhilef, Member, IEEE, and Mohamad N. Abdul Kadir

Abstract—A three-stage 18-level hybrid inverter circuit and itsinnovative control method have been presented. The three hybridinverter stages are the high-, medium-, and low-voltage stages.The high-voltage stage is made of a three-phase conventionalinverter to reduce dc source cost and losses. The medium- and low-voltage stages are made of three-level inverters constructed usingcascaded H-bridge units. The novelty of the proposed algorithmis to avoid the undesirable high switching frequency for high-and medium-voltage stages despite the fact that the inverter’s dcsources are selected to maximize the inverter levels by eliminatingredundant voltage states. Switching algorithms of the high- andmedium-voltage stages have been developed to assure fundamentalswitching frequency operation of the high-voltage stages and notmore than few times this frequency for the medium-voltage stage.The low-voltage stage is controlled using SVM to achieve thereference voltage vector exactly and to set the order of dominantharmonics as desired. The realization of this control approach hasbeen enabled by considering the vector space plane in the stateselection rather than individual phase levels. The inverter has beenconstructed, and the control algorithm has been implemented. Testresults show that the proposed algorithm achieves the claimedfeatures, and all major hypotheses have been verified.

Index Terms—Inverters, power conversion harmonics,pulsewidth modulated inverters, pulsewidth modulation (PWM),voltage control.

I. INTRODUCTION

MULTILEVEL INVERTER (MLI) received considerableattention during recent years and has been widely rec-

ommended for high- and medium-power applications [1]–[3].Among the basic MLI topologies, cascaded H-bridge (CHB)is featured by its modular structure and linear relationshipbetween the numbers of inverter elements and levels. The maindrawback of CHB inverter is the need for large number ofisolated dc supplies [4]–[6].

Asymmetrical MLI, which results from supplying the CHBcells with different dc voltages, provides higher number oflevels for the same circuit topology [6]–[9]. The maximumnumber of levels is achieved when the cascaded-cell dc voltagesform a ratio-3 geometric sequence [10]–[14]. This ratio hasbeen used to construct inverters with large number of levelsand, consequently, very small voltage distortion for variousapplications [14], [15]. It has been found, however, that ratio-3

Manuscript received October 12, 2009; revised December 27, 2009,February 18, 2010, and April 8, 2010; accepted April 13, 2010. Date ofpublication May 17, 2010; date of current version March 11, 2011.

The authors are with the Department of Electrical Engineering, Univer-sity of Malaya, 50603 Kuala Lumpur, Malaysia (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2010.2049716

dc-sourced inverter is not appropriate for high-frequencypulsewidth modulation (PWM) control methods as the high-voltage stage is subjected to high switching frequency [11],[16], [17]. Asymmetrical inverters, like other CHB inverters,suffer from the need for large number of isolated dc supplies[18], [19].

Hybrid MLIs created by cascading smaller dissimilar invertercircuits can reduce the number of dc sources required [20].Hybrid inverters have been implemented in various designs,such as the following:

1) connecting a two-level three-phase inverter in series withthree-level stage(s) formed by full-bridge cells [21];

2) connecting H-bridge three-level stage(s) in series with aneutral-point-clamped three-level stage [22];

3) cascading two three-level neutral-point-clamped inverterby connecting their outputs to the two sides of an open-winding load [23];

4) in mixed-level topology, a superior full-bridge cell isconstructed using two arms of multilevel diode-clampedor flying-capacitor branches. Two l-level arms construct(2l − 1)-level mixed topology cell; therefore, the re-quired number of isolated dc supplies reduces [24], [25].

Other options have also been taken into consideration, suchas supplying all hybrid inverter stages using the same dc sourceand isolating the outputs using multiprimary transformer [26],[27]. This design is not suitable for drive application where theinverter operates in wide frequency range, including very lowvalues. Alternatively, one dc supply per phase has been used tosupply the high-voltage stage, while the lower voltage stageshave been connected to capacitors and controlled to supplyreactive power only [28], [29].

In this paper, the proposed topology based on type (1)indicated before has been chosen due to its sensible tradeoffbetween the cost and the number of levels. The number ofstages has been extended to three, and the number of levels hasbeen maximized by ratio-3-related dc sources.

Many studies have reported on the control of the MLI.Both high- and low-frequency switching approaches have beenconsidered. Examples of high-frequency switching include thecarrier-comparison PWM strategies, the space vector mod-ulation (SVM) and the carrier-based SVM. High-switching-frequency approach has been used generally with symmetricaltopologies, where effective amplitude control and harmon-ics reduction method is crucial due to the small number oflevels [30]–[35]. Among the low-frequency control strategiesare voltage vector approximation which has been applied forasymmetrical MLI [14], selected harmonics elimination which

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1340 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

has been implemented using switching angle lookup tables [6],and real-time-selected harmonic elimination [36], [37].

The approach of combining high and low switching frequen-cies for various stages of hybrid inverter has been consideredrecently [21], [26], where the major power supplying stageshave been operated in square wave mode, while the low-power quality-improving stage has been controlled by carrier-comparison PWM strategy. In [38], a nine-level three-stageasymmetrical cascaded MLI has been controlled with a hybridstrategy; the high-power cells have been operated at funda-mental frequency, while the low power stage is controlled byhigh-frequency PWM. The hybrid PWM (HPWM) algorithmpresented in [39] considered also the three-stage asymmetricalinverter with (1:2:6) dc voltage ratio to provide 19 levels. Three-level comparators have been used to produce the high- andmedium-voltage stage switching signals, while PWM modu-lator for low-voltage stage produces the complement to thereference voltage. The study states that the maximum numberof levels that can be operated in this mode has been adopted,and the optimum 27-level design is not suitable for this controlmethod.

A new method based on unidimensional geometric repre-sentation of one phase of MLI voltage levels has been pro-posed (1-DM) [40]. This method identifies the two nearestinverter voltage levels to the reference voltage and determinesthe duty ratios corresponding to the two levels by simplifiedcalculations. This concept has been applied to the symmetricaland asymmetrical CHBs and with various voltage ratios. Inanother paper “submitted for publication” [41], the authorshave shown that 1-DM, when applied to three-phase inverter,is equivalent to the conventional SVM control method withsimplified switching signal calculations. However, although notexplicitly mentioned but can be shown from the concept andresults, the control based on 1-DM subjects the high-voltagestage to high switching frequency when the number of levels ismaximized. The high-frequency operation period of the high-voltage stage will be very considerable when the amplitude ofthe reference voltage vector is just below the total minus thehighest stage dc voltages.

The modulation condition has been introduced to define thecascaded inverter which is suitable for PWM control as the oneat which switching between any two adjacent voltage levelsis achievable by controlling the lowest voltage stage whilefixing the states of other stages [9]. In order to ensure thatall transitions between adjacent voltage levels can be donethrough the low-voltage stage, only some state redundancy hasto be included, and the maximum number of levels must beabandoned. Previous studies have either chosen to satisfy themodulation condition and, therefore, not to design the inverterwith maximum number of levels; in this case, PWM controlcan be effectively considered as in [21], [26], [38], and [39].Otherwise, when the dc sources selected to provide maximumnumber of levels, PWM control leads to high-voltage stageoperating in high switching frequency as in [13] and [40].

The proposed control strategy is distinctive in enabling thehybrid inverter which has been designed with maximum num-ber of levels by ratio-3 dc sourcing to be PWM controlledwithout subjecting the high-voltage stage to high switching

Fig. 1. Three-stage 18-level hybrid MLI topology.

frequency. This has been enabled by involving the 2-D spacevector in the proposed hybrid strategy. In this algorithm, high-voltage stage will be operated in square wave mode. Themedium-voltage stage will be operated in low-frequency mode,while the low-voltage stage will be controlled by SVM at theintended switching frequency. An approach based on voltagevector decomposition has been developed to ensure the fre-quency conditions for high and medium stages and, at the sametime, to set the low-voltage stage in a valid SVM-controlledregion.

The inverter circuit topology, definition of the switchingvariables, and the inverter voltage vectors are described inSection II. The dual control concept is presented in Section III.In Section IV, the implementation of the power circuit and thecontrol strategy has been presented. Experimental results anddiscussion are given in Section V.

II. INVERTER TOPOLOGY AND SWITCHING STATES

The inverter circuit shown in Fig. 1 consists of the main high-voltage six-switch inverter with each output line in series withtwo single-phase full-bridge inverters. The main and H-bridgecells are fed by isolated dc sources of 9V s, 3V s, and V s. Thisvoltage ratio provides 18-level inverter. In this design, the high-voltage stage has only one dc source that operates with reducedcurrent ripple compared to the three dc sources of CHB design[13]–[16]. Therefore, considerable reduction in the number ofdc sources and losses can be achieved.

To explain the noncompliance to the modulation condition bythis design, consider the reference point 0 V in Fig. 1. Assumethat the output point A voltage is required to be changedbetween 4Vs and 5Vs. The sole option to produce 4Vs and 5Vsis to add up (0 + 3V s + V s) and (+9V s − 3V s − V s) fromthe three stages, respectively. If the reference voltage amplitudeis located between these two levels, there will be a carrierfrequency switching between the two states. This switchinginvolves all the three stages, including the high-voltage stage,and this is undesirable. The algorithm presented in the nextsection prevents the need for this kind of switching.

MEKHILEF AND ABDUL KADIR: NOVEL VECTOR CONTROL METHOD FOR THREE-STAGE HYBRID CASCADED MLI 1341

A. Voltage Vectors and Inverter States

The switching variables of the inverter are denoted by{(xabc), (yabc), (zabc)}, where x is a binary digit (x ∈ {0, 1})while y and z are trinary digits (y, z ∈ {0, 1, 2}). The states ofthe high-, medium-, and low-voltage stages are determined byxabc, yabc, and zabc, respectively. The output voltage vectorcan be represented in terms of switching state, as shown in thefollowing derivation. Line voltages are represented in terms ofthe switching variables in⎡⎣ vab

vbc

vca

⎤⎦=9VS

⎡⎣ xa − xb

xb − xc

xc − xa

⎤⎦+3VS

⎡⎣ ya − yb

yb − yc

yc − ya

⎤⎦+VS

⎡⎣ za − zb

zb − zc

zc − za

⎤⎦ .

(1)

Phase voltages of the Y-connected load can be represented asfollows:⎡⎣ νan

νbn

νcn

⎤⎦ =

13

⎡⎣ νab − νca

νbc − νab

νca − νbc

⎤⎦

=V s

3

⎡⎣ 2 −1 −1−1 2 −1−1 −1 2

⎤⎦

⎡⎣ 9xa + 3ya + za

9xb + 3yb + zb

9xc + 3yc + zc

⎤⎦. (2)

The voltage vector is achieved by Park’s transformationgiven in (3)

[νd

νq

]=

[1 −0.5 −0.50

√3

2 −√

32

] ⎡⎣ νan

νbn

νcn

⎤⎦ (3)

[νd

νq

]=Vs

[1 −0.5 −0.50

√3

2 −√

32

] ⎡⎣ 9xa + 3ya + za

9xb + 3yb + zb

9xc + 3yc + zc

⎤⎦ . (4)

Using (4), the voltage vector corresponding to any inverterstate can be achieved. Alternatively, the voltage vector diagramof the three-stage inverter is drawn by two superposition steps.First, the vector diagram of the three-level medium-voltagestage inverter is drawn at the end of each of the seven vectors ofthe high-voltage stage. Then, the vector diagram correspondingto the low-voltage stage has been superimposed at the ends ofresultant vectors, as shown in Fig. 2.

B. Voltage Vectors in g–h Axis System

The 60◦-spaced g–h coordinate system shown in Fig. 3 willbe used to represent the voltage vectors in the proposed controlalgorithm. This system allows straightforward calculations as itis tightly related to the inverter voltage vectors. The g–h voltagevector components for the high-voltage stage are given in

[νg

νh

]= 9Vs

[1 −1 00 1 −1

]⎡⎣ xa

xb

xc

⎤⎦ . (5)

Equation (5) can be applied to medium- and low-voltagestages after replacing the dc voltage (9Vs) by 3V s or V s andxabc by yabc or zabc. Equation (5) shows that the inverter

Fig. 2. Voltage vectors of the 18-level inverter.

Fig. 3. 60◦-spaced g − h axis system used to represent the voltage vectors.

vectors have g–h coordinates which are integer multiples of V s,allowing simple fixed-point calculations.

III. DUAL SVM CONTROL STRATEGY

A. High- and Medium-State Domains

Each of the 18-level inverter vectors can be represented bythe addition of three vectors that belong to high, medium, andlow stages. With the exception of the outmost vectors, most ofthe 18-level inverter vectors can be represented by more thanone combination of the three-stage voltage vectors, as for theexample vector V 1 shown in Fig. 2. To achieve fundamentalfrequency operation at high-voltage stage, the control algorithmexplained in the next section aims to hold the high-voltagestate as long as the reference vector can be reached by addingmedium and low vectors to this high-voltage state vector. Weshall define the hexagonal area marked by the medium- andlow-stage vectors superimposed on a given high-state vector byits domain. The seven domains of the high-voltage stage vectorsare shown in Fig. 4.


Fig. 4. High-voltage vector domains.

In Fig. 4, the large hexagon, which is the inverter vectorspace, is composed of seven partially overlapped high-statehexagonal domains. Some regions in the space belong toexactly one high-state domain without overlap, e.g., the regiondenoted by R1, which is covered only by the domain of statexabc = 011. If the reference vector is located in this area, thecontroller should select the corresponding high state. Otherareas are overlaps of more than one high-state domains, suchas R2 (R3), which is mutual between xabc = 010 and 011(xabc = 000, 110, 010, and 111). If the reference is located insuch region, there is more than one option in the selection ofxabc. The circular trajectory of the reference vector shown inFig. 4 passes through the six high-state domains consecutively,and the controller will change the high-voltage stage stateevery 60◦.

The domains of the middle stage vectors can be definedin a similar way. Nineteen hexagons that represent the areacovered by low-voltage stage vector diagram can be drawnwithin each of the seven high-state domains at the tips of the19 medium-voltage vectors, as shown in Fig. 5, within thedomain of xabc = 100. The medium-state selection determineswhich of the 19 hexagons is covered by the SVM control of thelow-voltage stage inverter.

By holding the state of high-voltage stage, medium-stagestate selection and SVM control of the low-voltage stage willcover the high-voltage stage domain area defined in Fig. 4,except the small 12 triangles at the outer side darkly shaded inFig. 5. To avoid any distortion that may result from the presenceof reference vector on the areas out of SVM-controlled low-voltage stage reach, a modified domain definition is introduced.The exact area covered by the SVM control of the low-voltagestage is the basic domain minus the 12 shaded triangles. Thedescription of the resultant domain, however, is quite compli-cated. Alternatively, we have elected the smaller hexagons of7V s sides marked with the dashed line in Fig. 5 as the mod-ified domains. The modified domain is entirely located in theSVM-controlled region and enables the use of the same algo-rithm to handle the basic (8V s) and modified (7V s) domains.

Fig. 5. Medium-stage domains corresponding to the high state xabc = 100;the dashed lines define the PWM high-voltage stage domains.

The difference between the basic high-state domain andthe modified domain is that, in the basic domain, there arecertain areas outside the reach of the SVM control and somedistortion will result if the reference vector is located in theseareas. The modified domain, on the other hand, is fully coveredby the SVM control areas. However, the maximum amplitudeof the reference vector, which is located within the modifieddomains, is 7

√3V s, while the maximum amplitude for the

basic domain is 8.5√

3V s, as shown in Fig. 5. Therefore, thebasic domain has higher maximum output amplitude by 21.4%,and we will test the controller using both domains.

B. Control Concept

The flow diagram of the control algorithm is shown inFig. 6. The reference vector is sampled at a sampling rateof Ts. During the sampling period, the controller determinesthe next switching states for high-, medium-, and low-voltagestages consecutively. The outputs of the high- and medium-stage routines are the values of xabc and yabc to be appliedduring the following sampling period. The low-voltage stageroutine determines the three vectors nearest to the low-stagereference and their corresponding duty ratios during the follow-ing switching period. The output of the low-voltage routine is aj-element state vector [zabc], rather than one state zabc. Duringthe following sampling period, zabc will take the values of thesevector elements consecutively for subperiods of Tc(= Ts/j).

C. Determination of High and Medium States

Initially, the reference vector is converted to its g–h compo-nents using the following equations:

gref = |Vref | ×(

cos θref −sin θref√

3

)

href = |Vref | ×(

2 sin θref√3

). (6)


Fig. 6. Flow diagram of the control algorithm.

The calculation of xabc(yabc) begins by determining if thereference vector is located in the domain of the current high(medium)-voltage state by comparing the reference absoluteg–h coordinates to the first quadrant portion of the domain, asshown in Fig. 6. If so, xabc(yabc) holds its value during the nextswitching interval.

If the reference vector is not within the current state domain,the new high (medium) switching state will be calculated asfollows.

1) The reference vector is compared to the seven high(19 medium) domains, and a short list of the feasiblestates for the next switching period is generated, wherethe feasible state is any state that has the reference vectorlocated in its domain.

2) If the feasible state list has one element, this state will bethe next high (medium) state (end).

3) Otherwise, the feasible state list is compared to the initialstate, and the state with minimum difference is taken asthe next state.

D. Low-Voltage-State Voltage Vector Control

The low-voltage stage is composed of a three-level inverterand has been controlled using the voltage vector control strat-egy. The control routine is carried out according to the follow-ing steps.

1) The three inverter states nearest to the reference stateand the corresponding duty ratios have been determinedfollowing the procedure presented in [31]. This proce-dure is found suitable as it applies a 60◦-displaced axissystem to determine the inverter vectors and the duty

Fig. 7. Types of the three-level inverter triangles.

ratios. However, the aforementioned reference providesno information about the sequence of sorting the inverterstates.

2) The inverter is operated in four switching states withineach sampling interval Ts to realize the reference vector.The first and last switching states are equivalent. The statesequence has been determined first by identifying the typeof the triangle in which the reference vector is locatedaccording to Fig. 7. The three types of the triangles aredefined as follows.i) Type 1: The triangle is formed by two outer vectors

and one inner vector.ii) Type 2: The triangle is formed by one outer vector and

two inner vectors.iii) Type 3: The triangle is formed by zero and two inner

vectors.


The outer vectors are associated with unique switchingstates and the inner six vectors are associated with twoequivalent switching states, while the center zero vectoris associated with three zero states. In Fig. 7, the outervector states are denoted by (λ). The inner vector statesare denoted by (σ1, σ′

1, σ2, and σ′2), where the three

trinary digits (zabc) of σ1 state are composed of one (13)and two (03) digits, where the subscript indicates that thedigit is trinary. State σ′

1 is equivalent to σ1 but with one(23) and two (13) digits. On the other hand, σ2 has one(03,) and two (13) digits in its trinary expression, whileσ′

2 is its equivalent of one (13) and two (23) digits.The state sequence has been assigned in a way that

each switching interval starts and ends with equivalentstates and there is one switching variable transition as-sociated with any switching action, and therefore, oneswitching pulse per switching variable (za, zb, or zc)occurs every 2Ts. According to the reference triangletype shown in Fig. 7, the state sequence over 2Ts isassigned as follows:Type 1: (σ-λ1-λ2-σ′-λ2-λ1-σ) or (σ-λ2-λ1-σ′-λ1-λ2-σ);Type 2: (σ1-σ2-λ-σ′

1-λ-σ2-σ1) or (σ2-λ-σ′1-σ′

2-σ′1-λ-σ2);

Type 3: (ζ-σ1-σ2-ζ ′-σ′1-σ′

2-ζ ′′), (ζ ′-σ2-σ1-ζ-σ1-σ2-ζ ′), or(ζ ′′-σ′

2-σ′1-ζ ′-σ2-σ1-ζ).

3) The state sequence and duty ratio information are ex-panded to form the switching state vector [zabc] with thefour switching states repeated proportionally to their dutyratios. As indicated earlier, this vector has j elements;consider, for example, type 1 triangle, and assume thatthe sequence (σ, λ1, λ2, σ

′) is to be followed accordingto the nearest state criteria. Denoting the duty ratios ofstates σ, λ1, and λ2 by dσ , dλ1, and dλ2, respectively, thelow-stage state vector will be of the following form:

zabc(1 : j) =

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

σ...σλ1...

λ1

λ2...

λ2

σ′...σ′

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

← zabc(1)...

← zabc(nσ)← zabc(nσ + 1)

...← zabc(nσ + nλ1)

← zabc(nσ + nλ1 + 1)...

← zabc(nσ + nλ1 + nλ2)← zabc(nσ + nλ1 + nλ2 + 1)

...← zabc(j)

(7)

where

nσ = round(j∗dσ/2) (8)

nλ1 = round(j∗dλ1) (9)

nλ2 = round(j∗dλ2). (10)

In (8)–(10), “round” stands for rounding to the nearestinteger.

Fig. 8. Experimental setup.

IV. EXPERIMENTAL SETUP DESCRIPTION

A prototype of the proposed inverter has been implemented.The low- and medium-voltage stages need bidirectional currentsupply and have been supplied by 12-V −5.5-A · h lead acidbatteries. Three series-connected units are used for the medium-voltage stage to supply 36 V. Batteries have been chosen dueto the small inverter ratings and to avoid the complexity andcost of electronic converter supplies, as the inverter basicallyneeds six bidirectional dc supplies besides the main dc unidi-rectional supply, assuming a nonregenerative load. The high-voltage stage has been fed 108 V using the laboratory dc powersupply. For high- and medium-voltage stages, insulated-gatebipolar transistors are used, while MOSFETs have been usedfor the low-voltage stage. A 0.9-kW 380-V 50-Hz four-poleasynchronous motor has been used as a load.

The control algorithm has been implemented using a DSPcontroller board eZdsp R2812 based on the 150-MHz fixed-point TMS320R2812 CPU. The sampling time (Ts) for theouter loop has been set to 111 μs.

The sampling period has been divided to (j =)100 subinter-vals; therefore, the 50-Hz reference voltage will be representedby (1 ÷ (50 × 111 μ) =)180 samples. The low-stage state willhave a period of 2Ts or a switching frequency of 4.5 kHz,assuming that the final state could be taken as the initial statefor the following period. The consequence of selecting j of 100is that the minimum switching pulsewidth for the low-voltagestage will be 2Ts/100.

One of the 16-b digital ports has been allocated for inputand another port for output. Eight out of the 16 input portbits have been allocated for the reference vector amplitude,where the voltage vector that has a norm of V s is representedby (10)H . The base or 100% reference amplitude is taken asthe radius of the largest circle that can be drawn inside theinverter hexagonal vector space. The radius of this circle is(17V s ×√

3/2 =)14.722V s and, according to the definedscale, is equivalent to (EC)H .

Fifteen out of the 16-b output port has been used to providethe switching signal. Each arm of the two- and three-levelsubinverters is driven by 1 b. An external logic circuit has beenused to decode the switching signals and insert blanking time,as shown in Fig. 8.

V. EXPERIMENTAL RESULTS AND DISCUSSION

Two modes have been tested: The first implements the basichigh-state hexagonal domain of side length that is equivalent


Fig. 9. Phase-voltage measurement with 80% amplitude and 50-Hz frequencyreference. (a) Phase-voltage waveform. (b) Frequency spectrum of the phasevoltage.

Fig. 10. Switching pulses with M = 0.9. From the top: (C1) High-voltagestage, (C2) medium-voltage stage, (C3) low-voltage stage, and (Z3) time axis×50 zoom in the low-voltage stage switching pulses shown on C3.

to 8V s, whereas the second uses the modified domain of sidelength that is equivalent to 7V s, as indicated in Section III andshown in Fig. 5.

A. Inverter Characteristics With Basic High-State Domain

Fig. 9 shows the measured phase-voltage waveform and itscorresponding frequency spectrums with sinusoidal referenceof 80% amplitude and 50 Hz. The total harmonic distortion(THD) is less than 2%, reflecting low distortion of the outputvoltage, and Fig. 9(b) shows that the dominant harmonics orderis around 180, which is the number of sampling intervals percycle.

Fig. 10 shows the switching signals of the three stages. Thetop signal verifies that the high-voltage stage operates in squarewave mode, the second signal shows that the medium stageoperates at an average switching frequency that is equivalentto four times the fundamental frequency, and the third is the

Fig. 11. Phase voltage due to the switching signals shown in Fig. 10. From thetop: Voltage due to high-voltage stage only, voltage due to high- and medium-voltage stages, and voltage due to the three stages.

Fig. 12. THD variation against the reference amplitude (%) for the outputvoltage produced by both the basic (8 Vs) and the modified (7 Vs) domains.The suggested domain switching is indicated.

switching signal for the low-voltage stage. As the low-voltagestage signal is not visible on the same timescale, a horizontalzoom in 1-ms interval (9Ts) is shown at the bottom of Fig. 10.This waveform shows 4.5 pulses during this interval, whichconfirms what has been mentioned in Section IV that the low-voltage stage switching signals have one pulse every 2Ts.

In Fig. 11, the top waveform shows the load phase voltagedue to the high-voltage stage only, and the middle waveform isdue to the high- and medium-voltage stages. The voltage waveat the bottom of Fig. 11 is the total voltage resultant from thethree stages corresponding to the switching signals of Fig. 10.

THD variation with the reference voltage amplitude is shownin Fig. 12 with the solid line. The output voltage has lowharmonic distortion over a wide range of M . The high THDexperienced when M < 0.2 is due to the fewer number of levelsavailable to form the output voltage, as shown in Fig. 13(a). Asshown in Fig. 13(b), the frequency of the dominant harmonics isaround 9 kHz, or 1/Ts, and this is twice the average switchingfrequency of the low-voltage stage.


Fig. 13. Phase-voltage measurements with M = 9.4% and 50-Hz frequencyreference. (a) Phase-voltage waveform. (b) Frequency spectrum of the phasevoltage.

Fig. 14. Basic domain phase voltage with reference amplitude = 45%.

It can be noticed in Fig. 12 that there is a rise in the harmonicdistortion when the reference amplitude, or the magnitude con-trol ratio M , is around 45% and 65%. To investigate the causeof THD rise, consider the measured phase-voltage waveformwith a reference amplitude of 45% in Fig. 14; the waveformhas a defect almost every 30◦. With this reference voltage am-plitude, the reference vector is always located in the zero highstate’s domain. Therefore, the high-voltage stage will alwaysproduce zero voltage. The reference vector, however, passesthrough the 12 triangles not covered by the SVM control regionof the low-voltage stage shown in Fig. 5. In these regions, theresultant low reference is out of the low-voltage stage vectorspace, and this causes the distortion.

Fig. 15 shows that, within the two rings where 0.41 < M <0.47 and 0.65 < M < 0.71, as the reference voltage rotates, itwill be subjected to pass through the triangular areas outsidethe PWM control region.

Fig. 15. Two rings show the area at which the inverter is prone to highdistortion using the basic high-state domain.

Fig. 16. Shaded ring represents the range of reference amplitude at which theinverter is prone to distortion.

B. Inverter Characteristics With Modified High-State Domain

We have diagnosed the distortion in the waveforms for cer-tain ranges of M that occurs when the reference voltage vectorfalls on the part of the high domain which is not covered bythe PWM control range of the low stage. At this step, we willexamine the characteristics of the inverter when the modifiedhigh-state domain is considered. As the 7V s hexagon is entirelyunder the PWM control, we can obtain full PWM for anyreference voltage amplitude less than 82%, as shown in Fig. 16.

This hypothesis has been verified by the output voltagemeasurement with a reference amplitude of 45%, as shown inFig. 17. In Fig. 17(a), the defects in phase-voltage waveform


Fig. 17. Measurements with modified 7V s high-state domain and 45% refer-ence amplitude. (a) Phase voltage, 50 V/div, 10 ms/div. (b) High-voltage stageswitching signals. (c) Phase voltage corresponding to high stage only. (d) Phasevoltage corresponding to medium- and low-voltage stages.

examined in Fig. 14 are cancelled. To explain the high-voltagestage controller performance for the measurements shown inFig. 17, assume initially that the reference vector is located

Fig. 18. Phase voltage with M = 0.9 and modified 7V s high domain(50 V/div; 5 ms/div).

within the zero state’s domain. As the reference vector anglechanges, the reference vector will be outside this domain at areference angle of about −43◦, which is point P1 in Fig. 16. Atthis angle, the high-state controller changes the high state fromzero to state x = 100 and holds this state until the referencevector leaves this domain when its angle becomes about +43◦,which is point P2 in Fig. 16. At this point, the controller hascompared state 100 to the three next feasible states (000, 110,and 111), and the controller based on the minimum switchingaction criteria will select either state 000 or 110, as they areequally distant from the present state (100). Fig. 17(b) showsthat state 000 has been selected; this is a zero state that remainsas the high-voltage state until point P3, which is 120◦ afterpoint P1. As shown in Fig. 17(b), the inverter selected state010 after P3. The resultant phase voltage due to the high-voltage stage only is shown in Fig. 17(c). The positive pulsecorresponds to the case when x associated with that phase isone, and the other two x bits are zeros. The two negative pulsesare due to the case when the x that is not associated to thatphase is one, and the zero levels between the pulses are due tothe zero states.

While the 7V s domain solves the PWM domain problemat the two ranges of reference amplitude shown in Fig. 15,Fig. 16 shows that the proper SVM operation will be lost as thereference amplitude exceeds 82%. To show this, examine thephase-voltage waveform with 90% reference amplitude shownin Fig. 18; the improper selection of the high state causes adefect almost every 60◦. The THD over the entire range ofreference amplitude drawn with dashed line in Fig. 12 showsthat, for the range 0 < M < 0.8, the selection of 7V s highdomains has cured the problem of increased distortion aroundM = 0.45 and M = 0.65. However, we can notice a fast rise inharmonic distortion for M > 0.8.

From the THD characteristics of the two domains (8V s and7V s), it can be realized that the problems of intermitted rangedistortion associated with the basic high-state domain and highdistortion for M > 0.8 associated with the modified domaincan be avoided by setting the domain of 7V s for M < 0.8 andof 8V s for M > 0.8. This solution will not disturb the high-voltage stage switching frequency or the maximum number oflevel advantages of the proposed inverter. The proposed modeswitching region and resultant THD characteristics are shownin Fig. 12.


TABLE ICOMPARISON OF THE PROPOSED ALGORITHM WITH THE HPWM AND 1-DM ALGORITHMS

C. Comparison With Other Control Algorithms

A comparison between the proposed algorithm and two otherrecently reported algorithms is shown in Table I. The algorithmsindicated in Section I are the HPWM algorithm described in[39] and the 1-DM method reported in [40] and [41], as bothmethods are proposed as alternatives for the basic PWM andSVM techniques for MLIs. Moreover, both methods are suit-able for multistage inverters; indeed, the HPWM is exclusivelyapplicable for multistage inverters.

VI. CONCLUSION

In this paper, a three-stage 18-level inverter and its innovatedcontrol strategy have been presented. The inverter has beendesigned with one main dc source to reduce the dc supply cost,and the supply voltage ratio has been selected to maximize thenumber of symmetrical levels. While this design is known tobe unsuitable for carrier-based PWM control as it subjects thehigh-voltage stage to high switching frequency, the suggestedcontrol method has been proven to avoid this problem.

In the proposed algorithm, the high-voltage stage switchingfrequency equals the output fundamental frequency, and themedium stage operates at no more than five times this fre-quency. The SVM method is used to control the low-voltagestage which operates at an average frequency that is equivalentto half the sampling frequency and provide all the SVM controladvantages.

The suggested strategy has been tested using fixed-point low-cost DSP controller card, and owing to the 60◦ coordinate sys-tem, the controller execution speed is shown to be satisfactoryfor most applications. During the experimental testing stage, thedistortion problem that occurs with certain reference amplitudehas been addressed. To solve this problem, simple modificationhas been introduced and tested without compromising any ofthe system features.

The experimental results prove the hypothesis regardingthe switching frequency and show that the proposed inverterprovides very low harmonic distortion over a wide range ofthe modulation index, and the dominant harmonic frequencyis around the sampling periods or twice the low-voltage stageswitching frequency.

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Saad Mekhilef (M’01) received the B.Eng. degreein electrical engineering from the University of Setif,Setif, Algeria, in 1995 and the Master of EngineeringScience and Ph.D. degrees from the University ofMalaya, Kuala Lumpur, Malaysia, in 1998 and 2003,respectively.

He is currently an Associate Professor with theDepartment of Electrical Engineering; University ofMalaya. He is the author and coauthor of more than100 publications in international journals and pro-ceedings. He is actively involved in industrial con-

sultancy for major corporations in the power electronics projects. His researchinterests include power conversion techniques, control of power converters,renewable energy, and energy efficiency.

Mohamad N. Abdul Kadir was born in Mosul,Iraq, in 1967. He received the B.S. and M.S. de-grees in electrical engineering from the Universityof Mosul, Mosul, in 1988 and 1992, respectively.He has been working toward the Ph.D. degree in theDepartment of Electrical Engineering, University ofMalaya, Kuala Lumpur, Malaysia, since 2007.

Since 1992, he has joined several academic insti-tutes in Iraq and Malaysia as a Lecturer. His researchinterests are in the areas of power electronics andelectrical drives.

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