November 7, 2013

Welcome Jane Celusak is a program manager supporting industry consortia on behalf of IEEE-ISTO including Nexus 5001 Forum. Jane works closely with the industry consortia leadership to develop new initiatives to support the strategic directions of organization and acts as a liaison between programs and other IEEE-SA support functions. Jane has over 15 years’ experience in business and organizational development and external, customer and foundation relationship management. She has a MA in Public Policy and International Affairs.

Let’s Get Started!

Randy Dees Randy Dees is a Senior Member of the Technical Staff at Freescale Semiconductor, working in the 32-bit Automotive Microcontroller Applications group supporting highly integrated advanced MCUs with embedded Flash memory. He graduated from the University of Houston in December 1980 and began working at Motorola Semiconductor in January 1981. Motorola later spun the semiconductor group off as Freescale. He has worked in both Product Engineering and Application supporting 8- to 32-bit microprocessors, integrated circuits for telecommunications, and 32-bit microcontrollers. He has been working with Nexus-based MCUs since 1999 and has been either the co-chairman or the chairman of the IEEE-ISTO 5001 Nexus Consortium’s technical subcommittee since 2000.

Nexus 5001 Forum

What is Nexus? Nexus is an industry standard debug standard for embedded microcontrollers.

Growing out of a white paper written in 1998 from Freescale (then part of Motorola) along with Agilent Technologies (then HP) on a new debug standard, the Nexus Consortium joined forces with the IEEE-ISTO to release the first version of the standard, the IEEE-ISTO 5001-1999.

The standard was updated in 2003 to address enhancements and minor oversights (IEEE-ISTO 5001-2003). An additional update was released in 2012 that adds support for the IEEE 1149.7 and Nexus messaging over an Aurora protocol link.

The standard covers not only the debug protocol but also the pin interface and connectors, driving a new level of standardization

To date, Nexus is implemented on MCU devices from several semiconductor companies on a wide variety of core types. Information on the Nexus Consortium can be obtained at www.nexus5001.org

Nexus Class Definition

8

The Nexus standard defines debug from Class 1 (static debug) all the way through to Class 4 with memory substitution and port replacement

Run Control

Memory and

Port Substitution

Class 1

Run Time Control

Class 2

Dynamic Debug

Class 3

Data Trace

Class 4

Advanced Debug

Nexus Members

Agenda Introduction of Webinar contents and presenters - Jane

Celusak, IEEE-ISTO

Description of GM tool set; debugger, trace, M/C, RPC - Norm D’Amico – GM

Lauterbach debugger + high speed trace demonstration - Udo Zoettler – Lauterbach

M/C tool Demo, bypass + e-hooks demo and Multi tool use case – M/C + debugger/trace arbitration demo - Steve Rosenthal-ETAS

Overview of IC’s supporting the Nexus 5001 Standard- Randy Dees, Freescale Semiconductor

Q+A - Jane Celusak, IEEE-ISTO

Presenter Norm D'Amico is a Staff

Engineer at General Motors working as a Team Leader in Global Powertrain ECU Development Tools.

Norm works with the Tier-1 ECU suppliers and the Tier-2 tool suppliers to insure that GM's requirements are implemented properly on development ECUs. Norm has also worked in tool development and software integration roles while at GM.

Prior to GM, Norm held several positions at ERIM (since acquired by General Dynamics) in the development of electronic hardware and software for synthetic aperture radar (SAR) systems.

Norm received his B.S. in Electrical Engineering from Wayne State University in 1986, and has been involved in embedded electronic systems his entire career.

Norm D’Amico, General Motors

Opening Remarks

Today’s material is a natural progression from the information that was presented at last year’s webinar (Use of Nexus Based Software Development Tools for Powertrain ECUs)

The focus today will be to demonstrate some of the Nexus based development tools that are currently being used in industry

13

GM Tools Overview

GM Powertrain has developed instrumentation strategies that are used across entire generations of ECU programs, including:

ECMs (Engine Control Modules)

TCMs (Transmission Control Modules)

Hybrids (Hybrid Control Modules)

The Nexus-based instrumentation strategies have promoted reuse of the development tools and have helped GM to save both time and money

14

GM Tools Overview

There are 3 primary tool sets used in the development of ECU software and calibration at GM

Software debugging / trace tools

Measurement and calibration tools

Rapid prototyping tools

15

Software Debugging / Trace

Allows developers to find and correct software issues

16

MPC56xx

Ve

rtiC

al

LAUTERBACH

ECU (Development Controller)

ethernet or USB

ETAS

XETK-V2

Nexus I/F

Samtec connector

Developer’s PC

Nexus Class 3+,

JTAG, A/D Bus

Software Debugging / Trace

Typical bench set up for software debugging and trace

17

ETAS XETK-V2 (inside)

ECU

Lauterbach LA-7690

Lauterbach LA-7630

Lauterbach Samtec Adapter

Lauterbach LA-7931

ETAS ES600

Measurement and Calibration

Allows calibrators to adjust/tune calibration values (constants), and to measure key ECU parameters

18

MPC56xx

Ve

rtiC

al

ECU (Development Controller)

ETAS

XETK-V2

Developer’s PC

Nexus Class 3+,

JTAG, A/D Bus

ethernet ETK I/F

LEMO connector

Measurement and Calibration

Typical set up in a development vehicle

19

development controller in a vehicle connected

to the M&C Tool

Rapid Prototyping

Allows developers to test new ideas and experiment without changing code in the ECU

20

Ve

rtiC

al

ECU (Development Controller) LVDS

connector

Ve

rtiC

al

RCP

Nexus I/F

RCP I/F

dSPACE

DS543

ethernet

ETAS

XETK-V2

Developer’s PC

MPC56xx

Nexus Class 3+,

JTAG, A/D Bus

Rapid Prototyping

Used in development vehicles and on benches

21

Presenter Udo Zoettler works at

Lauterbach, Inc. and has been a Sales/Marketing Manager for the last 17 years. Udo's work is focused on sales and customer acquisition as well as providing training classes to end customers for Lauterbach debugger products used in automotive and embedded systems software development. Prior to Lauterbach, Inc., Udo held a sales/marketing manager position at Krohn & Stiller. Udo received his MSE from the Technical University Ilmenau, Germany, in 1989.

Udo Zoettler, Lauterbach

TRACE32

PowerTrace II 2nd Generation Debug Tools

for

Nexus Aurora HSTP Interface based

Microcontrollers (MPC57xx)

Real time debugging and trace analysis Embedded software in engine and transmission

controllers needs to be tested and validated for

performance, safety and quality assurance.

The utilization of the NEXUS class3 debug interface

on the microcontroller allows the Lauterbach

debugger real time access to all cores to display

source code and to have read/write access to data

memory without interference with the cores‘ real time

code execution.

Today’s focus will be to demonstrate multi core debug

and high speed serial trace features on 3 e200Z4

cores based on a freescale MPC5746M (McKinley)

device

PowerTrace II Real Time Trace and Debugger Gigabit Ethernet + USB host interfaces

Support for Nexus Aurora HSTP

up to 4 lanes of high speed serial trace

6Gb/sec bandwith per lane

Up to 4 GByte trace memory

Program execution and data r/w history

trace

Performance Analyzer

Function Runtime Analysis

Code Coverage Analysis

Real Time System Performance Analysis

History based Trace debugging: CTS

Long Term Trace Recording through

Streaming Mode

LA-7699: PowerDebug II

LA-7694: PowerTrace II 4GB

LA-3911: Pre Processor

MPC57xx Nexus Aurora

LA-3738: Debugger Bundle AUTO26

LA-3871: Conv.

Samtec40 HSTP +

AUTO26 to Samtec34

Freescale Eval Board

MPC5746M with JTAG14

and Nexus standard

Samtec34 interfaces

Typical Debug Tool Setup

NEXUS class3 debugger Run control: Single Step, Run, Break, Breakpoints

Source code listing

Read/Write real time memory access

Flash programming

Real time Trace: Program execution, Data r/w

history

Advanced features: Function Runtime Analysis,

Code Coverage Analysis, Performance Analysis,

History based trace debugging

Long Term Streaming Mode real time trace

Run control, Source code listing, r/w real time memory access

Switch to Lauterbach debugger demo

Presenter Steve Rosenthal is a senior software engineer at ETAS, where he has been involved in vehicle diagnostic solutions, M/C tool (INCA) development and integration, and Rapid Prototyping software (EHOOKS). Prior to joining ETAS, Steve worked at Hewlett-Packard for a number of years as a software engineer and consultant. Steve received his BS degree in Mathematics/Computer Science from Lawrence Technological University, Southfield, MI in 1987.

Steve Rosenthal

Randy Dees Randy Dees is a Senior Member of the Technical Staff at Freescale Semiconductor, working in the 32-bit Automotive Microcontroller Applications group supporting highly integrated advanced MCUs with embedded Flash memory. He graduated from the University of Houston in December 1980 and began working at Motorola Semiconductor in January 1981. Motorola later spun the semiconductor group off as Freescale. He has worked in both Product Engineering and Application supporting 8- to 32-bit microprocessors, integrated circuits for telecommunications, and 32-bit microcontrollers. He has been working with Nexus-based MCUs since 1999 and has been either the co-chairman or the chairman of the IEEE-ISTO 5001 Nexus Consortium’s technical subcommittee since 2000.

Nexus 5001

Qorivva Automotive MCU Roadmap

Execution

Production

Gen 1*

Gen 2

Gen 3 Gen 4 No timer system

GTM timer system

eTPU timer system

MPC5777C

MPC574xP

MPC5746R

MPC5777M

MPC5775K

MPC5746M

MPC574xG

MPC574xC

MPC560xE

MPC560xB/C/D

2003 2008 2012 1998

MPC564xA

MPC563xM

MPC564xL

MPC567xK

MPC566xG/E

MPC5676R

MPC567xF

MPC564xB/C

MPC564xS

MPC560xP

MPC560xS

MPC565

MPC563

MPC555

MPC561

MPC566

MPC564

MPC562

Separate security module

Supports functional safety

MPC5565

MPC5561

MPC5553

MPC5534

MPC5566

MPC5554

MPC5567

MPC5510

* Not considered Qorivva devices.

MPC5777M and MPC5746R to be announced November 2013.

TM

Key Functional Characteristics • Two independent 200 MHz Power Architecture z4

computational cores Single 200 MHz Power Architecture z4 in lockstep

• eDMA – 64 channels (w/ lockstep DMA) • 4M Flash with ECC • 320k total SRAM with ECC 256k of system RAM (incls. 32k of standby RAM) 64k of tightly coupled data RAM

• 3 ΣΔ ADC converters – 12 channels • 4 SAR converters – 52 channels • Cross Triggering Unit • Ethernet (MII-lite/RMII) • DSPI – 7 channels (2 supporting µSec channel) • LINFlex - 6 channels (2 supporting µSec channel) • FlexCAN – 4 chls, 2 w/ flexible data rate capability • SENT – 6 channels • 2 eTPU2+ timers – 64 channels • 1 eMIOS – 32 channels • Reaction module – 10 channels

Key Electrical Characteristics

• -40 to +125 °C (ambient) • Single 5v power supply

Package • 176 LQFP, 252 MAPBGA • 292 MAPBGA eCal package (incls. RAM buddy chip)

for emulation/debug

Enablement • Software : AutoSAR drivers • Tools : Debugger (Lauterbach), multicore compiler

(Wind River and Green Hills)

MPC5746R 4M Block Diagram

TM

MPC5777C 8M Block Diagram

COMPUTATIONAL SHELL

8.25MB Flash (4x64kB EEPROM)

512k SRAM (48k Standby)

SRAM Control

CACHE 16k D-Cache

External Bus

Interface

16k I-Cache

VLE

FPU

MPU

Cross Bar Switch with ECC – 132MHz

STM

INTC

SWT

DEBUG

Flash Control

MMU

Bridge B

Bridge A

DTS

MMU

Nexus 3+

JTAG PowerPC™

e200420

e200Z7 lock-step

STM

INTC

SWT

2 x eTPU2+

16ch eMIOS

FCCU

3 x eSCI

2 x DSPI

CMU

(I) Glitch Filter

1 x eQADC

1 x PSI5

PMU

2 x SIUx

1 x MCAN-FD

2 x FlexCAN

Confidential and Proprietary

1 x MC

AN

-FD

8ch

Reactio

n

FM

PL

L +

PL

L

CR

C (3ch

)

16 x

Sem

aph

ores

DT

S fo

r DA

Q

Safety M

od

ule

DT

M (N

exus)

Tem

p S

enso

r

1 x eTP

U2+

4 x P

IT

1 x PS

I-5

16 ch

eMIO

S

1 x Zip

wire

1 x eQA

DC

12 x DE

CF

IL

3 x DS

PI (M

SB

)

3 x eSC

I (MS

B)

PA

SS

/ TD

M

CS

E2

BA

M

2 x FlexC

AN

64ch eDMA SPE1.1

16k D-Cache

16k I-Cache

VLE

MMU

FPU

SPE1.1

e200Z7 (dual issue)

e200Z7 (dual issue)

SRAM Control

64ch eDMA

Ethernet

Zipwire

SECURITY

CSE2

Cores & Memory • Two independent z7 dual issue computational cores @ 264MHz

• Cores include VLE, SPE1.1, FPU , MMU • 16kB i-cache & 16kB data-cache w/ coherency

• Single z7 lockstep core @ 264MHz (for ISO26262 and ASIL-D) • Up to 8.25MB Flash RWW w/ ECC including 4 x 64kB EEPROM • Up to 589kB total SRAM

• 512kB on chip static RAM w/ECC (up to 48KB standby) • 45kB eTPU RAM , 32kB data cache (w/line locking)

• Security • PASS and TDM (Tamper Detection) • CSE2 (Crypto Services Engine for Encryption & Secure Boot)

I/O & System • Up to 70ch eQADC from 4 converters w/12bit resolution

• On-chip temperature sensor and VGA (x1,x2,x4) • 12 x Decimation Filters w/ hardware knock integrators

• Timers – up to 128 channels (96ch eTPU2+ and 32ch eMIOS) • 2 x 64ch eDMA support (128ch total) • 6 x CAN ports (4 x FlexCAN + 2 x MCAN with Flexible Datarate)

• Ethernet • DSPI – 5 channels (2 supporting µSec ch.) • eSCI – 6 channels (2 supporting uSec ch.) • Reaction module – 8 channels for current control • Up to 12ch SENT, Zipwire, 2ch PSI-5 • 1 x CRC unit – w/ 3 independent channels, • 4 x protected port outputs, MPU and MMU • FMPLL + PLL • Safety Monitors – e2eECC, CLK, Voltage, Fault Collection

Packaging & Enablement • 416 PBGA, 516 PBGA • Calibration – VertiCal (using 552CSP)

SENT

Optional Content: • 300MHz per core • 4 x Sigma Delta ADCs (up to 20ch, 16bit)

TM

MPC5777M 8M Block Diagram Key Functional Characteristics

• Two independent 300 MHz Power Architecture z7 computational cores Single 300 MHz Power Architecture z7 core in delayed

lockstep for ASIL-D safety

• Single I/O 200 MHz Power Architecture z4 core • eDMA controller – 128 channels • 8M Flash with ECC • 596k total SRAM with ECC 404k of system RAM (incls. 64k standby) 192k of tightly coupled data RAM

• 10 ΣΔ & 12 SAR converters – 84 channels • Ethernet (MII/RMII) • DSPI – 8 channels (3 supporting µSec ch.) • LINFlex - 6 channels (3 supporting µSec ch.) • MCAN-FD/TTCAN – 4x modules/1x module • GTM – 248 timer channels

Key Electrical Characteristics

• -40 to +125 °C (ambient) • 165 °C junction for KGD • 1.26V Vdd, 5.0V I/O, 5V ADC

Package • 292 PBGA, 416 PBGA, 512 PBGA • eCal emulation device for each package

Enablement • Software: AutoSAR drivers • Tools

Debugger: Green Hills, Lauterbach and PLS Multicore compiler: HighTec, GCC, Wind River & Green

Hills Simulation tools

TM

MPC5746M 4M Block Diagram Key Functional Characteristics

• Two independent 200 MHz Power Architecture z4 computational cores Single 200 MHz Power Architecture z4 core in delayed

lockstep for ASIL-D safety

• Single I/O 200 MHz Power Architecture z4 core • eDMA controller – 64 channels • 4M Flash with ECC • 320k total SRAM with ECC 128k of system RAM (incls. 64k standby on 292 PBGA pac

kage) 192k of tightly coupled data RAM

• 6 ΣΔ & 8 SAR converters – 60 channels on 292 MAPBGA, 48 channels on 176 LQFP

• Ethernet (MII/RMII) • DSPI – 7 channels (2 supporting µSec ch.) • LINFlex - 5 channels (2 supporting µSec ch.) • MCAN-FD/TTCAN – 3x modules/1x module • GTM – 120 timer channels

Key Electrical Characteristics

• -40 to +125 °C (ambient) • 165 °C junction for KGD • 1.26V Vdd, 5.0V I/O, 5V ADC

Package • 176 LQFP / EP, 292 PBGA • eCal emulation device for each package

Enablement • Software: AutoSAR drivers

• Tools Debugger: Green Hills, Lauterbach and PLS Multicore compiler: HighTec, GCC, Wind River, GHS Simulation tools

TM

MPC5744P 2.5M Block Diagram Core • Dual up to 200 MHz PowerTM ISA e200 core ( e200z420) • 32 bit Reg File, 64 bit BIU with E2E ECC, • 64kB RAM of D-LMEM with MPU for fast context switch + local data • 8KB 2-way I-cache / 4KB 2-way D-Cache • 1x Scalar FPU (compiler supported) per core • Safety enhanced Cores – VLE only • No Signal processing unit extension + NO MMU • Delayed Lock Step configuration only

Memory • 2.5 MBytes NVM with ECC (with add. Safety measure for address). • 64kB EEE (Data Flash) available incl. ECC • Up to 384 Kbyte global system SRAM with ECC (Addr + Data) I/O • 3 x FlexCAN (64+2x32 message buffers) • 1 x FlexRay (Dual Channel 64 msg. buffers) • 2 x LINFlex (Uart/Lin protocol driver) • 4 x DSPI (4 cs each) • 2x FlexPWM (2x 12ch for 2 independent Motors Controlled) • 3 x eTimer modules (18 channel total) • 4 x SAR ADC – 1MS/s target 5V input capable • 2 x Cross-triggering unit for motor control automatism • 2x SENT • Ethernet (257BGA only)

System • Interprocessor I/F SIPI (– approx 300Mbaud) • Safe DMA • Fault Collection unit, WDG, T-sens, & CRC computing unit • Nexus debug interface – Aurora • Dual-PLL (Peripheral + System Core) • 3.3 V Single supply: internal regulator with external power stage or

External supply • 3.3 V I/Os (ADC 5 V capable) • 144 LQFP / 257 MAPBGA 0.8 mm pitch • Tj = 150°C .

Cross Bar Switch –E2E ECC (Addr+Data)

Memory Protection Unit – 32 regions

2.5 M FLASH (I/D) (A+D ECC)

PMU

SWT

MCM

STM

INTC

CACHE

PowerPC™ e200

VLE

S-FPU

DLMEM Nexus/ Aurora

JTAG

Debug

CACHE

PowerPC™ e200

Safety Checker

VLE

S-FPU

2 x L

INF

lex

4 x D

SP

I

4 x

AD

C

3 F

lexCA

N

3 x eT

imer

FC

CU

2 x F

lexPW

M

2x CT

U

2 x TS

EN

S

I/D-cache

384 KB SRAM

(A+D ECC)

FlexRay SIPI

2 x SE

NT

Safe eDMA

Safety Lake

I/O Bridge

SRAM Ctrl Multi Ported

Flash ctrl I/O

Bridge

I/O

Sy

ste

m

Crossbar Slaves

Ethernet

TM

256k SRAM

(with ECC)

256k SRAM

(with ECC)

MPC5748C/G Block Diagram

Communications I/O System

48ch* ATD 10bit

eMIOS 96ch

4 I2C,

3 SAI

4 DSPI

6 SPIs

8 CAN

18 LIN Flex

32ch* ATD 12bit

CTU

3 Analog Comp- arators

CROSSBAR SWITCH Memory Protection Unit (MPU)

Crossbar Masters

3x Nexus Class 3+

JTAG

Debug System

Peripheral Bridge

HSM

256k SRAM

(with ECC)

Flash controller

SIUL

16xPIT+RTI

3xSWT

3xSTM

SSCM

STCU (MBIST/LBIST)

FCCU

BAF/BAR

16xSemaphore

DMA MUX

6M Flash

incl EE emulation (with ECC)

Applications: •High end Gateway and Body Modules Key Characteristics: •2x e200z4 + 1x z2 cores, FPU on z4 cores •160 MHz max for z4s and 80 MHz on z2 •HSM Security Module option supports both SHE and EVITA low/medium standard •Media Local Bus supports MOST communication •2 x USB 2.0 (1 OTG and 1 Host module) support interfacing to 3G modem and infotainment domain •2 x Ethernet 10/100 Mbps RMII, MII, +1588, AVB •CAN module optionally supports CAN FD •SDHC provides standard SDIO interface •Low Power Unit provides reduced CAN, LIN, SPI, ADC functionality in low power mode •Designed to ISO26262 process for use in ASIL B •-40 to +125C (ambient) •3.0V to 5.5V

Packages: •176 LQFP, 256 BGA, 324 BGA

VReg

RTC/API

8-40MHz Osc

FMPLL

32KHz Osc

16MHz IRC

128KHz IRC

ML

B

SD

HC

Fle

xRay

2x U

SB

2.0

2x E

ther

net

e200z2 Core

e200z4 Core

e200z4 Core

*Mixture of internal and external channels Features available depend on package and device version

1 CRC

5747C 5748C 5747G 5748G

Cores 2 2 3 3

Flash 4M 6M 4M 6M

RAM 512k 768k 768k 768k

MLB N N Y Y

USB N N Y Y

Low Power Unit

Interface

32ch

eD

MA

TM

MPC577xK 4M Block Diagram

Specifications:

CPU: 3x PPC: 2x e200z7 266 MHz Power dual issue with SPE2 and VFPU and e200z4 133MHz in permanent lockstep

SPT: FFT Accelerator, DMA

Analog: Octal SD + 4 SAR, Ultra low jitter PLL, precision DAC

Package: 356 PBGA – 0.8 mm pitch – 17 x 17 mm2 body

Temp Range (Ta): -40 to 125 C, 150 C Tj, AEC-Q100 Grade 1

Main Supply: 3.3V IO (5V SAR) and 1.2V Core (ext or PMU)

Key Features:

Safety: developed as per ISO26262 with target ASIL-D

Safety Enablement: Safety Manual and FMEDA

SPT: Radix4/2, r2c, c2c, 50 MHz 16 bit twiddle, 24 bit results

SRAM: Multi ported SRAM Ctrl and 1.5MB SRAM with ECC

Top of Class Analogue IP: PLL, DAC, OSC and ADC

SW Enablement: QMS MCAL and/or Safe Mcal Asil B (D)

NV Memory

CPU Platform

e200z4LS @ 133MHz

16kB I-cache 2 way

SFPU

16kB D-cache 2 way

Ext. Memory I/F

4MB with ECC

16 bit PDI

Volatile Emb. Memory

1.5MB RAM with ECC

Connectivity

2 x Cross Trig Unit 3 x IIC 2 x SENT I/F

2 x FlexPWM (12 ch) 4 x LinFlex Ctrl 4 x dSPI

3 x eTimers – 6 ch. each 4 x Flex CAN (1FD) SWT & STM

Safety & Support

OSC and PLL

T-Sensor

FCCU & CRC

Safe DMA

DEBUG Nexus 3+

Fabric

64 bit XBAR with E2E ECC

ADC Input

8 x – 10MHz

DAC

2Ms/s 8 bit DAC

4x 12bit SAR -1MHz

Signal processing toolbox

Scheduler

FFT

DMA

Radar Processing Platform Master Comm Bus

128 msg FlexRay

100base T Ethernet

Intra ECU connectivity

Zipwire (SIPI/LFAST)

Vehicle and ECU Network

e200z7 @266MHz

16kB I-cache 2 way

VFPU & SPE2-SIMD

16kB D-cache 2 way

e200z7 @266MHz

16kB I-cache 2 way

VFPU & SPE2-SIMD

16kB D-cache 2 way

e200z4 LS @ 133MHz

8kB I-cache 2 way

SFPU

4kB D-cache 2 way

PMU

Safe Memory

MEMU

TM

COPY

Questions and Answers

Any questions that we are unable to accommodate due to time constraints will be answered on the website www.nexus5001.org

For more information on Nexus 5001 Forum, please visit:

www.nexus5001.org For questions or comments email admin@nexus5001.org