nrf52840 · 2018-03-23 · technology) that implements a superset of 16 and 32-bit instructions to...

nRF52840

Product Specificationv1.0

4413_417 v1.0 / 2018-03-16

Feature list

Features:

• Bluetooth® 5, IEEE 802.15.4-2006, 2.4 GHz transceiver

• -95 dBm sensitivity in 1 Mbps Bluetooth® low energy (BLE) mode

• -103 dBm sensitivity in 125 kbps BLE mode (long range)

• +8 dBm TX power (down to -20 dBm in 4 dB steps)

• On-air compatible with nRF52, nRF51, nRF24L and nRF24AP Series

• Supported data rates:

• Bluetooth® 5: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps

• IEEE 802.15.4-2006: 250 kbps

• Proprietary 2.4 GHz: 2 Mbps, 1 Mbps

• Single-ended antenna output (on-chip balun)

• 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption)

• 4.8 mA peak current in TX (0 dBm)

• 4.6 mA peak current in RX

• RSSI (1 dB resolution)

• ARM® Cortex

®-M4 32-bit processor with FPU, 64 MHz

• 212 EEMBC CoreMark score running from flash memory

• 52 µA/MHz running from flash memory

• Watchpoint and trace debug modules (DWT, ETM and ITM)

• Serial wire debug (SWD)

• Rich set of security features

• ARM® TrustZone

® Cryptocell 310 security subsystem

• NIST SP800-90A and SP800-90B compliant random number generator

• AES-128: ECB,CBC,CMAC/CBC-MAC,CTR,CCM/CCM*

• Chacha20/Poly1305 AEAD supporting 128- and 256-bit key size

• SHA-1, SHA-2 up to 256 bits

• Keyed-hash message authentication code (HMAC)

• RSA up to 2048-bit key size

• SRP up to 3072-bit key size

• ECC support for most used curves, among others P-256 (secp256r1) and

Ed25519/Curve25519

• Application key management using derived key model

• Secure boot ready

• Flash access control list (ACL)

• Root-of-trust (RoT)

• Debug control and configuration

• Access port protection (CTRL-AP)

• Secure erase

• Flexible power management

• 1.7 V-5.5 V supply voltage range

• On-chip DC/DC and LDO regulators with automated low

current modes

• 1.8 V-3.3 V regulated supply for external components

• Automated peripheral power management

• Fast wake-up using 64 MHz internal oscillator

• 0.4 µA at 3 V in System OFF mode, no RAM retention

• 1.5 µA at 3 V in System ON mode, no RAM retention, wake on

RTC

• 1 MB flash and 256 kB RAM

• Advanced on-chip interfaces

• USB 2.0 full speed (12 Mbps) controller

• QSPI 32 MHz interface

• High-speed 32 MHz SPI

• Type 2 near field communication (NFC-A) tag with wake-on

field

• Touch-to-pair support

• Programmable peripheral interconnect (PPI)

• 48 general purpose I/O pins

• EasyDMA automated data transfer between memory and

peripherals

• Nordic SoftDevice ready with support for concurrent multi-

protocol

• 12-bit, 200 ksps ADC - 8 configurable channels with programmable

gain

• 64 level comparator

• 15 level low-power comparator with wake-up from System OFF

mode

• Temperature sensor

• 4x 4-channel pulse width modulator (PWM) unit with EasyDMA

• Audio peripherals: I2S, digital microphone interface (PDM)

• 5x 32-bit timer with counter mode

• Up to 4x SPI master/3x SPI slave with EasyDMA

• Up to 2x I2C compatible 2-wire master/slave

• 2x UART (CTS/RTS) with EasyDMA

• Quadrature decoder (QDEC)

• 3x real-time counter (RTC)

• Single crystal operation

• Package variants

• aQFN™

73 package, 7 x 7 mm

4413_417 v1.0 ii

Feature list

Applications:

• Advanced computer peripherals and I/O devices

• Mouse

• Keyboard

• Multi-touch trackpad

• Advanced wearables

• Health/fitness sensor and monitor devices

• Wireless payment enabled devices

• Internet of things (IoT)

• Smart home sensors and controllers

• Industrial IoT sensors and controllers

• Interactive entertainment devices

• Remote controls

• Gaming controllers

4413_417 v1.0 iii

ContentsFeature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

1 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 About this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1 Document naming and status . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Peripheral naming and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 132.3 Register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1 Fields and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.1 DUMMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Core components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.1 Floating point interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1.2 CPU and support module configuration . . . . . . . . . . . . . . . . . . . . . 184.1.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2.1 RAM - Random access memory . . . . . . . . . . . . . . . . . . . . . . . . 204.2.2 Flash - Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.4 Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 NVMC — Non-volatile memory controller . . . . . . . . . . . . . . . . . . . . . . 234.3.1 Writing to flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.3.2 Erasing a page in flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3.3 Writing to user information configuration registers (UICR) . . . . . . . . . . . . . 244.3.4 Erasing user information configuration registers (UICR) . . . . . . . . . . . . . . . 244.3.5 Erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3.6 Access port protection behavior . . . . . . . . . . . . . . . . . . . . . . . . 244.3.7 Partial erase of a page in flash . . . . . . . . . . . . . . . . . . . . . . . . . 244.3.8 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.3.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.3.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4 FICR — Factory information configuration registers . . . . . . . . . . . . . . . . . . 304.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.5 UICR — User information configuration registers . . . . . . . . . . . . . . . . . . . 414.5.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.6 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.6.1 EasyDMA array list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.7 AHB multilayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.8 Debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8.1 DAP - Debug access port . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.8.2 CTRL-AP - Control access port . . . . . . . . . . . . . . . . . . . . . . . . . 504.8.3 Debug interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.8.4 Real-time debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.8.5 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5 Power and clock management. . . . . . . . . . . . . . . . . . . . . . . . 54

4413_417 v1.0 iv

5.1 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . 545.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555.3 POWER — Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.1 Main supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605.3.2 USB supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655.3.3 System OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665.3.4 System ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675.3.5 RAM power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675.3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685.3.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.3.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.4 CLOCK — Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.4.1 HFCLK controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.4.2 LFCLK controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.4.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845.4.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6 Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936.1 Peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.1.1 Peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936.1.2 Peripherals with shared ID . . . . . . . . . . . . . . . . . . . . . . . . . . 946.1.3 Peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.1.4 Bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.1.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.1.6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946.1.7 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.2 AAR — Accelerated address resolver . . . . . . . . . . . . . . . . . . . . . . . . 966.2.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966.2.2 Resolving a resolvable address . . . . . . . . . . . . . . . . . . . . . . . . . 966.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR . 976.2.4 IRK data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.2.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.2.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3 ACL — Access control lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.4 CCM — AES CCM mode encryption . . . . . . . . . . . . . . . . . . . . . . . . 1046.4.1 Key-steam generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046.4.2 Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056.4.3 Decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056.4.4 AES CCM and RADIO concurrent operation . . . . . . . . . . . . . . . . . . . 1066.4.5 Encrypting packets on-the-fly in radio transmit mode . . . . . . . . . . . . . . . 1066.4.6 Decrypting packets on-the-fly in radio receive mode . . . . . . . . . . . . . . . 1076.4.7 CCM data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086.4.8 EasyDMA and ERROR event . . . . . . . . . . . . . . . . . . . . . . . . . 1096.4.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096.4.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.5 COMP — Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146.5.1 Differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156.5.2 Single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166.5.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186.5.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.6 CRYPTOCELL — ARM TrustZone CryptoCell 310 . . . . . . . . . . . . . . . . . . . 124

4413_417 v1.0 v

6.6.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266.6.2 Always-on (AO) power domain . . . . . . . . . . . . . . . . . . . . . . . . 1266.6.3 Lifecycle state (LCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266.6.4 Cryptographic key selection . . . . . . . . . . . . . . . . . . . . . . . . . 1266.6.5 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 1276.6.6 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276.6.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286.6.8 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.7 ECB — AES electronic codebook mode encryption . . . . . . . . . . . . . . . . . . 1326.7.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326.7.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326.7.3 ECB data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326.7.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336.7.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.8 EGU — Event generator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346.8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.8.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

6.9 GPIO — General purpose input/output . . . . . . . . . . . . . . . . . . . . . . 1416.9.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426.9.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446.9.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6.10 GPIOTE — GPIO tasks and events . . . . . . . . . . . . . . . . . . . . . . . . 1496.10.1 Pin events and tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496.10.2 Port event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506.10.3 Tasks and events pin configuration . . . . . . . . . . . . . . . . . . . . . . 1506.10.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516.10.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

6.11 I2S — Inter-IC sound interface . . . . . . . . . . . . . . . . . . . . . . . . . . 1556.11.1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566.11.2 Transmitting and receiving . . . . . . . . . . . . . . . . . . . . . . . . . 1566.11.3 Left right clock (LRCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576.11.4 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576.11.5 Master clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586.11.6 Width, alignment and format . . . . . . . . . . . . . . . . . . . . . . . . 1596.11.7 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606.11.8 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626.11.9 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646.11.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646.11.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.12 LPCOMP — Low power comparator . . . . . . . . . . . . . . . . . . . . . . . 1736.12.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746.12.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756.12.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756.12.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

6.13 MWU — Memory watch unit . . . . . . . . . . . . . . . . . . . . . . . . . . 1806.13.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6.14 NFCT — Near field communication tag . . . . . . . . . . . . . . . . . . . . . . 1966.14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976.14.2 Operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996.14.3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006.14.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2006.14.5 Frame assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016.14.6 Frame disassembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026.14.7 Frame timing controller . . . . . . . . . . . . . . . . . . . . . . . . . . 203

4413_417 v1.0 vi

6.14.8 Collision resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046.14.9 Antenna interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2056.14.10 NFCT antenna recommendations . . . . . . . . . . . . . . . . . . . . . . 2056.14.11 Battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2066.14.12 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2066.14.13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2066.14.14 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.15 PDM — Pulse density modulation interface . . . . . . . . . . . . . . . . . . . . 2206.15.1 Master clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216.15.2 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216.15.3 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226.15.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226.15.5 Hardware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236.15.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236.15.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246.15.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

6.16 PPI — Programmable peripheral interconnect . . . . . . . . . . . . . . . . . . . 2306.16.1 Pre-programmed channels . . . . . . . . . . . . . . . . . . . . . . . . . 2316.16.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

6.17 PWM — Pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . . 2366.17.1 Wave counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366.17.2 Decoder with EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 2406.17.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2476.17.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2476.17.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

6.18 QDEC — Quadrature decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 2556.18.1 Sampling and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566.18.2 LED output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2576.18.3 Debounce filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2576.18.4 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586.18.5 Output/input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586.18.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586.18.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2596.18.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

6.19 QSPI — Quad serial peripheral interface . . . . . . . . . . . . . . . . . . . . . 2676.19.1 Configuring peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . 2676.19.2 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686.19.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686.19.4 Erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686.19.5 Execute in place . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686.19.6 Sending custom instructions . . . . . . . . . . . . . . . . . . . . . . . . . 2696.19.7 Deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2706.19.8 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2706.19.9 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2706.19.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2756.19.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

6.20 RADIO — 2.4 GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2856.20.1 Packet configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2866.20.2 Address configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2876.20.3 Data whitening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2886.20.4 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2886.20.5 Radio states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896.20.6 Transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2906.20.7 Receive sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

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6.20.8 Received signal strength indicator (RSSI) . . . . . . . . . . . . . . . . . . . . 2936.20.9 Interframe spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936.20.10 Device address match . . . . . . . . . . . . . . . . . . . . . . . . . . . 2946.20.11 Bit counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2946.20.12 IEEE 802.15.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 2956.20.13 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3036.20.14 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3046.20.15 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

6.21 RNG — Random number generator . . . . . . . . . . . . . . . . . . . . . . . 3306.21.1 Bias correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3316.21.2 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3316.21.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3316.21.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

6.22 RTC — Real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 3336.22.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3336.22.2 Resolution versus overflow and the PRESCALER . . . . . . . . . . . . . . . . . 3336.22.3 COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3346.22.4 Overflow features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3356.22.5 TICK event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3356.22.6 Event control feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 3356.22.7 Compare feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3366.22.8 TASK and EVENT jitter/delay . . . . . . . . . . . . . . . . . . . . . . . . . 3386.22.9 Reading the COUNTER register . . . . . . . . . . . . . . . . . . . . . . . 3406.22.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3416.22.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

6.23 SAADC — Successive approximation analog-to-digital converter . . . . . . . . . . . . 3466.23.1 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3476.23.2 Reference voltage and gain settings . . . . . . . . . . . . . . . . . . . . . 3496.23.3 Digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3496.23.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3496.23.5 Continuous sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3516.23.6 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3516.23.7 Event monitoring using limits . . . . . . . . . . . . . . . . . . . . . . . . 3516.23.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3526.23.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3526.23.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

6.24 SPI — Serial peripheral interface master . . . . . . . . . . . . . . . . . . . . . 3676.24.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 3676.24.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3706.24.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

6.25 SPIM — Serial peripheral interface master with EasyDMA . . . . . . . . . . . . . . 3746.25.1 SPI master transaction sequence . . . . . . . . . . . . . . . . . . . . . . . 3756.25.2 D/CX functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3766.25.3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776.25.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776.25.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3786.25.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3796.25.7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

6.26 SPIS — Serial peripheral interface slave with EasyDMA . . . . . . . . . . . . . . . . 3896.26.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3906.26.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3906.26.3 SPI slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3906.26.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3926.26.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

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6.26.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 4026.27 SWI — Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

6.27.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4046.28 TEMP — Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 404

6.28.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4056.28.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

6.29 TWI — I2C compatible two-wire interface . . . . . . . . . . . . . . . . . . . . . 4106.29.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4116.29.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . 4116.29.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4126.29.4 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 4126.29.5 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 4136.29.6 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 4136.29.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4146.29.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4146.29.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

6.30 TIMER — Timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4206.30.1 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4216.30.2 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4216.30.3 Task delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4226.30.4 Task priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4226.30.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

6.31 TWIM — I2C compatible two-wire interface master with EasyDMA . . . . . . . . . . . 4266.31.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4276.31.2 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 4286.31.3 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 4286.31.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 4296.31.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4306.31.6 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . 4306.31.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.31.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 4396.31.9 Pullup resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

6.32 TWIS — I2C compatible two-wire interface slave with EasyDMA . . . . . . . . . . . . 4406.32.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4436.32.2 TWI slave responding to a read command . . . . . . . . . . . . . . . . . . . 4436.32.3 TWI slave responding to a write command . . . . . . . . . . . . . . . . . . . 4446.32.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 4456.32.5 Terminating an ongoing TWI transaction . . . . . . . . . . . . . . . . . . . . 4466.32.6 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4466.32.7 Slave mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 4466.32.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4476.32.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

6.33 UART — Universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . 4546.33.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4556.33.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4556.33.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4566.33.4 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4566.33.5 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4566.33.6 Suspending the UART . . . . . . . . . . . . . . . . . . . . . . . . . . . 4576.33.7 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4576.33.8 Using the UART without flow control . . . . . . . . . . . . . . . . . . . . . 4576.33.9 Parity configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4586.33.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4586.33.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

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6.34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA . . . . . . . . . 4646.34.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4656.34.2 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4656.34.3 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4666.34.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.34.5 Using the UARTE without flow control . . . . . . . . . . . . . . . . . . . . 4686.34.6 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . . 4686.34.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4686.34.8 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4696.34.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4696.34.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

6.35 USBD — Universal serial bus device . . . . . . . . . . . . . . . . . . . . . . . 4796.35.1 USB device states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4806.35.2 USB terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4816.35.3 USB pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4826.35.4 USBD power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . 4826.35.5 USB pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4836.35.6 USB reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4836.35.7 USB suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . 4846.35.8 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4856.35.9 Control transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4866.35.10 Bulk and interrupt transactions . . . . . . . . . . . . . . . . . . . . . . . 4896.35.11 Isochronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . 4926.35.12 USB register access limitations . . . . . . . . . . . . . . . . . . . . . . . 4946.35.13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4956.35.14 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

6.36 WDT — Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5196.36.1 Reload criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5196.36.2 Temporarily pausing the watchdog . . . . . . . . . . . . . . . . . . . . . . 5206.36.3 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5206.36.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5206.36.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

7 Hardware and layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5247.1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

7.1.1 aQFN73 ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 5247.2 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

7.2.1 aQFN73 7 x 7 mm package . . . . . . . . . . . . . . . . . . . . . . . . . 5277.3 Reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

7.3.1 Circuit configuration no. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 5297.3.2 Circuit configuration no. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 5317.3.3 Circuit configuration no. 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 5337.3.4 Circuit configuration no. 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 5357.3.5 Circuit configuration no. 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 5377.3.6 Circuit configuration no. 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 5397.3.7 PCB guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5417.3.8 PCB layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

8 Recommended operating conditions. . . . . . . . . . . . . . . . . . . . 544

9 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . 545

10 Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

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10.1 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54610.2 Box labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54610.3 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54710.4 Code ranges and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54810.5 Product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

11 Liability disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55111.1 RoHS and REACH statement . . . . . . . . . . . . . . . . . . . . . . . . . . 55111.2 Life support applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

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1 Revision historyDate Version Description

March 2018 1.0 First release

4413_417 v1.0 12

2 About this documentThis product specification is organized into chapters based on the modules and peripherals that areavailable in this IC.

The peripheral descriptions are divided into separate sections that include the following information:

• A detailed functional description of the peripheral• Register configuration for the peripheral• Electrical specification tables, containing performance data which apply for the operating conditions

described in Recommended operating conditions on page 544.

2.1 Document naming and statusNordic uses three distinct names for this document, which are reflecting the maturity and the status of thedocument and its content.

Document name Description

Objective Product Specification (OPS) Applies to document versions up to 0.7.

This product specification contains targetspecifications for product development.

Preliminary Product Specification (PPS) Applies to document versions 0.7 and up to 1.0.

This product specification contains preliminarydata. Supplementary data may be published fromNordic Semiconductor ASA later.

Product Specification (PS) Applies to document versions 1.0 and higher.

This product specification contains final productspecifications. Nordic Semiconductor ASA reservesthe right to make changes at any time withoutnotice in order to improve design and supply thebest possible product.

Table 1: Defined document names

2.2 Peripheral naming and abbreviationsEvery peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used foridentification and reference. This name is used in chapter headings and references, and it will appear inthe ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer toidentify the peripheral.

The peripheral instance name, which is different from the peripheral name, is constructed using theperipheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix isnormally only used if a peripheral can be instantiated more than once. The peripheral instance name isalso used in the CMSIS to identify the peripheral instance.

4413_417 v1.0 13

About this document

2.3 Register tablesIndividual registers are described using register tables. These tables are built up of two sections. The firstthree colored rows describe the position and size of the different fields in the register. The following rowsdescribe the fields in more detail.

2.3.1 Fields and valuesThe Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field hasenumerated values, then every value will be identified with a unique value id in the Value Id column.

A blank space means that the field is reserved and read as undefined, and it also must be written as 0to secure forward compatibility. If a register is divided into more than one field, a unique field name isspecified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields whenvalues can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/off, and so on.

Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimalvalues have no prefix.

The Value column can be populated in the following ways:

• Individual enumerated values, for example 1, 3, 9.• Range of values, e.g. [0..4], indicating all values from and including 0 and 4.• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or

alternatively the field's translation and limitations are described in the text instead.

If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all butthe first field. Subsequent fields will indicate inheritance with '..'.

A feature marked Deprecated should not be used for new designs.

2.4 Registers

Register Offset Description

DUMMY 0x514 Example of a register controlling a dummy feature

Table 2: Register overview

2.4.1 DUMMYAddress offset: 0x514

Example of a register controlling a dummy feature

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID D D D D C C C B A A

Reset 0x00050002 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

ID RW Field Value ID Value Description

A RW FIELD_A Example of a field with several enumerated values

Disabled 0 The example feature is disabled

NormalMode 1 The example feature is enabled in normal mode

ExtendedMode 2 The example feature is enabled along with extra

functionality

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About this document

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID D D D D C C C B A A

Reset 0x00050002 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0


B RW FIELD_B Example of a deprecated field Deprecated

Disabled 0 The override feature is disabled

Enabled 1 The override feature is enabled

C RW FIELD_C Example of a field with a valid range of values

ValidRange [2..7] Example of allowed values for this field

D RW FIELD_D Example of a field with no restriction on the values

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3 Block diagramThis block diagram illustrates the overall system. Arrows with white heads indicate signals that sharephysical pins with other signals.

4413_417 v1.0 16

Block diagram

nRF52840

APB0

AHB TO APBBRIDGE

RADIO

CPU

ARMCORTEX-M4

AHB-AP

RNG

TEMPWDT

NVMC

ANT

POWERnRESETRTC [0..2]

PPI

TIMER [0..4]

NVIC

UICRFICR

SW-DP

CODE

EasyDMA master

QDEC

SAADC

GPIOTE

P0.0 – P0.31P1.0 – P1.15

AIN0 – AIN7

LEDAB

UARTE [0..1]

SPIS [0..2] MOSIMISOCSN

COMP

EasyDMA

RXDTXDCTSRTS

ETM

SysTick

TPIUTP

EasyDMA

LPCOMP

EasyDMAmaster

master

NFCTNFC1NFC2

EasyDMA master

master

SWDIOSWCLK

CTRL-AP

PWM [0..3]OUT0 – OUT3

I2S

MCKLRCK

SCLSDOUT

SDIN

PDMCLKDIN

SCK

EasyDMA master

EasyDMA master

EasyDMA master

I-Cache

slave

slave

slave

slave

slave

mas

ter

CLOCK

XL2XL1XC2XC1

USBDD-D+

EasyDMA master

VBUS

SPIM [0..3]SCK

MISOEasyDMA

MOSI

master

TWIM [0..1]SCLSDA

EasyDMAmaster

QSPI IO3IO2IO1IO0

EasyDMAmasterCSNSCK

ECB

EasyDMAmaster

CCM

EasyDMAmaster

AAR

EasyDMAmaster

CryptoCell

DMAmaster

TWIS [0..1]SCLSDA

EasyDMAmaster

RAM0

slave

RAM1

slave

RAM2

slave

RAM3

slave

RAM4

slave

RAM5

slave

RAM6

slave

RAM7

slave

GPIO

slave

RAM8

slave

AHB multilayer

P0.0 – P0.31P1.0 – P1.15

P0.0 – P0.31P1.0 – P1.15

Figure 1: Block diagram

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4 Core components4.1 CPUThe ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2technology) that implements a superset of 16 and 32-bit instructions to maximize code density andperformance.

This processor implements several features that enable energy-efficient arithmetic and high-performancesignal processing, including:

• Digital signal processing (DSP) instructions• Single-cycle multiply and accumulate (MAC) instructions• Hardware divide• 8- and 16-bit single instruction multiple data (SIMD) instructions• Single-precision floating-point unit (FPU)

The ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for theARM®Cortex® processor series is implemented and available for the M4 CPU.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handlingevents at configurable priority levels via the nested vectored interrupt controller (NVIC).

Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache canbe enabled to minimize flash wait states when fetching instructions. For more information on cache,see Cache on page 25. The section Electrical specification on page 19 shows CPU performanceparameters including wait states in different modes, CPU current and efficiency, and processing power andefficiency based on the CoreMark® benchmark.

The ARM system timer (SysTick) is present on nRF52840. The SysTick's clock will only tick when the CPU isrunning or when the system is in debug interface mode.

4.1.1 Floating point interruptThe floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, whichin turn will trigger the FPU interrupt.

See Instantiation on page 22 for more information about the exceptions triggering the FPU interrupt.

To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit withinthe floating-point status and control register (FPSCR) needs to be cleared. For more information about theFPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.

4.1.2 CPU and support module configurationThe ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on thedevice.

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Core components

Option / Module Description Implemented

Core options

NVIC Nested vector interrupt controller 48 vectors

PRIORITIES Priority bits 3

WIC Wakeup interrupt controller NO

Endianness Memory system endianness Little endian

Bit-banding Bit banded memory NO

DWT Data watchpoint and trace YES

SysTick System tick timer YES

Modules

MPU Memory protection unit YES

FPU Floating-point unit YES

DAP Debug access port YES

ETM Embedded trace macrocell YES

ITM Instrumentation trace macrocell YES

TPIU Trace port interface unit YES

ETB Embedded trace buffer NO

FPB Flash patch and breakpoint unit YES

HTM AMBA™

AHB trace macrocell NO

4.1.3 Electrical specification

4.1.3.1 CPU performance

The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU isexecuting the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocksare IDLE.

Symbol Description Min. Typ. Max. Units

WFLASH CPU wait states, running CoreMark from flash, cache

disabled

2

WFLASHCACHE CPU wait states, running CoreMark from flash, cache

enabled

3

WRAM CPU wait states, running CoreMark from RAM 0

CMFLASH CoreMark, running CoreMark from flash, cache enabled 212 CoreMark

CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache

enabled

3.3 CoreMark/

MHz

CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache

enabled, DCDC 3V

59 CoreMark/

mA

4.2 MemoryThe nRF52840 contains 1 MB of flash and 256 kB of RAM that can be used for code and data storage.

The CPU and the peripherals having EasyDMA can access memory via the AHB multilayer interconnect.

The CPU is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Memorylayout on page 20.

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Core components

RAM3AHB slave

RAM2AHB slave

RAM1AHB slave

RAM0AHB slave

RAM7AHB slave

RAM6AHB slave

RAM5AHB slave

RAM4AHB slave

AHB multilayer interconnectA

HB

sl

ave

Page 0

Page 1

Page 2

Page 3..254

Page 255

0x0000 0000

0x0000 2000

0x0000 3000

0x000F F000

FlashICODE/DCODE

AH

B

slav

e

NV

MC

ICODE

DCODE

Peripheral

EasyDMA

DM

A b

usPeripheral

EasyDMA

DM

A b

us

CPU

ARM Cortex-M4

Sys

tem

bus

ICO

DE

DC

OD

E

AHB2APB

AHB

APB

0x0000 1000

I-Cac

he

0x2000 0000

0x2000 1000

0x2000 2000

0x2000 3000

0x2000 4000

0x2000 5000

0x2000 6000

0x2000 7000Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

0x2000 8000

0x2000 9000

0x2000 A000

0x2000 B000

0x2000 C000

0x2000 D000

0x2000 E000

0x2000 F000Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

Data RAMSystem

0x0080 0000

0x0080 1000

0x0080 2000

0x0080 3000

0x0080 4000

0x0080 5000

0x0080 6000

0x0080 7000

0x0080 8000

0x0080 9000

0x0080 A000

0x0080 B000

0x0080 C000

0x0080 D000

0x0080 E000

0x0080 F000

Code RAMICODE / DCODE

Section 0

Section 1

Section 2

Section 3

Section 4

Section 5

0x2001 0000 0x0081 0000

0x2001 8000 0x0081 8000

0x2002 0000 0x0082 0000

0x2002 8000 0x0082 8000

0x2003 0000 0x0083 0000

0x2003 8000 0x0083 8000

RAM8AHB slave

Figure 2: Memory layout

See AHB multilayer on page 48 and EasyDMA on page 45 for more information about the AHBmultilayer interconnect and the EasyDMA.

The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to theapplication to partition the RAM within these regions so that one does not corrupt the other.

4.2.1 RAM - Random access memoryThe RAM interface is divided into 9 RAM AHB slaves.

RAM AHB slave 0-7 is connected to 2x4 kB RAM sections each and RAM AHB slave 8 is connected to 6x32kB sections, as shown in Memory layout on page 20.

Each of the RAM sections have separate power control for System ON and System OFF mode operation,which is configured via RAM register (see the POWER — Power supply on page 60).

4.2.2 Flash - Non-volatile memoryThe flash can be read an unlimited number of times by the CPU, but it has restrictions on the number oftimes it can be written and erased and also on how it can be written.

Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatilememory controller on page 23.

The flash is divided into 256 pages of 4 kB each that can be accessed by the CPU via both the ICODE andDCODE buses as shown in Memory layout on page 20.

4.2.3 Memory mapThe complete memory map is shown in Memory map on page 21. As described in Memory on page19, Code RAM and the Data RAM are the same physical RAM.

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Core components

Device

Device

Device

RAM

RAM

Peripheral

SRAM

Code

Private peripheral bus

AHB peripherals

APB peripherals

UICRFICR

Data RAM

Code RAMFlash

0xFFFFFFFF

0x00000000

0x20000000

0x40000000

0x60000000

0x80000000

0xA0000000

0xC0000000

0xE0000000

0x00000000

0x10000000

0x40000000

0x50000000

0xE0000000

0x00800000

0x10001000

0x20000000

XIP0x120000000x19FFFFFF

System address map Address map

Figure 3: Memory map

4413_417 v1.0 21

Core components

4.2.4 Instantiation

ID Base address Peripheral Instance Description

0 0x40000000 CLOCK CLOCK Clock control

0 0x40000000 POWER POWER Power control

1 0x40001000 RADIO RADIO 2.4 GHz radio

2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter Deprecated

2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA,

unit 0

3 0x40003000 SPI SPI0 SPI master 0 Deprecated

3 0x40003000 SPIM SPIM0 SPI master 0

3 0x40003000 SPIS SPIS0 SPI slave 0

3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated

3 0x40003000 TWIM TWIM0 Two-wire interface master 0

3 0x40003000 TWIS TWIS0 Two-wire interface slave 0




4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated

4 0x40004000 TWIM TWIM1 Two-wire interface master 1

4 0x40004000 TWIS TWIS1 Two-wire interface slave 1

5 0x40005000 NFCT NFCT Near field communication tag

6 0x40006000 GPIOTE GPIOTE GPIO tasks and events

7 0x40007000 SAADC SAADC Analog to digital converter

8 0x40008000 TIMER TIMER0 Timer 0

9 0x40009000 TIMER TIMER1 Timer 1

10 0x4000A000 TIMER TIMER2 Timer 2

11 0x4000B000 RTC RTC0 Real-time counter 0

12 0x4000C000 TEMP TEMP Temperature sensor

13 0x4000D000 RNG RNG Random number generator

14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption

15 0x4000F000 AAR AAR Accelerated address resolver

15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption

16 0x40010000 WDT WDT Watchdog timer

17 0x40011000 RTC RTC1 Real-time counter 1

18 0x40012000 QDEC QDEC Quadrature decoder

19 0x40013000 COMP COMP General purpose comparator

19 0x40013000 LPCOMP LPCOMP Low power comparator

20 0x40014000 EGU EGU0 Event generator unit 0

20 0x40014000 SWI SWI0 Software interrupt 0











26 0x4001A000 TIMER TIMER3 Timer 3

27 0x4001B000 TIMER TIMER4 Timer 4

28 0x4001C000 PWM PWM0 Pulse width modulation unit 0

4413_417 v1.0 22

Core components

ID Base address Peripheral Instance Description

29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface

30 0x4001E000 ACL ACL Access control lists

30 0x4001E000 NVMC NVMC Non-volatile memory controller

31 0x4001F000 PPI PPI Programmable peripheral interconnect

32 0x40020000 MWU MWU Memory watch unit

33 0x40021000 PWM PWM1 Pulse width modulation unit 1

34 0x40022000 PWM PWM2 Pulse width modulation unit 2




36 0x40024000 RTC RTC2 Real-time counter 2

37 0x40025000 I2S I2S Inter-IC sound interface

38 0x40026000 FPU FPU FPU interrupt

39 0x40027000 USBD USBD Universal serial bus device

40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA,

unit 1

41 0x40029000 QSPI QSPI External memory interface

45 0x4002D000 PWM PWM3 Pulse width modulation unit 3

47 0x4002F000 SPIM SPIM3 SPI master 3

0 0x50000000 GPIO GPIO General purpose input and output Deprecated

0 0x50000000 GPIO P0 General purpose input and output, port 0

0 0x50000300 GPIO P1 General purpose input and output, port 1

42 0x5002A000 CRYPTOCELL CRYPTOCELL CryptoCell subsystem control interface

N/A 0x10000000 FICR FICR Factory information configuration

N/A 0x10001000 UICR UICR User information configuration

Table 3: Instantiation table

4.3 NVMC — Non-volatile memory controllerThe non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memoryand the UICR (user information configuration registers).

The CONFIG on page 26 is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing(CONFIG.WEN = Een). The user must make sure that writing and erasing are not enabled at the same time.Having both enabled at the same time may result in unpredictable behavior.

4.3.1 Writing to flashWhen write is enabled, full 32-bit words can be written to word-aligned addresses in the flash.

As illustrated in Memory on page 19, the flash is divided into multiple pages. The same 32-bit word inthe flash can only be written n WRITE number of times before a page erase must be performed.

The NVMC is only able to write 0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit backto 1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1.Note that the restriction on the number of writes (nWRITE) still applies in this case.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes codefrom the flash while the NVMC is writing to the flash.

4413_417 v1.0 23

Core components

NVM writing time can be reduced by using READYNEXT. If this status bit is set to '1', code can performthe next data write to the flash. This write will be buffered and will be taken into account as soon as theongoing write operation is completed.

4.3.2 Erasing a page in flashWhen erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page26.

After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specifiedby tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to theflash.

See Partial erase of a page in flash on page 24 for information on dividing the page erase time intoshorter chunks.

4.3.3 Writing to user information configuration registers (UICR)User information configuration registers (UICR) are written in the same way as flash. After UICR has beenwritten, the new UICR configuration will only take effect after a reset.

UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR onpage 28 or ERASEALL on page 27. The time it takes to write a word to UICR is specified by tWRITE.The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.

4.3.4 Erasing user information configuration registers (UICR)When erase is enabled, UICR can be erased using the ERASEUICR on page 28.

After erasing UICR all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. TheCPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.

4.3.5 Erase allWhen erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALLon page 27. This operation will not erase the factory information configuration registers (FICR).

The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted if the CPUexecutes code from the flash while the NVMC performs the erase operation.

4.3.6 Access port protection behaviorWhen access port protection is enabled, parts of the NVMC functionality will be blocked in order toprevent intentional or unintentional erase of UICR.

CTRL-AP ERASEALL NVMC ERASEPAGE NVMC ERASEPAGE

PARTIAL

NVMC ERASEALL NVMC ERASEUICR

APPROTECT

Disabled Allowed Allowed Allowed Allowed Allowed

Enabled Allowed Allowed Allowed Allowed Blocked

Table 4: NVMC Protection

4.3.7 Partial erase of a page in flashPartial erase is a feature in the NVMC to split a page erase time into shorter chunks, so this can be used toprevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area inthe flash and does not work with UICR.

4413_417 v1.0 24

Core components

When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIALon page 28. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page28. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N numberof times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives thecumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as oneerase cycle.

After the erase is done, all bits in the page are set to '1'. The CPU is halted if the CPU executes code fromthe flash while the NVMC performs the partial erase operation.

The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has startedbut the total erase time is less than tERASEPAGE.

4.3.8 CacheAn instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.

See the Memory map in Memory map on page 20 for the location of flash.

A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states for a cache miss, where the instruction is not available in the cache and needs to be fetched fromflash, depends on the processor frequency and is shown in CPU on page 18

Enabling the cache can increase CPU performance and reduce power consumption by reducing thenumber of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache willuse some current when enabled. If the reduction in average current due to reduced flash accesses is largerthan the cache power requirement, the average current to execute the program code will reduce.

When disabled, the cache does not use current and does not retain its content.

It is possible to enable cache profiling to analyze the performance of the cache for your program usingthe ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for everyinstruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around afterreaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration toget correct numbers.

4.3.9 Registers

Base address Peripheral Instance Description Configuration

0x4001E000 NVMC NVMC Non-volatile memory controller

Table 5: Instances


READY 0x400 Ready flag

READYNEXT 0x408 Ready flag

CONFIG 0x504 Configuration register

ERASEPAGE 0x508 Register for erasing a page in code area

ERASEPCR1 0x508 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated

ERASEALL 0x50C Register for erasing all non-volatile user memory

ERASEPCR0 0x510 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated

ERASEUICR 0x514 Register for erasing user information configuration registers

ERASEPAGEPARTIAL 0x518 Register for partial erase of a page in code area

ERASEPAGEPARTIALCFG 0x51C Register for partial erase configuration

ICACHECNF 0x540 I-code cache configuration register.

IHIT 0x548 I-code cache hit counter.

4413_417 v1.0 25

Core components


IMISS 0x54C I-code cache miss counter.


4.3.9.1 READYAddress offset: 0x400

Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


A R READY NVMC is ready or busy

Busy 0 NVMC is busy (on-going write or erase operation)

Ready 1 NVMC is ready

4.3.9.2 READYNEXTAddress offset: 0x408

Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A R READYNEXT NVMC can accept a new write operation

Busy 0 NVMC cannot accept any write operation

Ready 1 NVMC is ready

4.3.9.3 CONFIGAddress offset: 0x504

Configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW WEN Program memory access mode. It is strongly recommended

to only activate erase and write modes when they are

actively used. Enabling write or erase will invalidate the

cache and keep it invalidated.

Ren 0 Read only access

Wen 1 Write enabled

Een 2 Erase enabled

4.3.9.4 ERASEPAGEAddress offset: 0x508

Register for erasing a page in code area

4413_417 v1.0 26

Core components

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW ERASEPAGE Register for starting erase of a page in code area

The value is the address to the page to be erased.

(Addresses of first word in page). Note that the erase must

be enabled using CONFIG.WEN before the page can be

erased. Attempts to erase pages that are outside the code

area may result in undesirable behaviour, e.g. the wrong

page may be erased.

4.3.9.5 ERASEPCR1 ( Deprecated )Address offset: 0x508

Register for erasing a page in code area. Equivalent to ERASEPAGE.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW ERASEPCR1 Register for erasing a page in code area. Equivalent to

ERASEPAGE.

4.3.9.6 ERASEALLAddress offset: 0x50C

Register for erasing all non-volatile user memory

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW ERASEALL Erase all non-volatile memory including UICR registers. Note

that the erase must be enabled using CONFIG.WEN before

the non-volatile memory can be erased.

NoOperation 0 No operation

Erase 1 Start chip erase

4.3.9.7 ERASEPCR0 ( Deprecated )Address offset: 0x510

Register for erasing a page in code area. Equivalent to ERASEPAGE.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW ERASEPCR0 Register for starting erase of a page in code area. Equivalent

to ERASEPAGE.

4413_417 v1.0 27

Core components

4.3.9.8 ERASEUICRAddress offset: 0x514

Register for erasing user information configuration registers

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW ERASEUICR Register starting erase of all user information configuration

registers. Note that the erase must be enabled using

CONFIG.WEN before the UICR can be erased.

NoOperation 0 No operation

Erase 1 Start erase of UICR

4.3.9.9 ERASEPAGEPARTIALAddress offset: 0x518

Register for partial erase of a page in code area

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW ERASEPAGEPARTIAL Register for starting partial erase of a page in code area

The value is the address to the page to be partially erased

(address of the first word in page). Note that the erase must

be enabled using CONFIG.WEN before every erase page

partial and disabled using CONFIG.WEN after every erase

page partial. Attempts to erase pages that are outside the

code area may result in undesirable behaviour, e.g. the

wrong page may be erased.

4.3.9.10 ERASEPAGEPARTIALCFGAddress offset: 0x51C

Register for partial erase configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A

Reset 0x0000000A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0


A RW DURATION Duration of the partial erase in milliseconds

The user must ensure that the total erase time is long

enough for a complete erase of the flash page.

4.3.9.11 ICACHECNFAddress offset: 0x540

I-code cache configuration register.

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID B A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW CACHEEN Cache enable

Disabled 0 Disable cache. Invalidates all cache entries.

Enabled 1 Enable cache

B RW CACHEPROFEN Cache profiling enable

Disabled 0 Disable cache profiling

Enabled 1 Enable cache profiling

4.3.9.12 IHITAddress offset: 0x548

I-code cache hit counter.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW HITS Number of cache hits

4.3.9.13 IMISSAddress offset: 0x54C

I-code cache miss counter.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


A RW MISSES Number of cache misses

4.3.10 Electrical specification

4.3.10.1 Flash programming


nWRITE Number of times a 32-bit word can be written before erase 2

nENDURANCE Erase cycles per page 10000

tWRITE Time to write one 32-bit word 411 µs

tERASEPAGE Time to erase one page 851 ms

tERASEALL Time to erase all flash 1691 ms

tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total

execution time for one partial page erase is defined as

ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc.

1.051

1 Applies when HFXO is used. Timing varies according to HFINT accuracy when HFINT is used.

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4.3.10.2 Cache size


SizeICODE I-Code cache size 2048 Bytes

4.4 FICR — Factory information configuration registersFactory information configuration registers (FICR) are pre-programmed in factory and cannot be erased bythe user. These registers contain chip-specific information and configuration.

4.4.1 Registers

Base address Peripheral Instance Description Configuration

0x10000000 FICR FICR Factory information configuration

Table 7: Instances


CODEPAGESIZE 0x010 Code memory page size

CODESIZE 0x014 Code memory size

DEVICEID[0] 0x060 Device identifier

DEVICEID[1] 0x064 Device identifier

ER[0] 0x080 Encryption root, word 0



ER[3] 0x08C Encryption root, word 3

IR[0] 0x090 Identity Root, word 0



IR[3] 0x09C Identity Root, word 3

DEVICEADDRTYPE 0x0A0 Device address type

DEVICEADDR[0] 0x0A4 Device address 0

DEVICEADDR[1] 0x0A8 Device address 1

INFO.PART 0x100 Part code

INFO.VARIANT 0x104 Build code (hardware version and production configuration)

INFO.PACKAGE 0x108 Package option

INFO.RAM 0x10C RAM variant

INFO.FLASH 0x110 Flash variant

INFO.UNUSED8[0] 0x114 Reserved

INFO.UNUSED8[1] 0x118 Reserved

INFO.UNUSED8[2] 0x11C Reserved

PRODTEST[0] 0x350 Production test signature 0



TEMP.A0 0x404 Slope definition A0


TEMP.A2 0x40C Slope definition A2




TEMP.B0 0x41C Y-intercept B0

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TEMP.B1 0x420 Y-intercept B1



TEMP.B4 0x42C Y-intercept B4


TEMP.T0 0x434 Segment end T0


TEMP.T2 0x43C Segment end T2



NFC.TAGHEADER0 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,

NFCID1_2ND_LAST and NFCID1_LAST.





NFC.TAGHEADER3 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,


TRNG90B.BYTES 0xC00 Amount of bytes for the required entropy bits

TRNG90B.RCCUTOFF 0xC04 Repetition counter cutoff

TRNG90B.APCUTOFF 0xC08 Adaptive proportion cutoff

TRNG90B.STARTUP 0xC0C Amount of bytes for the startup tests

TRNG90B.ROSC1 0xC10 Sample count for ring oscillator 1



TRNG90B.ROSC4 0xC1C Sample count for ring oscillator 4


4.4.1.1 CODEPAGESIZEAddress offset: 0x010

Code memory page size

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R CODEPAGESIZE Code memory page size

4.4.1.2 CODESIZEAddress offset: 0x014

Code memory size

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R CODESIZE Code memory size in number of pages

Total code space is: CODEPAGESIZE * CODESIZE

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4.4.1.3 DEVICEID[n] (n=0..1)Address offset: 0x060 + (n × 0x4)

Device identifier

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R DEVICEID 64 bit unique device identifier

DEVICEID[0] contains the least significant bits of the device

identifier. DEVICEID[1] contains the most significant bits of

the device identifier.

4.4.1.4 ER[n] (n=0..3)Address offset: 0x080 + (n × 0x4)

Encryption root, word n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R ER Encryption root, word n

4.4.1.5 IR[n] (n=0..3)Address offset: 0x090 + (n × 0x4)

Identity Root, word n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R IR Identity Root, word n

4.4.1.6 DEVICEADDRTYPEAddress offset: 0x0A0

Device address type

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A

Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R DEVICEADDRTYPE Device address type

Public 0 Public address

Random 1 Random address

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4.4.1.7 DEVICEADDR[n] (n=0..1)Address offset: 0x0A4 + (n × 0x4)

Device address n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R DEVICEADDR 48 bit device address

DEVICEADDR[0] contains the least significant bits of

the device address. DEVICEADDR[1] contains the most

significant bits of the device address. Only bits [15:0] of

DEVICEADDR[1] are used.

4.4.1.8 INFO.PARTAddress offset: 0x100

Part code

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0x00052840 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0


A R PART Part code

N52840 0x52840 nRF52840

Unspecified 0xFFFFFFFF Unspecified

4.4.1.9 INFO.VARIANTAddress offset: 0x104

Build code (hardware version and production configuration)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R VARIANT Build code (hardware version and production

configuration). Encoded as ASCII.

AAAA 0x41414141 AAAA

BAAA 0x42414141 BAAA

CAAA 0x43414141 CAAA

AABA 0x41414241 AABA

AABB 0x41414242 AABB

AACA 0x41414341 AACA

AAAB 0x41414142 AAAB


4.4.1.10 INFO.PACKAGEAddress offset: 0x108

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Package option

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R PACKAGE Package option

QI 0x2004 QIxx - 73-pin aQFN


4.4.1.11 INFO.RAMAddress offset: 0x10C

RAM variant

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R RAM RAM variant

K16 0x10 16 kByte RAM






4.4.1.12 INFO.FLASHAddress offset: 0x110

Flash variant

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R FLASH Flash variant

K128 0x80 128 kByte FLASH



K1024 0x400 1 MByte FLASH

K2048 0x800 2 MByte FLASH


4.4.1.13 PRODTEST[n] (n=0..2)Address offset: 0x350 + (n × 0x4)

Production test signature n

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1


A R PRODTEST Production test signature n

Done 0xBB42319F Production tests done

NotDone 0xFFFFFFFF Production tests not done

4.4.1.14 TEMP.A0Address offset: 0x404

Slope definition A0

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A A A A A

Reset 0xFFFFF320 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0


A R A A (slope definition) register.


Slope definition A1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFF343 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 0 1 1



4.4.1.16 TEMP.A2Address offset: 0x40C

Slope definition A2

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFF35D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 0 1




Slope definition A3

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFF400 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0




Slope definition A4

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFF452 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0




Slope definition A5

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFFF37B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1



4.4.1.20 TEMP.B0Address offset: 0x41C

Y-intercept B0

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A A A A A A A

Reset 0xFFFF3FCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0


A R B B (y-intercept)

4.4.1.21 TEMP.B1Address offset: 0x420

Y-intercept B1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFF3F98 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0



4413_417 v1.0 36

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Y-intercept B2

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFF3F98 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0




Y-intercept B3

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFF0012 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0



4.4.1.24 TEMP.B4Address offset: 0x42C

Y-intercept B4

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFF004D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1




Y-intercept B5

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Reset 0xFFFF3E10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0



4.4.1.26 TEMP.T0Address offset: 0x434

Segment end T0

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A

Reset 0xFFFFFFE2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0


A R T T (segment end) register

4.4.1.27 TEMP.T1Address offset: 0x438

Segment end T1

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ID A A A A A A A A

Reset 0xFFFFFF00 1

nrf52840 · 2018-03-23 · technology) that implements a superset of 16 and 32-bit instructions to...

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