nss-mic 2009 summary rafael ballabriga ph-ese-me

NSS-MIC 2009 SummaryNSS-MIC 2009 Summary

Rafael Ballabriga

PH-ESE-ME

-2- NSS-MIC conference, Orlando (October 2009) R. Ballabriga

NSS ConferenceNSS Conference

• Photodetectors and Scintillation detectors• Semiconductor Detectors• Analog and digital circuits• Nuclear measurements and monitoring techniques• New detector concepts and instrumentation• Instrumentation for homeland security• Data acquisition and analysis systems• Radiation damage effects• Computing and software for experiments• Trigger and front-end systems• Gaseous detectors• High energy physics instrumentation• Gamma ray imaging• Neutron Imaging• Accelerators and beam line instrumentation


MIC ConferenceMIC Conference

• X-Ray imaging

• PET/SPECT instrumentation

• Simulation and modelling of medical imaging systems

• Animal imaging and instrumentation techniques

• Image processing and evaluation

• Image reconstruction

• Quantitative imaging techniques


This talk

• ASICS– PX90DC (P. Grybos, AGH UST Cracow)– Medipix3 (R. Ballabriga, CERN)– ASIC for SDD-based X-ray Spectrometers (G. De Geronimo, BNL)– New dynamic TOT method (K. Shimazoe, Tokio University)

• 3D Interconnects– 3D IC @ Fermilab (G. Deptuch, Fermilab)– New techniques in SOI pixel detectors (Y. Arai, KEK)– MAPS based on 3D integration (W. Dulinski, IPHC Strasbourg)

• SiPM – 2 posters/~250 in NSS-2006– 15 posters/~250 in NSS-2009 (and a few talks)– Introduction– SPIROC chip (W. Shen, Heidelberg)– BASIC chip (C. Marzocca, Politecnico di Bari and INFN)– Readout of SiPM for TOF PET (P. Jarron, CERN)

• Summary


ASICsASICs


PX90DC (P. Grybos)

Prototype readout chip for hybrid pixel detector

Functionaliy: Single Photon Counting, Energy window, continuous readout

90nm CMOS technology (TSMC)

9 metal layers

40x32 pixels

100umx100um pixel


PX90DC (P. Grybos)


CharacteriCharacterization of the zation of the Medipix3 Pixel Readout Medipix3 Pixel Readout

ChipChip

R. Ballabriga, M.Campbell, E. H. M. Heijne, J. Jakubek, X. Llopart, R. Plackett, S. Pospisil, L. Tlustos, Z. Vykydal, W.Wong

CERN, PH department


Medipix3 IntroductionMedipix3 Introduction

• Medipix3 is a Hybrid Pixel Detector readout chip working in Single Photon Counting Mode

• Designed in 130nm CMOS technology• Highly configurable pixel• Flexible readout scheme (ROI, Configurable output

port width)• It implements a novel architecture for improving the

system’s spectrometric performance

Eliminating the distortion from charge diffusion in the spectrum


Charge summing and allocation concept

55µm

The winner takes all

• Charge is summed in every 4 pixel cluster on an event-by-event basis

• The incoming quantum is assigned as a single hit


gm

gm

VFBK

PolarityBitGainMode

SummingMode

Test Input

Input Pad

TestBit

B_TH2<0:4>

TH1

Cluster commoncontrollogic

+Arbitration

circuitry

CounterA

Next Pixel_A

ModeContRWDisablePixelCom

AdjustTHHSpectroscopicMode

ANALOG DIGITAL

CF

CTEST

To adjacent pixels (A, B, D)

From adjacent pixels (F, H, I)

x1

From adjacent pixels (A, B, D)

To adjacent pixels (F, H, I)

A B CD E FG H I

BLOCK DIAGRAM OF PIXEL E

DISC

DISC

x2

x6

TH2

x6

x3

x3

x1

x1

B_TH1<0:4>

Confx1

x6

x6

x1

ShutterAPrevious Pixel_A

x1

Clk_read

CounterB

Next Pixel_B

x1

x1

ShutterBPrevious Pixel_B

x1

x1

CounterSel

x1

x1

Medipix3 Pixel SchematicMedipix3 Pixel Schematic


• Design in 130 nm CMOS technology, 8 metal layers• ~1600 transistors per pixel

1. Preamplifier

2. Shaper

3. Two discriminators with 5-bit

threshold adjustment

4. Pixel memory (13-bits)

5. Arbitration logic for charge

allocation

6. Control logic

7. Configurable counter

Pixel LayoutPixel Layout

21

45

6

3

7

55 µ

m

55 µm


Medipix3 chipMedipix3 chip

• Pixel matrix of 256 x 256 pixels

• Bottom periphery contains:– LVDS drivers and receivers– Band-Gap and 25 DACs (10 9-bit and 15

8-bit)– 32 e-fuse bits– EoC and 2 Test pulse generators per pixel

column– Temperature sensor– Full IO logic and command decoder– Power/Ground pads– TSV landing pads– Pads extenders

• Top periphery contains:– Power/Ground pads– TSV landing pads– Pads extenders

• > 115 Million transistors

• Typical power consumption:– 600 mW in Single pixel mode– 900 mW in Charge summing mode

17.3

mm

14.1 mm


Medipix3 Modes of OperationMedipix3 Modes of Operation

System Configuration Pixel Operating Modes # Thresholds

Fine Pitch Mode → 55 µm x 55 µm Single Pixel Mode

2Charge Summing Mode

Spectroscopic Mode → 110 µm x 110 µmSingle Cluster Mode

8Charge Summing Mode

Front-end Gain Modes Linearity # Thresholds

High Gain Mode ~10 ke-

2Low Gain Mode ~20 ke-

Pixel Counter Modes Dynamic range # Counters

1-bit 1 2

4-bit 15 2

12-bit 4095 2

24-bit 16777215 1

Pixel Readout Modes # Active Counters Dead Time

Sequential Read-Write 2 Yes

Continuous Read-Write 1 No


Electrical Measurements


Threshold scan with a 109Cd source (preliminary)

Threshold scan with a 109Cd source (Shutter time 2.5s) 2 peaks expected (~22kev and ~25kev)

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20000

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Threshold (DAC steps)

To

tal C

hip

Co

un

ts

Ideal


Threshold scan with a 109Cd source (Shutter time 2.5s)

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To

tal

Ch

ip C

ou

nts

Ideal

SPM



Threshold scan with a 109Cd source (Shutter time 2.5s)

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14000

16000

18000

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To

tal

Ch

ip C

ou

nts

Ideal

SPMCSM



Measured X-ray tube spectrum (preliminary)

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0 50 100 150 200 250 300 350


de

riv

(Nu

m o

f C

hip

Co

un

ts)

CSM_Ni_HV50

Spectrum of a W X-ray tube at 50kV and I=10mA.

~2mm Al prefiltering. Ni foil filtering. (8.3keV K-edge)

0.5s exposure time


Summary of electrical Summary of electrical measurementsmeasurements

Single Pixel Mode Charge Summing Mode

CSA Gain 11.4 mV/ke-

CSA-Shaper GainHigh Gain 34 nA/ke-

Low Gain 20 nA/ke-

Non-LinearityHigh Gain <5% up to 10 ke-

Low Gain <5% up to 20 ke-

Peaking time HG / LG ~110 ns

Return to baselineHigh Gain <1.5 µs for 12 ke-

Low Gain <2.5 µs for 25 ke-

Electronic noise High Gain ~60 e-

rms ~130 e-rms

Low Gain ~85 e-rms ~180 e-

rms

Unadjusted Threshold spreadHigh Gain ~1000 e-

rms ~1800 e-rms

Low Gain ~1900 e-rms ~3200 e-

rms

Expected Minimum thresholdHigh Gain ~450 e- ~900 e-

High Gain ~650 e- ~1300 e-

Pixel power consumption HG / LG 8 µW 15 µW

The chip can be operated up to 460Mrad and beyond


Silicon Drift Detector


Asic for SDD-based X-ray Spectrometers (G. De Geronimo)

Gain 2.6 and 5.2V/fC (0.83V/ke-)

5th order shaper

16 channels (1700 x 200 µm2/ch)

2mW/channel

Analog and leakage current monitors

Temp sensor


A New Dynamic Time A New Dynamic Time over Threshold Methodover Threshold Method

K. Shimazoe1, H. Takahashi1, T. Fujiwara2, T. Furumiya3, J. Ohi3, Y. Kumazawa3

1Bioengineering, The University of Tokyo, Tokyo,Bunkyo-ku, Japan2Nuclear Engineering and Management, The University of Tokyo, Tokyo,Bunkyo-ku, Japan3Shimadzu Corporation, Kyoto, Japan


A New Dynamic Time Over Threshold Method (K. Shimazoe)

• Time Over Threshold (TOT) system has advantage over pulse height measurements on its high integrity and low power dissipation because of its binary readout and circuit simplicity. However the relation between TOT and input charge is strongly nonlinear and dynamic range is limited. We propose a new dynamic TOT system which converts the pulse height to pulse width with a dynamically changing threshold. This kind of TOT system can enable wider dynamic range and improves linearity since the threshold follows the input signal and even shorten the width of TOT pulse. We show the concept of dynamic TOT system and results with discrete circuits. It can improve the dynamic range and theoretically it is possible to desired relation between TOT and input charge by using dedicated threshold function. We also designed and fabricated 48 channel dynamic TOT ASIC with 0.25um TSMC CMOS technology.


0

1

2

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6

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Time (s)

Vo

ltag

e (V

)

Wave1

Wave2

Wave3

Dynamic Threshold

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0.2

0.4

0.6

0.8

1

1.2

1.4

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Time (s)

Vo

ltag

e (V

)

Comp1_ftot

Comp2_ftot

Comp3_ftot

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 5 10 15 20 25 30 35 40 45 50

Time (s)

Vo

ltag

e (V

)

Comp1_dtot

Comp2_dtot

Comp3_dtot


CdetIdet

-Av

CF

Shaper

CI

R2

DISC

R1

V

Monostable multivibrator

A New Dynamic Time Over Threshold Method (K. Shimazoe)


3D interconnects3D interconnects


Vertically Integrated Circuits at Fermilab (G. Deptuch)


• Benefits– Density– Optimized processing (specialized layers e.g. analog/digital)– Speed (reducing interconnects distance)

• Challenges– Bonding (need high yields to be competitive)– Packaging (thin wafers)

• Main customers– Stacked microprocessors and SRAM devices

3D integrated circuits


3D integrated circuits (vendors)

Tezzaron MIT Lincoln Labs

Ziptronix

W2W, C2W W2W W2W, C2W

Bonding Cu-Cu Conventional oxide bonding

DBITM tecnology. Oxide bond

Via process Via First Via Last

Via 4um pitch, 1.2um diam, 6um deep

1.2um diam, 6um pitch

Process Chartered 130nm CMOS

0.18um SOI


VIP1/VIP2 chips. (Vertically integrated pixel)

3 tiers: Data sparsification, Time stamp, Analog

Time stamping pixel readout chip for ILC




VIPIC CHIP (Vertically integrated photon imaging chip) (Light Sources)How it works:X-ray Photon Correlation Spectroscopy (XPCS) is a technique that is used at X-ray light sources to generate speckle patterns for the study of the dynamics in various equilibrium and non-equilibrium processesThe chip is divided in 16 group of 256 pixels read out in parallel but through separate LVDS serial ports Data sparsification is performed in each group

Sensors fabricated at BNL; DBI Sensors fabricated at BNL; DBI

bonding done at Ziptronix (all inbonding done at Ziptronix (all in

process)process)


New techniques in SOI pixel detectors (Y. Arai)

Slide: Y. Arai (Oct. 15, 2009@CLIC09)

0.2um Silicon on insulator CMOS technology.


Slide: Y. Arai (Oct. 15, 2009@CLIC09)

New techniques in SOI pixel detectors (Y. Arai)


Ultra Thin, Fully depleted MAPS based on 3D integration of

Heterogeneous CMOS layers (Wojciech Dulinski, Strasbourg)


Ultra Thin, Fully depleted MAPS based on 3D integration of Heterogeneous CMOS layers (Wojciech Dulinski)

• Aim: Fast, High precision radiation tolerant and ultrathin CMOS sensors

• Solution: MAPS on fully depleted epitaxial substrate with first stage buffer amplifier on the same wafer and 3D coupling to the readout electronics

• Requirements:– Fast readout frame ~10us

– Pixel pitch ~20um

– Ultrathin ~50-100um

– 5uW/pixel, ENC ~12 e- rms, Gain ~150uV/e-


Slide : W. Dulinski EUDET-JRA1 Meeting, Strasbourg, March 2009

NSS: XFAB 0.35um

Ultra Thin, Fully depleted MAPS based on 3D integration of Heterogeneous CMOS layers (Wojciech Dulinski)


SiPMSiPM


A SiPM is a matrix of Single Photon Avalanche Diodes (SPADs) with a common output. A SPAD is build as a PIPN junction diode in series with a quench resistance. It is biased over the breakdown voltage.

i(t)

t

SiPM principle

François Powolny

The output of the SiPM is the sum of all the SPADs


François Powolny

SiPM


SPIROC ASIC (Wei Shen)



1MIP~16 pixels fired

Threshold ½ MIP

Jitter<500ps


BASIC chip (C. Marzocca)


BASIC chip (C. Marzocca)

Chip in 0.35m

3.3V, 6.6mW/channel

(190mx590m)

SiPM bias fine tunning

Low impedance, High dinamic range, flexibility in processing the current

Rin=17Ohm

BW=250MHz

Fast Path: fast trigger signal

Slow Path: energy


Readout of SiPM for TOF PET


SummarySummary


Summary

• Some ASICs that were presented at NSS have been presented in this presentation.

• An international collaboration in the field of 3D IC for HEP was created. 3D IC brings benefits and challenges and seems a direction industry is taking.

• SiPMs are emerging as candidates to replace Photomultiplier tubes, specially in medical imaging due to insensitivity to magnetic fields and operating « low voltage ». They were chosen in HEP for the Hadron Calorimeter for the ILC.


Other designs of interest (for completeness)

• A Pixel Front-End ASIC in 0.13 μm CMOS for the NA62 Experiment with on Pixel 100ps Time-to-Digital Conversion

• FE-I4: the New ATLAS Pixel Chip for Upgraded LHC Luminosities

• PARISROC, a Photomultiplier Array Integrated Read Out Chip

• FREDA: a Programmable Mixed Signal ASIC for Gas Micro-Strip Detectors Having a Wide Range of Input Capacitance

• Design and Performance of the ABCN-25 Readout Chip for the ATLAS Inner Detector Upgrade

• Low Noise 64-Channel ASIC for Si, GaAs and CdTe Strip Detectors


Additional SlidesAdditional Slides


Medipix3 Dicing optionsMedipix3 Dicing options


X [µm] Y [µm]ActiveArea

Medipix2 and Timepix 14111 16120 87.1%

Medipix3 top and bottom WB

14100 17300 81.2%

Medipix3 bottom WB 14100 15900 88.4%

Medipix3 top and bottom TVS

14100 15300 91.9%

Medipix3 bottom TVS 14100 14900 94.3%

17.3

mm

14.1 mm

Multiple dicing optionsMultiple dicing options

15.9

mm

15.3

mm

14.9

mm


Equalization procedureEqualization procedure


Matrix equalization

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6000

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8000

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Nu

mb

er o

f P

ixel

s

0

50

100

150

200

250

Nu

mb

er o

f P

ixel

s

Equalized

Not Equalized

r.m.s=38 DAC steps

r.m.s=2.8 DAC steps

1 DAC step ~ 45e- (to be measured with sources)


Chip power Chip power consumptionconsumption


Chip Power Consumption


SPIROC


Electrical model for the SiPM


VIPIC CHIP (Vertically integrated photon imaging chip)How it works:X-ray Photon Correlation Spectroscopy (XPCS) is a technique that is used at X-ray light sources to generate speckle patterns for the study of the dynamics in various equilibrium and non-equilibrium processesThe chip is divided in 16 group of 256 pixels read out in parallel but through separate LVDS serial ports Data sparsification is performed in each group



Preamplifier output in the MPIX3 chip

-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

-2.00E-07 8.00E-07 1.80E-06 2.80E-06 3.80E-06 4.80E-06

Time [s]

Vo

ltag

e [V

]

Pream_10DPream_20DPream_40DPream_60DPream_80DPream_100DPream_120DPream_140D

y = 0.0092x + 0.0097

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 5 10 15 20 25 30 35

Input Charge [ke-]

Pre

amp

lifi

er O

utp

ut

Am

pli

tud

e [V

]


Stud Bonding


• The gold stud bump flip chip assembly process creates conductive gold bumps on the die bond pads, and connects the die to the circuit board or substrate with adhesive or ultrasonic assembly. Stud bumping requires no under-bump metallization (UBM), and thus does not require wafer processing; individual die can be stud bumped as easily as they can be wire bonded.

Stud bonding (http://www.flipchips.com/tutorial03.html)


• ADVANTAGES AND LIMITATIONS• Gold stud bump flip chip offers several advantages. The bumping

equipment, a wire bonder or dedicated stud bumper, is widely available and well characterized. Since stud bumps are formed by wire bonders, they can be placed anywhere a wire bond might be placed. They can easily achieve pitches of less than 100 microns and be placed on pads of less than 75 microns.

• Since stud bumping can be done on a wire bonder, it does not require wafers or under-bump metallization (UBM). Single, off-the-shelf die can be bumped and flipped without pre-processing. This makes stud bump flip chip fast, efficient, and flexible for product development, prototyping and low to medium volume production, while easy to scale up to high volume wafer-based production with automated equipment.

• Because stud bumping is a serial process, the bumping time required increases with the number of bumps. However, high speed equipment now can place as many as 12 bumps per second. Stud bump assemblies demand more precise die placement equipment and are less tolerant of placement errors than self-aligning solder assemblies.

• Each of the stud bump assembly processes has advantages and limitations that suit it for specific applications. Stud bump assembly has been successful in a wide range of applications. Selecting the most appropriate assembly process depends on the application, the die size and number of bumps, the substrate, equipment availability, cost, and other considerations. Choosing the proper process is the best assurance of success.

Stud bonding (http://www.flipchips.com/tutorial03.html)


Pile-up rejector block (de Geronimo)

nss-mic 2009 summary rafael ballabriga ph-ese-me

Documents

nssmic conference

pixel memory

pixel cluster

medipix3 pixel readout

soi pixel detectors

grybosprototype readout

single photon

heidelbergbasic chip