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ENT-AN1180Application Note

VSC8584 Design and Layout GuideOctober 2016

VSC8584 Design and Layout Guide

VPPD-03550 ENT-AN1180 Application Note Revision 2.0

Contents

1 Revision History ............................................................................................................................. 11.1 Revision 2.0 ........................................................................................................................................ 11.2 Revision 1.0 ........................................................................................................................................ 1

2 Overview ........................................................................................................................................ 2

3 Power and Ground Considerations ................................................................................................ 33.1 Ground Isolation ................................................................................................................................. 33.2 Bob Smith Termination ....................................................................................................................... 33.3 Power Supply Planes .......................................................................................................................... 43.4 Analog Power Plane Filtering .............................................................................................................. 43.5 Local Decoupling ................................................................................................................................. 5

4 Thermal Considerations ................................................................................................................. 6

5 Copper Interface ............................................................................................................................ 75.1 Layout Considerations ........................................................................................................................ 75.2 RJ-45 Connectors ................................................................................................................................ 7

6 SerDes Interface ............................................................................................................................. 96.1 Design Rules ....................................................................................................................................... 96.2 AC Coupling Capacitors ....................................................................................................................... 96.3 SerDes Media ..................................................................................................................................... 9

7 Design Considerations ................................................................................................................. 107.1 REF_FILT/REF_REXT Pins .................................................................................................................. 107.2 Clock Inputs ...................................................................................................................................... 10

7.2.1 Device REFCLK ....................................................................................................................................... 10

7.2.2 Clock Oscillator Power Supply Filtering ................................................................................................. 11

7.2.3 QSGMII Operation and Clock Input Requirements ............................................................................... 11

7.2.4 1588 Reference Clock ............................................................................................................................ 11

7.3 LEDs .................................................................................................................................................. 12

8 Schematic and Layout Review Checklist ...................................................................................... 138.1 Reference Clock ................................................................................................................................ 138.2 1588 Signals ...................................................................................................................................... 138.3 Twisted Pair ...................................................................................................................................... 148.4 Fibre Media ...................................................................................................................................... 148.5 MAC Interface ................................................................................................................................... 158.6 SMI Interface .................................................................................................................................... 158.7 SPI Slave ............................................................................................................................................ 158.8 JTAG Interface .................................................................................................................................. 16


VPPD-03550 ENT-AN1180 Application Note Revision 2.0

8.9 Miscellaneous Pins ........................................................................................................................... 168.10 Power Pins ...................................................................................................................................... 16


VPPD-03550 ENT-AN1180 Application Note Revision 2.0 1

1 Revision HistoryThe revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

1.1 Revision 2.0In revision 2.0 of this document, the Schematic and Layout Review sections were added. For more information, see .Schematic and Layout Review Checklist

1.2 Revision 1.0Revision 1.0 was the first release of this document.



2 OverviewThis document provides guidelines for the design and layout of printed circuit boards utilizing the VSC8584 quad-port PHY or devices within the VSC8584 family. It is geared toward achieving first pass design success.The following documents are recommended references for use during the board design process.

VSC8584 DatasheetENT-AN0098 Magnetics GuideENT-AN0065 SimpliPHY Dual Media Copper/Fibre/SFP GuideIEEE802.3, CSMA/CD Access Method and Physical Layer SpecificationHigh Speed Digital Design, Author: Howard Johnson, Ph.D., ISBN 0-13-395724-1



3 Power and Ground Considerations

3.1 Ground IsolationTo isolate the board from ESD events and to prevent a common-mode noise ground path, a separate chassis ground region should be allocated. This separate chassis ground, as seen in the following illustration, should be electrically connected to the external chassis and to the shield ground of the RJ-45 connectors.

Figure 1 • Ground Plane Layout

3.2 Bob Smith TerminationIn addition, the Bob Smith termination impedance should be connected between the chassis ground and the cable-side center taps of the transformer module.



Figure 2 • Bob Smith Termination

3.3 Power Supply PlanesThe VSC8584 requires a minimum of two power rails, 2.5 V and 1.0 V. The filtered analog 1.0 V and 2.5 V supplies should not be shorted to any other digital supply at the package or PCB level. The device datasheet provides other power supply options.

The most important PCB design and layout considerations are as follows:

Ensure the return plane is adjacent to the power plane (without a signal layer in between).Ensure a single plane is used for voltage reference with splits for individual voltage rails within that plane. Attempt to maximize the area of each power rail split on the power plane based oncorresponding via coordinates for each rail in order to maximize coupling between each voltage rail and the return plane.Minimize resistive drop while efficiently conducting away heat from the device using 1 ounce copper cladding.

Four layer PCBs with only one designated power plane must adhere to proper design techniques to prevent random system events such as CRC errors. Each of these supplies require the lowest resistive drop possible to the power pins of the device with properly placed local decoupling. For more information, see .Local Decoupling

Given their low-loss, ferrite beads should be used whenever possible over a series inductor filter, particularly for high-density or high-power devices.

3.4 Analog Power Plane FilteringIn addition, the Bob Smith termination impedance should be connected between the chassis ground and the cable-side center taps of the transformer module.



Figure 3 • Filtered Supply Schematic

The beads chosen should have the following characteristics.

Current rating of at least 150% of the maximum current of the associated power supplyMinimum DC resistance (DCR) of less than 100 MΩ is recommendedImpedance of 80 Ω to 100 Ω at 100 MHz

Panasonic EXCELSA39 (or similar), Steward HI1206N101R-00 (or similar), and Murata BLM31PG121SN (or other BLMxxPG parts) beads are recommended.

3.5 Local DecouplingBulk decoupling capacitors should be tantalum, and can be placed at any convenient position on the board. Local decoupling capacitors should be X5R or X7R ceramic, and placed as close to the VSC8584's power pins as possible for each and every power pin. Assuming that the VSC8584 device is on the top side of a PCB board, the best location for local decoupling capacitors is on the bottom or underside of the PCB board, directly under the device.



4 Thermal ConsiderationsFor proper cooling, maximize the number of via connections to the ground plane for efficient thermal dissipation. For board stackups greater than four layers, additional ground planes will enhance thermal dissipation and signal integrity performance.

When connecting these thermal vias to ground planes, it is advisable to avoid thermal-relief connection traces shown on the left-hand side of the following illustration, as these are designed to prevent the flow of heat through the PCB. Instead, the thermal vias should have a solid connection to the traces and planes on each layer as shown on the right-hand side of the following illustration.

Figure 4 • Thermal Vias

PCB thermal vias should connect to the solid ground planes within the board to dissipate heat below the package. A minimum of 1 ounce cladding is recommended.The following illustration shows a cross section of the thermal via.

Figure 5 • Thermal Ground Plane Connection



5 Copper InterfaceThe following illustration shows a copper PHY media interface.

Figure 6 • Copper/CAT-5 Interface

5.1 Layout ConsiderationsThe TXVPx_n and TXVNx_n pins interface to the external CAT5 cable, and are organized in fourdifferential pairs (x = A, B, C, D) for each PHY port. When routing these pairs on a PCB, either:

Route each trace single-ended with a characteristic impedance of 50 Ω referenced to ground.orRoute each positive and negative trace on each port as differential pairs with 100 Ω characteristic differential impedance.

5.2 RJ-45 ConnectorsSystem designers have several options for the choice of RJ-45 connectors.

Two tab orientations: tab-up and tab-downTwo orientations for multi-port connectors: stacked and single-rowSingle and bi-colored LEDs can be integrated into the connectors.Magnetics can be integrated into the connectors.

Most manufacturers can mix or match any combination of features. For example, LEDs may be added toany connector or single-row, multi-port configurations may be tab-up or tab-down. The exception to this isthe stacked connector, which contains both tab-up and tab-down orientations.



Figure 7 • RJ-45 Example Configurations



6 SerDes InterfaceThe following illustration shows a typical MAC-to-PHY serial interface.

Figure 8 • Typical MAC-to-PHY Serial Interface

6.1 Design RulesBest performance will result when SerDes traces are placed using the following design rules.

Traces should be routed as 50 Ω (100 Ω differential) controlled impedance transmission lines (microstrip or stripline).Traces should be of equal length on each differential pair and port to minimize skew.Traces should be run adjacent to a single ground plane to match impedance and minimize noise.Spacing between adjacent tracks equal to five times the ground-plane gap is recommended to reduce crosstalk between SerDes pairs. A minimum spacing of three times the ground-plane gap is required.Traces should avoid vias and layer changes. If layer changes cannot be avoided, mode-suppression vias should be included nearby to attenuate any radiating spurious fields.Guard vias should be placed no greater than one-quarter wavelength apart around the differential pair tracks (625 MHz fundamental for SGMII and 2.5 GHz fundamental for QSGMII).For applications not requiring a specific port's SGMII interface pins, these pins should be left floating (no-connect).

6.2 AC Coupling CapacitorsIn general, SerDes interfaces require series AC coupling capacitors to prevent common mode voltages from interfering with transmit and receive operation. If the common mode input and output specifications for the MAC and VSC8584 are compatible, then the AC capacitors can be removed. For more information, see the VSC8584 datasheet.

6.3 SerDes MediaThe VSC8584 has an additional SerDes interface to support SerDes media (such as 1000BASE-X fibre, 100BASE-FX fibre, or 10/100/1000BASE-T copper SFPs). Connection of the SFP's loss-of-signal output to a corresponding VSC8584 SIGDET input is recommended to increase link robustness, particularly for 100BASE-FX fibre operation.



7 Design ConsiderationsIf a board design is based on a Microsemi reference design, and use of Microsemi software is planned, keep a log of changes made to the Microsemi design (such as port number and PHY addresses) and retain the reference board's use of GPIO (parallel as well as serial) whenever possible.To reduce emissions, consider the following.

Use distributed reference clock signals as low-voltage swing (for example, 400 mVpp) instead of full swing (3.3 V)Placing AC-coupling capacitors on (Q)SGMII signals between switch and PHY devices or PHY devices and SFP modules may not be required because SFPs have built-in capacitors, and some Microsemi switch and PHY combinations are DC-compatible (they can be connected directly).Small capacitors on 1000BASE-T signals sometimes help with emissions, but may impact IEEE template compliance.

7.1 REF_FILT/REF_REXT PinsFor proper operation, the VSC8584 must generate an on-chip band gap reference voltage at the REF_FILT pin. For this, the following components are required for each VSC8584 in the system:

2.0KΩ resistor, 1% tolerance, minimum 1/16 watt1 μF capacitor, 10% tolerance, NPO, X7R or X5R ceramic materials are all acceptable

For best performance, special consideration of the ground connection of the voltage reference circuit is necessary to prevent bus drops that would cause reference voltage inaccuracy. The ground connections of the resistor and the capacitor should each be connected to a shared PCB signal trace, rather than being connected individually to a common ground plane, as shown in the figure below. This PCB signal trace should then be connected to a ground plane at a single point. In addition, the reference capacitor and resistor should be placed as close as possible to the VSC8584.

Figure 9 • Voltage Reference Schematic

7.2 Clock Inputs

7.2.1 Device REFCLKThe device reference clock supports 25 MHz or 125 MHz frequencies in either a single-ended CMOS logic level drive clock signal or differential AC-coupled LVDS drive clock signal. However, if the MAC interface will be used in QSGMII operating mode, see , QSGMII Operation and Clock Input Requirementsfor specific clock input requirements. If using a single-ended clock signal, refer to the datasheet for an appropriate bias network along with input amplitude requirements.The REFCLK_SEL2 pin configures the reference clock frequency expected on the REFCLK input pin.



The REFCLK_SEL2 pin configures the reference clock frequency expected on the REFCLK input pin. REFCLK_SEL2 has an on-chip pull-up resistor setting the device default for 125 MHz.

7.2.2 Clock Oscillator Power Supply FilteringIf using a 25 MHz or a 125 MHz 4-pin oscillator with a VCC pin, an RC filter should be implemented to avoid power supply switching noise coupling into the PHY. The filter should be set to filter out the frequency of the supply's switching regulation frequency. The OUT signal, shown in the following illustration, should be tied to REFCLK.

Figure 10 • Clock Power Supply Filtering

For a supply with a switching frequency of 350 kHz, use an R value of 2.2 Ω and a C value of 11 μF.

7.2.3 QSGMII Operation and Clock Input RequirementsBecause of the high-speed signaling present on the 5 Gbps line-rate QSGMII interface, particular care must be taken regarding the REFCLK_P/N inputs that ultimately determine symbol timing on the QSGMII. Ensure the following conditions are met to provide as accurate a clock input as possible for QSGMII-based designs.

Input 125 MHz reference clock signal with differential routing is used1 V differential peak-peak amplitude is recommendedThe provided reference clock source has no greater than 1.2 ps of RMS jitter

In order to simplify jitter tolerance analysis of reference clock components, it is easiest to verify that the clock oscillator's phase noise integrated over the 10 kHz–20 MHz band (with respect to fundamental, that is, dBc/Hz) is no greater than 1.2 picoseconds single-σ (RMS). Crystal oscillator vendors (such as Vectron International) provide application notes showing this conversion in detail or will provide the integrated values directly.

7.2.4 1588 Reference ClockThe input reference clock signal for IEEE 1588 operation has similar electrical requirements for the device REFCLK input as those in , except over a QSGMII Operation and Clock Input Requirementsdifferent range of input frequencies. Differential signaling is recommended for this input. For more information, see the device datasheet.



7.3 LEDsThe LED interface supports the following configurations: direct drive, basic serial LED mode, and enhanced serial LED mode. Each LED pin can be configured to display different status information that can be selected by setting the LED mode in register 29. Additional LED modes may be enabled on the LED0 pin whenever register 19E1, bits 15 to 12 are set to 1 (see the VSC8584 datasheet for information on specific LED settings, including the default drive state).

For direct-drive, each VSC8584 PHY port can support up to four single-colored LEDs or two bi-colored LEDs. Each LED pin sinks current when an indication is present and de-asserts when inactive. By design, each LED pin can also drive current when not active (this is very useful for bi-colored LEDs). Each LED pin in the VSC8584 device can be designated to indicate any of the possible LED status signals, further simplifying the overall design.

Figure 11 • LED Configurations



8 Schematic and Layout Review ChecklistThe following checklist should be reviewed to ensure proper design connectivity and pin group considerations.

8.1 Reference ClockThe following table shows the reference clock pins checklist.

Table 1 • Reference Clock Pins

Name Comment

REFCLK_P/N Ensure the clock driver meets jitter performance requirements. 125 MHz is highly recommended for QSGMII operation.Note:

Ensure the differential clock driver common mode voltage requirements are met or use ACcouplingcapacitors.

Refclk inputs are self-biased to 1 V (VDDA) with an internal termination, thusNote:no external biasing or termination components are needed.

RCVRD_CLK[1:0] If used, place an external series termination resistor, often 22 Ω–40 Ω near the source.

RefClk_Sel2 Internal pull-up. Ensure proper polarity: 1=125 MHz, 0=25 MHz.

CLK_SQUELCH_IN Internal pull-up. Place an optional resistor to GND for potential debug using the recovered clock.

8.2 1588 SignalsThe following table shows the 1588 signal pins checklist.

Table 2 • Reference Clock Pins

Name Comment

1588_DIFF_INPUT_CLK_P/N For IEEE-1588 applications, a quality oscillator is recommended. Use ACcouplingbecause the differential clock pair is self-biased to VDD1A. Noexternal termination is required, as there is an internal termination.

1588_LOAD_SAVE/GPIO10 May be left floating if unused.If used as a 1588 time of day load/save pin, take notice of the trace length.

1588_PPS_1/1588_SPI_IN_CLK Optional use. May be left floating if unused.If used as a PPS signal, take notice of the trace length and skew to otherPPS signals.If used as a 1588 SPI input clock for daisy-chained time-stamping content,ensure length matching to achieve setup/hold.

1588_PPS_2/1588_SPI_IN_CS Optional use. May be left floating if unused.If used as a PPS signal, take notice of the trace length and skew to otherPPS signals.If used as a 1588 SPI input chip select for daisy-chained time-stampingcontent, ensure length matching to achieve setup/hold.

1588_PPS_3/1588_SPI_IN_DI Optional use. May be left floating if unused.

If used as a PPS signal, take notice of the trace length and skew to otherPPS signals.If used as a 1588 SPI input data for daisy-chained time-stamping content,ensure length matching to achieve setup/hold.



Name Comment

1588_PPS_0/GPIO11 Optional use. May be left floating if unused.

If used as a PPS signal, take notice of the trace length and skew to otherPPS signals.If used as a GPIO, verify that the drive strength meets the application.

1588_PPS_RI Optional use (for calibration only). Tie to GND if not used.

1588_SPI_CLK/GPIO14 Optional use. May be left floating if unused.

3-pin TS push-out SPI, typically used in 2-step mode.

1588_SPI_CS/GPIO12 Optional use. May be left floating if unused.


1588_SPI_DO/GPIO13 Optional use. May be left floating if unused.


8.3 Twisted PairThe following table shows the twisted pair pins checklist.

Table 3 • Twisted Pair Pins

Name Comment

TXVPA_[3:0], TXVNA_[3:0]TXVPB_[3:0], TXVNB_[3:0]TXVPC_[3:0], TXVNC_[3:0]TXVPD_[3:0], TXVND_[3:0]

The naming convention used is such that [3:0] is the port identification and [A–D] isthe differential pair identification.Route as differential 100 Ω impedance or single ended 50 Ω impedance referenceto GND.

The correct RJ-45 connectivity to support 1GbE includes pairs (1,2;Note:3,6; 4,5; 7,8)Optional TVS components may be added, assuming the junction capacitance< 3 pF. Differential pair traces should be kept the same length.

Refer to the Magnetics Guide application note (ENT-AN0098) for more information about:

CMC on the line sidePHY side center taps individually AC-coupled to GNDIndividual Bob Smith termination per channelReturn loss: 18 dB for 1 MHz–40 MHz and 12–20log(f/80) dB over 40 MHz–100 MHzImportance of the flatness of frequency response from 1 MHz–40 MHzTurn ratio tolerance ±3% or betterInsertion loss ~1 dBCMNR 35 dB or betterCrosstalk 35 dB or better12 cores to provide better EMI

8.4 Fibre MediaThe following table shows the fibre media pins checklist.

Table 4 • Fibre Media Pins

Name Comment

FIBRIP/N_[3:0] Fibre input. May be left floating if unused.Maintain equal trace lengths for differential pairs.



Name Comment

FIBROP/N_[3:0] Fibre output. May be left floating if unused.

Maintain equal trace lengths for differential pairs.

SIGDET[3:0] If fibre media is used, this signal should be tied to LOS of the SFP module.

May be left floating if unused, or configured as a GPIO if needed.

GPIO[8:4] for I2C interface This interface does not support clock stretching.May be left floating if unused, or configured as GPIO if needed.

8.5 MAC InterfaceThe following table shows the MAC interface pins checklist.

Table 5 • MAC Interface Pins

Name Comment

TDP/N_[3:0] Input. Use AC-coupling for DC level adjustment and EMI suppression.For QSGMII, differential intra-pair skew must be kept to no more than 5 ps.Ensure Rx to TX spacing to minimize cross talk.

RDP/N_[3:0] Output. Use AC-coupling for DC level adjustment and EMI suppression. Reviewthe type of termination at the receiving end if not a Microsemi device.For QSGMII, differential intra-pair skew must be kept to no more than 5 ps.Ensure Rx to TX spacing to minimize cross talk.

SerDes_Rext[1:0] Bias resistor of 620 Ω ±1% in-between.

8.6 SMI InterfaceThe following table shows the SMI interface pins checklist.

Table 6 • MAC Interface Pins

Name Comment

MDC If not point-to-point, layout as a daisy chain rather than branching (which results in stubs).Confirm voltage swing compatibility with station master and other slaves on the bus.

MDIO If not point to point, layout as a daisy chain rather than branching (which results in stubs).Open drain I/O, thus a ~1.5K Ω pull-up resistor to the proper supply is required.

MDINT Open-drain output, thus a pull-up resistor to the proper supply is required.

NRESET Internal pull-down. Only de-assert NRESET after all power supplies and reference clocks are stable.

PHYADD[4:2] Internal pull-down.

PHYADD1 Internal pull-up.

8.7 SPI SlaveThe following table shows the SPI slave pins checklist.

Table 7 • SPI Slave Pins

Name Comment

SPI_IO_CLKSPI_IO_CSSPI_IO_DISPI_IO_DO

Optional use. Slave SPI I/O for 1588 and MACsec register access.Highly recommended for MACsec applications with more than twoslaves on the MDIO bus.



8.8 JTAG InterfaceThe following table shows the JTAG interface pins checklist.

Table 8 • JTAG Interface Pins

Name Comment

TCK, TDI, TDO, TMS May be left floating if unused.

TRST Internal pull-up. Must be pulled low during normal operation.

8.9 Miscellaneous PinsThe following table shows the miscellaneous pins checklist.

Table 9 • Miscellaneous Pins

Name Comment

THERMDA Add a test pad and optional 0 Ω to GND if unused.

THERMDC_VSS Add a test pad if unused.

REF_REXTREF_FILT

REF_REXT must use be 2.0K Ω 1% resistor and REF_FILT mustuse a 1 μF capacitor. The two components must join at a singlecommon point connected to the analog ground plane (see

Pins).REF_FILT/REF_REXT

COMA_MODE Internal pull-up. If not planned to be configured through software, thissignal must be pulled-down to enable PHY operation. This signal isalso used to synchronize LED operation amongst multiple chips.

LED[0:3]_PHY[0:3] If unused, leave floating. LED pins shall have a low series resistance.Ensure each chosen pin can drive the correct LED indication.

RESERVED Leave floating.

8.10 Power PinsFor proper decoupling and filtering details, see , Power Supply Planes Analog Power Plane

, and .Filtering Local Decoupling

Table 10 • Power Pins

Name Comment

VDD1A 1.0 V analog supply, mostly associated with the SerDes.

VDD1 1.0 V digital core supply.

VDD25A 2.5 V analog supply, mostly associated with the twisted pair interface.

VDD25 2.5 V digital core supply.

VDD_MDIO 1.2 V or 2.5 V for SMI (MDC and MDIO) pins. Ensure proper decoupling.

VSS (GND) For proper decoupling and filtering details, see Ground Isolationand .Bob Smith Termination



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© 2016 Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.

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VPPD-03550

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