of design parameters that the performance of multi cards · 2017. 3. 26. · –ansys hfss –ansys...
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Analysis of Design Parameters that Affect the Performance of Multi‐
site Vertical Probe Cards
Analysis of Design Parameters that Affect the Performance of Multi‐
site Vertical Probe Cards
Mohamed Eldessouki, PhDSV TCL – An SV Probe Company
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OverviewOverview• Motivation• Objective• PDN Impedance• PDN Elements & Simulation Results• Summary & Conclusion
2Mohamed Eldessouki
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MotivationMotivation• Customer
– Power plane requirements for high pin count multi‐DUT probe cards (Mobile Processor, Memory, …etc.) specifically,
– DC Resistance• Why is it important? How does it effect performance?
Related directly to voltage dropSensitive to Site to site design variation.
– Input Impedance• Why is it important? How does it effect performance?
Directly related to noise (SSN and crosstalk)Parameters are inductance and decoupling cap value & location.Vary from site to site due to sites orientations
3Mohamed Eldessouki
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ObjectiveObjective• Study Interconnect parameters that contribute to:– DC path resistance– Input impedance
• Find optimum design that minimizes DC path resistance & input impedance– Design elements & variables
4Mohamed Eldessouki
• Tools Used – ANSYS HFSS– ANSYS SIwave– Agilent ADS
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PDN impedance calculationPDN impedance calculation• Maximum allowable voltage drop
– Minimum DUT operating voltage– Maximum supply current – Target path resistance
5Mohamed Eldessouki
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PDN impedance calculationPDN impedance calculation• Maximum noise allowed
– Maximum voltage ripple– Transient current – Bandwidth
6Mohamed Eldessouki
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PDN impedance calculationPDN impedance calculation• Faster current delivery
– Decoupling caps location – Minimize trace inductance
• Low resistance & inductance for return path– Loop resistance– Loop inductance– GND coupling
7Mohamed Eldessouki
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• Source (tester)• Bulk & Decoupling Caps• Inductors & Ferrite Beads (LPF)• PCB Via
– Via diameter, length & plating– Via location to GND via– No of via connection
• PCB PWR Plane– Size (thickness, length, width)– Location of PWR plane wrt GND plane– No of PWR planes for each PWR net.– PWR Plane shape
8Mohamed Eldessouki
PDN ElementsPDN Elements
Probe CardProbe Card
PCBPCBMST, MLO, MLCMST, MLO, MLC
PHPH
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PDN ElementsPDN Elements
• Low Frequency Model– Length– Plating– Distance from GND via– Number of connections
• High Frequency Model– Skin effect– Proximity effect
L
d
L
dδ
Mohamed Eldessouki
Plated ViaSolid Via
Via Equivalent CircuitVia Equivalent Circuit
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PDN Simulation ResultsPDN Simulation Results
Case1• Single PWR via & GND via with the following conditions:– Constant via length 40 mils– Constant via plating thickness 1mil (Cu)– Via diameter (=6,8,10 and 12mils)– Via spacing =3 x via diameter– Solder pad diameter or keep‐out = 2x via diameter
10Mohamed Eldessouki
Via SimulationVia Simulation
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PDN Elements & simulation ResultsPDN Elements & simulation Results
11Mohamed Eldessouki
Via SimulationVia Simulation
Resistance Increase Resistance Increase
No Change in Inductance or CapacitanceNo Change in Inductance or CapacitanceCase1
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PDN Simulation ResultsPDN Simulation Results
12Mohamed Eldessouki
Via SimulationVia Simulation
R is inversely proportional with via diameter R is inversely proportional with via diameter
• How much path resistance changed?
–
• How much inductance changed?
– 2 2 / 1/4
If (S/r) is constant, loop inductance and coupling capacitance stay constantIf (S/r) is constant, loop inductance and coupling capacitance stay constant
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PDN Simulation ResultsPDN Simulation Results
13Mohamed Eldessouki
Via SimulationVia Simulation
No Change in loop Inductance
No Change in loop Inductance
Case1: Single PWR via & Single GND via
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PDN Simulation ResultsPDN Simulation Results
14Mohamed Eldessouki
Via SimulationVia Simulation
No Change in Coupling Capacitance
Case1: Single PWR via & Single GND via
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PDN Simulation ResultsPDN Simulation Results
Case2– Two 6mil via Vs single 12mil via:– Use a single via (PWR‐GND)
structure s‐parameter obtained by ANSYS‐HFSS
– Use Agilent ADS for complete system simulation
– Assumption: No coupling between the two via system
15Mohamed Eldessouki
Via SimulationVia Simulation
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PDN Simulation ResultsPDN Simulation Results
16Mohamed Eldessouki
No Change in Resistance
~50% Impedance reduction with two 6 mils viaVia SimulationVia SimulationCase2
12 mils via
two 6 mils via
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PDN Simulation ResultsPDN Simulation Results
17Mohamed Eldessouki
Via SimulationVia SimulationCase2
Inductance dropped by ~50%Inductance dropped by ~50%
12 mils via
two 6 mils via
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PDN Simulation ResultsPDN Simulation Results
18Mohamed Eldessouki
Via SimulationVia SimulationCapacitance increased by 55%Capacitance increased by 55%
12 mils via
two 6 mils via
Case2
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PDN Simulation ResultsPDN Simulation Results
•Case3– Comparison between two 6mil via vs single 12mil via using ANSYS HFSS
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12 mil via12 mil via 6 mil via Cross Configuration6 mil via Cross Configuration
6 mil via Inline Configuration6 mil via Inline Configuration
Mohamed Eldessouki
Via SimulationVia Simulation
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6 mils inline
6 mils cross
12 mils via
PDN Simulation ResultsPDN Simulation Results
Input Impedance for 1‐ two 6 mils via inline2‐ two 6 mils via cross3‐ single 12 mils via
20Mohamed Eldessouki
Via SimulationVia Simulation
60 mΩ drop VS 82 mΩ
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21Mohamed Eldessouki
PDN Simulation ResultsPDN Simulation Results
Inductance for1‐ two 6 mils via inline2‐ two 6 mils via cross3‐ single 12 mils via
Via SimulationVia Simulation
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22Mohamed Eldessouki
PDN Simulation ResultsPDN Simulation Results
Capacitance for1‐ two 6 mils via inline2‐ two 6 mils via cross3‐ single 12 mils via
Via SimulationVia Simulation
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x
y
…
…
…… … … …
…
Mohamed Eldessouki
PDN Simulation ResultsPDN Simulation ResultsReal Estate CalculationReal Estate Calculation
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PWR Plane SimulationPWR Plane Simulation
24Mohamed Eldessouki
PDN Simulation Results
• PWR Plane location investigation
• Via size impact on PWR Plane impedance
• Duplicating PWR plane impact on input impedance
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PWR Plane SimulationPWR Plane Simulation
• Case I– PWR Plane close to DUT
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• Case II– PWR Plane close to tester
Mohamed Eldessouki
PDN Simulation ResultsPDN Simulation Results
• 24 via connection from DUT to PWR Plane
• 1 via connection from Tester to PWR Plane
PWR Plane Location Tester side
Tester side
DUT side
DUT side
PWR via + 6 GND via
24 via + 24 GND via
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• Case I– PWR Plane close to DUT
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• Case II– PWR Plane close to tester
Mohamed Eldessouki
PWR Plane SimulationPWR Plane SimulationPDN Elements & Simulation Results
PWR Plane Location
mZin 351
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•Case I– Single PWR plane
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•Case II– Double PWR plane
Mohamed Eldessouki
PWR Plane SimulationPWR Plane SimulationPDN Elements & Simulation Results
Single PWR Plane Vs Double PWR Plane
mZin 190
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28Mohamed Eldessouki
PWR Plane SimulationPWR Plane SimulationPDN Elements & simulation Results
Single PWR Plane Vs Double PWR Plane
Inductance & Capacitance
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29Mohamed Eldessouki
System SimulationSystem SimulationPDN Elements & Simulation Results
• Case I– Double 6 mil via with 6mil PWR plane
• Case II– 12 mil via with 12 mil PWR plane
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System SimulationSystem SimulationPDN Elements & Simulation Results
• Case I– Double 6 mil via
with 6mil PWR plane
• Case II– 12 mil via with 12
mil PWR plane
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• Case I– Double 6 mil via
with double 6mil PWR plane
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• Case II– 12 mil via with 12
mil PWR plane
Mohamed Eldessouki
System SimulationSystem SimulationPDN Elements & Simulation Results
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SummarySummary
32Mohamed Eldessouki
– Two elements were investigated:• Via• PWR plane
– Different configurations were applied with different parameters:• Via diameter• Number of via connection• Via location & coupling effect• PWR plane location in the stack‐up• Number of PWR plane
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ConclusionConclusion
33Mohamed Eldessouki
• For optimum performance–Keep S/r ratio of PCB via to keep loop inductance constant
–Reduce PCB via diameter & increase number of via
–Reduce the coupling between GND‐GND & PWR‐PWR
–Reduce the input impedance by doubling PWR plane
–Location of PWR plane should be based on minimizing the length of smaller number of via connections
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Summary & ConclusionSummary & Conclusion
34Mohamed Eldessouki
• Benefits– Reducing Site‐to‐Site input impedance variation in multisite PC
– Reducing Tester Program (TP) development time
– Eliminating TP delay changes when ramping additional probe hardware
– Produce High yield in multisite probing