Integration of High-Speed CMOS

Sample-and-Hold Circuits

Mikko Waltari

Helsinki University of Technology

February 16, 1999

HELSINKI UNIVERSITY OF TECHNOLOGY

Department of Electrical and Communications Engineering

Mikko Waltari

INTEGRATION OF HIGH-SPEED CMOS

SAMPLE-AND-HOLD CIRCUITS

Licentiate's Thesis submitted for examination in Espoo, February 16. 1999

Supervisor

professor Kari Halonen

2nd examiner

Kimmo Koli, Lic.tech.

HELSINKI UNIVERSITY OF TECHNOLOGYABSTRACT OF THE

LICENTIATE'S THESIS

Author: Mikko Waltari

Name of the thesis: Integration of High-Speed CMOS

Sample-and-Hold Circuits

Date: 16.2. 1999 Number of pages: 95

Faculty: Electrical and Communications Engineering

Professorship: S-87 Electronic Circuit Design

Supervisor: professor Kari Halonen

2nd examiner: Kimmo Koli Lic.tech.

This thesis concentrates on the CMOS integration of high-speed sample-and-hold circuits

suitable for wide-band communications applications. The thesis includes a comprehensive

review of publications from the research area. It has been used to show the strengths

and weaknesses of di�erent architectures.

The distortion characteristics of the MOS-switch are studied in order to �nd out how

the harmonic distortion can be minimized. An analysis of the non-idealities in double-

sampled circuits is carried out. The double-sampling is a technique which can be used to

double the clock rate of switched capacitor circuits without tightening the speci�cations

set for the operational ampli�er. It turns out that the main problem in the double-

sampling is the potential timing skew between the parallel sampling circuits.

Two prototype circuits employing the double-sampling have been designed and fabricated.

One of the circuits uses a new technique to avoid the distortion due to the timing skew.

According to the measurement results the realized circuits are the fastest CMOS sample-

and-hold circuits ever reported.

Keywords: sample-and-hold

CMOSdouble-sampling

SC-circuit

timing skew

MOS switch

i

TEKNILLINEN KORKEAKOULU LISENSIAATTITYÖN TIIVISTELMÄ

Tekijä: Mikko Waltari

Työn nimi: Nopeiden näytteistyspiirien integrointi CMOS-tekniikalla

Päivämäärä: 16.2. 1999 Sivumäärä: 95

Osasto: Sähkö- ja tietoliikennetekniikan osasto

Professuuri: S-87 Piiritekniikka

Työn valvoja: professori Kari Halonen

Toinen tarkastaja: TkL Kimmo Koli

Tässä työssä on tutkittu laajakaistaisiin tiedonsiirtojärjestelmiin soveltuvien näytteistys-

piirien integrointia CMOS-teknologialla. Työ sisältää laajan katsauksen alan julkaisuihin,

jonka avulla käydään läpi eri piiriarkkitehtuurien heikkoudet ja vahvuudet.

MOS-transistorin käyttöä kytkimenä on tutkittu harmonisen särön minimoimisen näkö-

kulmasta. Lisäksi on analysoitu kaksoisnäytteistystekniikkaa, jolla SC-piirien kellotaa-

juus voidaan kaksinkertaistaa kasvattamatta operaatiovahvistimelle asetettuja vaatimuk-

sia. On osoittautunut, että tekniikan suurin ongelma on rinnakkaisten piirien näytteistys-

signaalin ajastuksessa.

Lopuksi esitellään kaksi kaksoisnäytteistykseen perustuvaa piiritoteutusta, joista jälkim-

mäisessä on pystytty poistamaan näytteistyssignaalin ajoitusvirheestä juhtuva häiriö

uutta tekniikkaa käyttäen. Mittaustulosten mukaan kehitetyt piirit ovat nopeimpia

koskaan raportoituja CMOS-tekniikalla toteutettuja näytteistyspiirejä.

Avainsanat: näytteistyspiiri

CMOS

kaksoisnäytteistys

SC-piiri

MOS-kytkin

ii

Preface

It was not easy to start the writing of this thesis particularly in foreign language

but it seems to be even harder to �nish. A feeling that I haven't said everything

I should or that I can �nd a more elegant formulation for some equation has

kept me revising the manuscript for days. Fortunately the time is running out

so I have to hit the last enter and start doing the 'real work' again.

I want to thank the people in the laboratory for advice and fruitful discus-

sions specially mentioning Saska Lindfors and Kimmo Koli. I am also grateful

to professor Kari Halonen for giving me time and freedom to concentrate in my

research.

I also want to thank Miia for patience and understanding that I hope will

last until my doctoral thesis are at this point some day in the next millennium.

Espoo, February 5, 1999

Mikko Waltari

iii

Contents

1 Introduction 1

2 Sample-and-Hold Operation 3

2.1 S/H Basics and Performance Metrics . . . . . . . . . . . . . . . . 3

2.2 Spectra of Sampled Signals . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Spectrum of a Sampled and Held Signal . . . . . . . . . . 7

2.2.2 Sampling Function . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Noise Issues in S/H Circuits . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 kT=C Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.2 Jitter in Sampling Clock . . . . . . . . . . . . . . . . . . . 10

2.3.3 Other Noise Sources . . . . . . . . . . . . . . . . . . . . . 11

2.4 Basic S/H Circuit Architectures . . . . . . . . . . . . . . . . . . . 12

2.4.1 Open-Loop Architectures . . . . . . . . . . . . . . . . . . 12

2.4.2 Closed-Loop Architectures . . . . . . . . . . . . . . . . . . 13

3 S/H Architectures and Implementations 15

3.1 Bipolar Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Diode Bridge . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.2 Switched Emitter Follower . . . . . . . . . . . . . . . . . . 16

3.2 CMOS Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 S/H Circuit with Source Follower Bu�er . . . . . . . . . . 19

3.2.2 S/H Circuit Using Miller Capacitance . . . . . . . . . . . 22

3.2.3 Charge Domain Gated-gm Sampler . . . . . . . . . . . . . 23

3.2.4 Switched Transconductance S/H Architecture . . . . . . . 25

3.2.5 Closed-Loop S/H Circuit with Resistor Ratio De�ned Gain 26

3.2.6 Closed-Loop S/H Circuit with Capacitor Ratio De�ned

Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

iv

3.2.7 S/H Circuit without a Reset Phase . . . . . . . . . . . . . 28

4 Sampling with a MOS Transistor Switch 30

4.1 Voltage Dependent Turn-O� Moment . . . . . . . . . . . . . . . 31

4.2 Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3 Bottom Plate Sampling . . . . . . . . . . . . . . . . . . . . . . . 37

4.4 Nonlinear time constant . . . . . . . . . . . . . . . . . . . . . . . 39

4.4.1 Distortion in CMOS and NMOS Switches: Comparison . 40

4.4.2 Lowering Switch On-Resistance with Gate Voltage Boosting 45

4.5 Sampling Function . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5 Double-Sampling 49

5.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2 Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.2.1 Memory e�ect . . . . . . . . . . . . . . . . . . . . . . . . 51

5.2.2 O�set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.2.3 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2.4 Timing Skew . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3 Proposed Skew Insensitive Circuit . . . . . . . . . . . . . . . . . 61

6 Dynamic Measuring of S/H Circuits 63

7 Prototype Design and Experimental Results 65

7.1 1st circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.1.2 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.1.3 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . 69

7.1.4 Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.1.5 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.1.6 Experimental Results . . . . . . . . . . . . . . . . . . . . 74

7.2 2nd circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.2.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . 80

7.2.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . 81

8 Conclusions and Future Work 84

v

Symbols and Abbreviations

�(t) Dirac's delta function

� Mobility

! Corner frequency

�2 variance

� Time constant

A Open-loop DC-gain

B Signal bandwidth

COX Oxide capacitance

f Frequency, feedback factor

fS Sampling frequency

f3dB 3 dB frequency

k Boltzmann's constant

L Channel length

T Sampling period, absolute temperature

Vdd Positive supply voltage

Vss Negative supply voltage

Vth Threshold voltage

W Channel width

vi

ADC Analog-to-digital converter

BiCMOS Bipolar CMOS

BJT Bipolar junction transistor

CCD Charge coupled device

CDS Correlated double sampling

CM Common mode

CMFB Common mode feedback

CMOS Complementary-metal-oxide-silicon

DAC Digital-to-analog converter

DC Direct current

DLL Delay locked loop

FFT Fast Fourier transform

GaAs Gallium arsenide

GBW Gain-bandwidth product

h(t) Sampling function

IC Integrated circuit

MOSFET Metal-oxide-silicon �eld-e�ect transistor

OTA Operational transconductance ampli�er

PLL Phase locked loop

S/H Sample-and-hold

SC Switched capacitor

SFDR Spurious free dynamic range

SINAD see SNDR

sinc(x) sin(x)/x

vii

SNDR Signal-to-noise-and-distortion ratio

SNR Signal-to-noise ratio

T/H Track-and-hold

THD Total harmonic distortion

Vpp Volts peak-to-peak

viii

Chapter 1

Introduction

The rapid growth of multimedia services has increased the demand for band-

width both in the wired and wireless terminals targeted to the consumer market.

The trend has also been towards systems that relay more and more on the digi-

tal signal processing. These things together have created an increasing demand

for high-speed analog-to-digital converters (ADCs). The cost driven consumer

market prefers CMOS solutions which o�er low fabrication cost and potential

for high integration level.

The conversion from a continuous time analog signal to a digital signal can

be separated in two phases. First the continuous time signal is sampled at

uniform time intervals and then the voltage samples are quantized to digital

bit codes. The sampling and the quantization can be performed simultaneously

as in the �ash type ADCs. However, doing them separately gives a better

performance since then the quantization circuit need not to handle a continuous

time signal. This is especially emphasized in the folding-and-interpolating and

parallel ADCs.

The sampling is typically done with a sample-and-hold (S/H) circuit which

can be a stand alone block or it can be integrated in the ADC front-end. The

CMOS technology o�ers both challenges and opportunities for the high-speed

S/H circuit design. The main challenges are the limited speed and the linearity

problems particularly when operating on low supply voltages. In this thesis

answers and optimal solutions to these problems are investigated through an

extensive literature survey, theoretical analysis, simulations and a design process

of two prototype circuits.

The organization of the thesis is as follows: The basic theory of the S/H

1

circuits and the commonly used performance metrics are presented in Chapter 2.

In Chapter 3 some published CMOS and bipolar S/H circuits are introduced

emphasizing their strengths and weaknesses. Chapter 4 is a study of the MOS

switch and especially its distortion characteristics. The double-sampling and

its nonidealities are investigated in Chapter 5. Also a new technique to avoid

the timing skew is proposed. The basics of the high-speed measurements of

S/H circuits are presented in Chapter 6. Chapter 7 describes the design of two

prototype circuits and presents the experimental results. A conclusion is made

in Chapter 8 by comparing the realized circuits with other published circuits.

The work described in this thesis has been partly published in [1]�[5].

2

Chapter 2

Sample-and-Hold Operation

2.1 S/H Basics and Performance Metrics

The main function of a sample-and-hold (S/H) circuit is to take samples of its

input signal and hold these samples in its output for some time period. Typically

the samples are taken at uniform time intervals thus the sampling rate (or clock

rate) of the circuit can be determined.

The operation of a S/H circuit can be divided in to the sample mode (some-

times also referred as acquisition mode) and the hold mode, whose durations

need not to be equal. In the hold mode the output of the circuit is equal to the

previously sampled input value. In the sample mode the output can either track

the input, when the circuit is often called a track-and-hold (T/H) circuit or it

can be reset to some �xed value. In some circuits the output is held the whole

period of the sampling clock. This is achieved by having a separate circuitry to

perform the sampling and the holding operations.

Sample-and-HoldTrack-and-Hold

t t

Figure 2.1: Output waveforms of di�erent S/H circuits.

3

acquisition time

droop rate

hold step

Output

Input

hold settling time

CLK

taperture delay

Figure 2.2: Time domain S/H circuit performance metrics.

The most common terms and performance metrics used in conjunction with

S/H circuits ([6][7]) are shortly introduced in the remainder of this section.

Which of them are more important than the others greatly depends on the ap-

plication of the S/H circuit. The used implementation technology also has some

e�ect on which parameters are usually given in circuit speci�cations. To fully

characterize a S/H circuit speci�cations both in time domain and in frequency

domain has to be de�ned. Unfortunately, some of the terms used are not well

established and thus the de�nitions in di�erent sources may be contradictory.

The acquisition time is the time from the command to switch from hold

mode to the sample mode to the moment when the circuit is ready to take a

new sample i.e. it tracks the input. Acquisition time is one of the parameters

that de�ne the maximum achievable sampling rate.

The aperture time or aperture delay is the �xed time from the sampling

command to the moment when the sample is actually taken.

Random variation of the sampling moment is called aperture uncertainty or

aperture jitter.

The hold mode settling time determines the time from the sampling moment

to the moment when the circuit output has settled within speci�ed accuracy of

its steady state value. If the S/H circuit is used in front of an ADC, the ADC

can digitize the S/H circuit output at that moment. The hold mode settling

4

time has a major impact on the maximum sampling rate of the S/H circuit.

There can be signal leakage from the S/H circuit output during the hold

mode. The output rate of change due to this is speci�ed by the droop rate.

The hold step or pedestal error is usually de�ned for track-and-hold circuits.

It is the di�erence in the output value at the end of the tracking and at the

hold mode. The pedestal may be signal dependent and thus produce harmonic

distortion.

During the hold mode the signal at the circuit input may couple to the

output. The amount of the input signal seen at the output is speci�ed by the

hold mode feedthrough.

Usually S/H circuits have an unity gain (i.e. the amplitude of the output

signal is equal to the amplitude of the input signal) but other gain values are

also applicable. The gain error determines the deviation of the gain from the

nominal value.

The dynamic range is the di�erence in decibels between the maximum al-

lowed input voltage and the minimum input voltage that can be sampled with

a speci�ed accuracy.

Nonlinearity in the S/H circuit causes distortion. Measured with a sinusoidal

input signal the total harmonic distortion (THD) is the ratio of the sum of

error energy in the frequencies harmonically related to the input frequency to

the signal energy at the fundamental frequency. The THD can be given in

percents or in decibels. In sampled data systems the aliasing complicates the

identi�cation of the harmonic frequencies in the spectrum.

The spurious free dynamic range (SFDR) is the ratio of the largest spurious

frequency and the fundamental frequency.

The signal-to-noise ratio (SNR) is the ratio of noise energy to the signal

energy.

The signal-to-noise-and-distortion ratio (SNDR or SINAD) is the ratio of

all error energy to the signal energy. Quite often the term signal-to-noise ratio

is used although SNDR is actually meant.

When a S/H circuit is employed in the ADC front-end it is meaningful to

speak of resolution, which is expressed as number of bits. The resolution is

just another way to express the SNDR for the maximum input signal and it is

obtained by (SNDR� 1:76)=6:02.

5

T

tX(t)

Figure 2.3: Sampling in time domain.

2.2 Spectra of Sampled Signals

An ideal S/H circuit takes samples of an input signal at uniform intervals T . In

the time domain this corresponds to multiplying the signal by an impulse train

y(t) = x(t) �1X

n=�1

�(t� nT ); (2.1)

where �(t) represents the Dirac's delta function. The result is a train of impulses

whose values correspond to the instantaneous values of the input signal.

The spectrum of the sampled signal is a convolution of the input spectrum

and the spectrum of the impulse train which also is an impulse train

Y (f) = X(f) ?1X

n=�1

1

T�(f �

n

T): (2.2)

This is illustrated in Figure 2.4, where fS is the sampling frequency and B

the signal bandwidth. The resulted spectrum is the original spectrum plus an

in�nite number of images of the original spectrum centered at multiples of the

sampling frequency. The �gure also clearly shows that as long as the bandwidth

of the input signal is less than half of the sampling frequency the images do not

overlap and thus the original signal can be restored by �ltering. If this condition

known as the Nyquist criterion is not satis�ed a part of the image spectrum is

aliased into the desired signal band causing irreversible distortion. Due to this

the input signal usually has to be band limited before sampling to avoid the

aliasing of noise and other unwanted signals present outside the desired signal

band. In the sub-sampling (or under sampling) the aliasing is utilized to sample

high frequency narrow-band signals. There a signal band around some multiple

of the sampling frequency is aliased to the baseband, which actually corresponds

to down conversion. The noise aliasing and sampling clock jitter prevent from

using this technique in high performance radio receivers.

6

f

f

f

0

0

2BSignal spectrum

Spectrum of the sampling waveform

Spectrum of the sampled signal

fS-fS 2fS-2fS

0 fS-fS 2fS-2fS

Figure 2.4: Spectrum of a sampled signal.

tT

Figure 2.5: A Sampled-and-held signal.

2.2.1 Spectrum of a Sampled and Held Signal

In practice the output waveform of a sampling circuit cannot be a train of

in�nitely narrow impulses. In most practical implementations the sample is

held in the output of the circuit until the next sample is taken (Figure 2.5). In

that case the circuit is called a sample-and-hold (S/H) circuit. Sometimes the

output tracks the input for half of the sample period and is held in the sampled

value for the other half. This type of circuit can be called a track-and-hold

(T/H) circuit. However, inconsistent terminology is seen quite often.

If the signal processing after a S/H circuit is done in discrete time, which

is e.g the case in ADCs with a front-end S/H circuit, the spectrum is the ideal

periodic spectrum as in Figure 2.4. On the contrary if the output waveform of

the S/H circuit is used as a continuous time signal the spectrum is di�erent.

A deglitcher preceding a DAC is a typical example of this kind of circuit. A

similar situation can also occur when measuring S/H circuits.

The time domain representation of a sampled-and-held signal is a convolution

7

f0 fS 2fS

Figure 2.6: Spectrum of sampled-and-held signal.

of the sampled signal (2.1) and a square pulse

y(t) =

"x(t) �

1Xn=�1

�(t� nT )

#?�

�t

T�

1

2

�; (2.3)

where �(t=T�1=2) denotes a square pulse from t = 0 to t = T . In the frequency

domain the convolution corresponds to multiplication and thus the spectrum of

the sampled-and-held signal is the spectrum of a sampled signal multiplied by

the spectrum of the square pulse, which has the form of sin(x )/x. Using this

well known relation the spectrum of a sampled-and-held signal can be written

Y (f) = e�j�fT �sin(�fT )

�fT

1Xn=�1

X(f �n

T): (2.4)

A power spectrum of this form is shown in Figure 2.6. In many cases the sinc

attenuation is not tolerable and the signal has to be either predistorted before

the hold operation or corrected after it.

2.2.2 Sampling Function

When ideal impulses (Dirac's delta functions) are used to describe operations in

analog continuous time signal processing one should be on the alarm. It turns

out that it is impossible to realize a circuit performing the sampling according

to (2.1). A practical circuit cannot pick the instantaneous value of its input

signal, but it rather takes a weighted average of the input during a time window

around the sampling moment. Mathematically this equals to integrating the

product of the input signal and the sampling function from minus in�nity to

plus in�nity in time domain. For a single sample this can be written as follows

y(t0) =

Z1

�1

x(t)h(t � t0)dt; (2.5)

8

where t0 is the sampling instant and h(t) the sampling function. The same for

an in�nite sequence of samples is

y(nT ) =

1Xn=�1

Z1

�1

x(t)h(t � nT )dt (2.6)

=

1Xn=�1

x(nT ) ? h(�nT ) (2.7)

= [x(t) ? h(�t)]

1Xn=�1

�(t� nT ): (2.8)

The integral in (2.6) can be identi�ed as a convolution resulting (2.7). This

can be interpreted as a sampled form of the convolution integral. In (2.8) the

same is presented using the Dirac's delta function. Utilizing this the frequency

domain signal can be easily obtained with the Fourier transform:

Y (f) = [X(f) �H(�f)] ?

1Xn=�1

�(f �n

T): (2.9)

This shows that in the frequency domain the e�ect of the sampling function

is seen as a multiplication by the conjugate of the Fourier transform of the

sampling function. Since the Fourier transform of an impulse is 1 the equa-

tion (2.9) is consistent with (2.2). A more realistic sampling function than

the Dirac's delta function is a triangular pulse, whose Fourier transform is

sin2(�fTb=2)=(�fTb=2)2, where Tb is the width of the base of the triangle. In

general it can be said that a real sampling function always adds a low-pass �l-

tering e�ect to the sampling operation. The modeling of the limited tracking

bandwidth can also be included in the sampling function [8].

2.3 Noise Issues in S/H Circuits

2.3.1 kT=C Noise

Any sampling circuit can be considered consisting at least of a switch and a

capacitor. The switch has always some �nite on-resistance which generates

thermal noise. The power spectral density of this noise is the well known

4kTR V2/Hz, where k is the Boltzmann's constant, T the absolute temper-

ature and R the resistance. The noise in the voltage sample is the resistor noise

9

�ltered by the low-pass circuit formed of the sampling capacitor and the switch

on-resistance. Integrating the resistor noise spectral density weighted by the

low-pass transfer function yields the mean square noise voltage on the capacitor

�2 = 4kTR

Z1

0

1

1 + (f2�RC)2 df (2.10)

=4kTR

(2�RC)2

>>>>>>>>1

0

2�RC arctan(f2�RC) =kT

C: (2.11)

By looking at the result it is obvious why this noise is often called kT=C noise.

An interesting point is that the noise voltage does not depend on the value

of the switch on-resistance and thus the only parameter which can be used to

control the noise is the value of the sampling capacitor. Although the desired

signal bandwidth is typically at least order of magnitude smaller than the noise

bandwidth of the sampling circuit the sampled noise is still determined by (2.11).

This is due to the fact that the sampling operation aliases all the noise energy

into the Nyquist band.

In ADCs a common requirement is that thermal noise power is smaller than

the power of the quantization noise which can be shown to be LSB2=12. Uti-

lizing this the requirement leads the following lowest limit for capacitor value

C:

C >kT � 12

LSB2=

kT � 12

2�2NV 2fs

; (2.12)

where N is the number of bits and Vfs the voltage corresponding to the ADC

full scale. In the case of 1 volt full scale voltage the capacitor values required for

10 and 16 bit resolution are 0.052 pF and 210 pF respectively, which indicates

that the capacitor values for 16 bit resolution begin to be impractically large to

integrate. To overcome this a popular solution in high resolution applications

is to use an oversampling ADC architecture, where the capacitor size can be

reduced linearly with the oversampling ratio.

2.3.2 Jitter in Sampling Clock

Random variation of the sampling moment is called jitter. It originates from

the clock generator phase noise and the sampling circuit noise. How the jitter is

transformed to the amplitude error in the sampled voltages can be understood

as follows: The error in the sampled voltage is equal to the chance of the input

voltage between the ideal sampling moment and the actual sampling moment.

10

The voltage change in turn is proportional to the jitter and the rate of change

of the input signal i.e. its derivative. For a sinusoidal input the derivative is

the cosine function multiplied by the corner frequency, which means that the

voltage error is proportional to the frequency and the amplitude of the input

signal. It can be shown [10] that the signal-to-noise ratio limited by jitter can

be written

SNR = �20 log(2�f�t); (2.13)

where f is the frequency of the input signal and �t the rms value of the jitter. It

can be seen that increasing the amplitude of the input signal does not improve

SNR since it also increases the voltage error.

The clock generator phase noise is usually speci�ed with the single-side-band

noise density L(f). If it is constant for di�erent carrier frequencies, the following

relation holds for the rms jitter originating from the clock generator phase noise:

�t /1

fclk: (2.14)

The message of equations (2.13) and (2.14) is that a good SNR is achieved by

keeping the ratio of the signal frequency to the clock frequency small. In the

sub-sampling this principle is violated and thus the attainable performance is

limited.

2.3.3 Other Noise Sources

Most S/H circuits need a bu�er ampli�er or an opamp at least in the hold

mode. The internal noise sources of the ampli�er add in power to the thermal

noise of the switch on-resistances. In the passive sampling the noise is band

limited by the RC time constant of the sampling circuit. When an ampli�er

contributes to the circuit transfer function, which is usually the case in the hold

mode and in some closed-loop S/H architectures also in the sampling mode, its

�nite bandwidth is likely the dominating band limiting factor. To reduce the

amount of the aliased noise the bandwidth of the ampli�er should be kept as

small as permitted by the settling requirements [9]. This is important, since if

the S/H circuit is preceded by an ADC the S/H circuit noise during the hold

mode is also aliased due to the sampling performed by the ADC. Again if the

signal after the S/H circuit is treated as a continuous time the hold mode no

noise aliasing occurs.

11

In addition to the white noise the S/H circuits su�er also from the �icker

or 1=f noise. However, in high speed applications (clock frequency several

megahertz) the white noise typically dominates. This is further enhanced by the

noise aliasing. If the 1=f noise becomes a problem there are several techniques

like the correlated double sampling (CDS) or the chopper-stabilization to get

rid of it [9].

2.4 Basic S/H Circuit Architectures

In the hold mode a S/H circuit remembers the value of the input signal at the

sampling moment, thus it can be considered as an analog memory cell. The

basic circuit elements that can be employed as a memory are capacitors and

inductors of which the capacitors store the signal as a voltage (or charge) and

the inductors as a current. In addition to the inductor a current memory needs

a switch that is a good short circuit when it is closed. Respectively a switch,

that is a good open circuit in its o�-state, is needed for a voltage memory. Since

capacitors and switches with a high o�-resistance are far easier to implement in

a practical integrated circuit (IC) technology than inductors and switches with

a very small on-resistance, all sample-and-hold circuits are based on the voltage

sampling. There exists also current mode S/H circuits, but they always include

voltage-to-current and current-to-voltage converters which allow the sampled

quantity to be voltage.

The S/H circuit architectures can roughly be divided into open loop and

closed loop architectures. The main di�erence between them is that in the

closed loop architectures the capacitor where the voltage is sampled is enclosed

in a feedback loop at least in the hold mode.

2.4.1 Open-Loop Architectures

The simplest S/H circuit consists of a switch and a capacitor (Figure 2.7 (a)). In

the sample mode the switch is closed and the voltage on the capacitor tracks the

input signal. In transition to the hold mode the switch is opened and the input

voltage value at the switch opening moment stays on the capacitor. This circuit,

however, is impractical since it is not capable of driving any load. Therefore a

bu�er has to be used to drive the load. An input bu�er may also be needed

to adjust the signal level suitable for the switch and to reduce the hold mode

feedthrough. A S/H circuit with an input and an output bu�er is shown in

12

A1 A2CS CS

Vin Vout Vin Vout

(a) (b)

φ φ

Figure 2.7: A simple S/H circuit (a) and a practical S/H circuit (b).

−

+

−

+

Vin Vout

CH

φ

Figure 2.8: A basic closed-loop S/H circuit.

Figure 2.7 (b).

The main advantage of this open loop S/H architecture is its potentially

high speed. The accuracy, however, is limited by the harmonic distortion arising

from the nonlinear gain of the bu�er ampli�ers and the signal dependent charge

injection from the switch. These problems are especially emphasized with a

MOS technology.

2.4.2 Closed-Loop Architectures

A well known technique to improve the linearity is to employ negative feedback.

The feedback can be used internally in the bu�er ampli�ers in an open-loop

architecture like the one in Figure 2.7 (b). This does not still help with the switch

induced distortion. The signal dependent charge injection can be avoided by

operating the switch at a constant potential, which can be realized by enclosing

the switch in a feedback loop to create a virtual ground. Figure 2.8 shows a

basic closed-loop S/H circuit following this idea.

Due to the feedback the output tracks the input in the sample mode. The

switch is connected to the virtual ground provided by the second operational

ampli�er and thus it introduces only a constant error charge. When the switch

13

−

+

Vin

Voutφ

φ φ

φ

C

Figure 2.9: A switched capacitor S/H circuit.

is opened the global feedback loop is broken and the input voltage is sampled in

the capacitor CH . The capacitor is permanently connected in a feedback loop

around the second operational ampli�er, which is used as a bu�er both in the

track mode and the hold mode.

Since the feedback loop encloses two opamps in the tracking mode the circuit

has to be heavily compensated in order to avoid instability. This naturally

reduces the speed of the circuit. Another potential disadvantage is the hold

mode feedthrough via the parasitic input capacitances of the �rst operational

ampli�er.

A closed-loop S/H architecture commonly used in switched capacitor (SC)

circuits is shown in Figure 2.9. It performs the sampling passively i.e. it is done

without the opamp, which makes the signal acquisition fast. In the hold mode

the sampling capacitor is disconnected from the input and put in a feedback

loop around the opamp like in the circuit of Figure 2.8. The signal dependent

charge injection from the switches is avoided by a technique called bottom plate

sampling, which relays on a special timing of the switch control signals. This

technique is discussed in more detail in Section 4.3.

14

Chapter 3

S/H Architectures and

Implementations

This chapter gives a brief descriptions of the S/H architectures found in the

recent publications. Although the focus of this thesis is on CMOS implemen-

tations the most important bipolar architectures are presented as well. The

examples will show that the di�erences of the bipolar and the MOS device are

highlighted in the S/H circuit design. This leads to very di�erent architectural

solutions in high performance designs.

3.1 Bipolar Architectures

The design of analog integrated circuits has much longer history in the bipolar

than in the MOS technology. Consequently the number of bipolar S/H circuits

reported is too large to be covered in this thesis. Thus only some of the most

important and most recently reported circuits are discussed.

3.1.1 Diode Bridge

Traditionally the high speed S/H circuits implemented in the GaAs technology

employ a diode bridge as the switching element. Since a good quality diode is

often available also in the silicon bipolar technology, the same types of archi-

tectures can be used. Figure 3.1 shows a simpli�ed schematic of a S/H circuit

based on the diode bridge switch. In the tracking mode CLK is high and the

15

V V

I1

2

in out

I

CLKCLK

C

Figure 3.1: Simpli�ed schematic of a S/H based on diode bridge .

current I1 is steered to �ow through the diode bridge. Since the impedance

of a forward biased diode is very low the output voltage on the capacitor C

is almost the same as the input voltage. The circuit is turned into the hold

mode when CLK goes low and CLK goes high steering the bias current past

the bridge. The high impedance of the reverse biased diodes virtually isolates

the output from the input. In a practical circuit at least the output has to be

bu�ered and usually some additional diodes are needed to establish the reverse

bias conditions.

The major disadvantage of the diode bridge S/H is the limited signal swing

when operating with a low supply voltages (3.3 V or less). Also high quality

diodes are not always available in the bipolar technology.

A low voltage S/H circuit employing a single diode as a switch is reported

in [11]. The circuit provides a 1.5 Vpp signal swing with a 3 V supply.

3.1.2 Switched Emitter Follower

The most bipolar S/H circuits in recent publications relay on a switched emitter

follower as a switch and are usually implemented using only NPN transistors.

The architecture was �rst introduced in [12] and its schematic is redrawn in

16

In1 In2Out1Out2

TT H H

CholdCholdC1

C2

Input buffer

Chold

SwitchSwitch Outputbuffer

Outputbuffer

Q1 Q2

Q3 Q4

Q5

Q6Q7

Q8

Q9

Q10

Q11

Q12 Q13

Q15

Q16

Q14

Figure 3.2: S/H architecture using emitter follower switch.

Figure 3.2. The both halves of the di�erential circuit consist of a switch and

an output bu�er. The input is brought to the switches through a di�erential

input bu�er, whose linearity is one of the major concerns in this architecture.

The linearity is improved by adding emitter degeneration resistors in the input

di�erential pair (Q1 and Q2 ) and diodes (Q3 and Q4 ) in series with the load

resistors.

In the track mode the bu�ered input is sampled in the capacitor Chold

through the emitter followerQ5. In transition to the hold mode the bias current

of the emitter follower is turned o� and its base is pulled down. The minimum

size of the sampling capacitor Chold is limited by the droop rate of the held

output. To make the droop smaller the bias current of the �rst emitter follower

(Q8 ) in the output bu�er is turned o� in the hold mode. The droop in the

di�erential output signal is considerably smaller than in the single output since

most of it is in the common mode.

In the hold mode the signal at the output of the input bu�er couples to

the hold capacitor through the parasitic base-emitter capacitor of Q5. The

feedthrough is minimized by connecting a feed-forward capacitor C1 from the

other output of the input bu�er to the hold node. The capacitor is implemented

by employing the base-emitter junction capacitance of a BJT.

While a 120 MS/s sampling rate was achieved in [12] it was increased to

1.2 GS/s in [13] mainly through the use of a more advanced technology. How-

17

ever, the increased speed was paid by decreased linearity (from 10 bits to 8

bits) and increased power consumption (from 40 mW to 460 mW). In [14] the

same authors managed to restore the resolution to 10 bits while maintaining

their previous power consumption. This was achieved by modifying the input

bu�er and adding a droop compensation circuit into the output bu�er. A 10

bit 250 MS/s S/H circuit with di�erent bu�ers and a di�erent hold-feedthrough

cancellation technique is presented in [15]. While all the previous designs re-

quire a 5 V supply in [16] both the input and the output bu�ers are redesigned

to allow operation with a 2.7 V supply voltage.

Another low voltage (3.3 V) architecture is presented in [17]. There the

need for an input bu�er is eliminated by using series type (the term by B.

Razavi) sampling, like in many CMOS architectures. The principle is as fol-

lows. In transition to the hold mode the sampling capacitor is �rst disconnected

from both ends and then turned over. As a result the plate where the signal

voltage was applied in sampling is connected to ground in the hold mode and

inverted signal voltage appears to the other plate now disconnected from the

signal ground. This type of sampling makes the circuit less susceptible to the

hold mode feedthrough, thus allowing to bring the input directly to the base

of the switched emitter follower. The DC-voltage levels inside the circuit are

di�erent in the sample and hold modes which helps to achieve the low voltage

operation. However, due to the series type sampling the linearity of the circuit

is limited by distortion produced by the nonlinear parasitic capacitances. In

the reported circuit the THD measured for a 10 MHz input signal was 60 dBc

at 100 MHz sampling rate. The quasidi�erential (two single ended circuits in

parallel) circuit provides a di�erential signal swing as high as 3 V from a 3.3 V

supply.

3.2 CMOS Architectures

One of the main challenges in the bipolar S/H design is the lack of a good simple

switch. In the CMOS the MOSFET is almost an ideal switch. When operating

in the triode region it can be considered as a voltage controlled resistance. In

addition, the purely capacitive impedance seen from the gate of a MOSFET

allows to store and bu�er sampled charges for a long time period without a

signi�cant droop.

In the bipolar S/H circuits the linearity problems are mainly connected with

18

In

Out

I

M1S1

C

Figure 3.3: A simple S/H circuit employing a source follower bu�er.

the bu�er circuits. However, paying great attention to the bu�er design and

using di�erent linearization techniques, it is possible to make high performance

S/H circuits with open loop bu�ers. In CMOS the lower transconductance of

the MOS device and the body e�ect make the most simple open loop bu�er,

the source follower, much less linear than its bipolar counterpart the emitter

follower.

A well known technique to linearize circuits is to utilize negative feedback.

For example an opamp connected to unity gain feedback makes a very linear

bu�er. The use of feedback does not need to be restricted only to the bu�er.

Enclosing the sampling capacitor in the feedback loop reduces the e�ects of

nonlinear parasitic capacitances and signal dependent charge injection from the

MOS switches. Unfortunately an inevitable consequence of the use of feedback

is the reduced speed.

The tradeo� between the speed and the linearity has caused the researches

to take two di�erent approaches in designing high speed high resolution CMOS

S/H circuits. One is to use an open loop architecture and put an e�ort to

maximize the linearity and the other to employ a closed loop architecture and

maximize the speed.

3.2.1 S/H Circuit with Source Follower Bu�er

The simplest open loop bu�er in CMOS is the source follower. Figure 3.3

shows a simple S/H circuit using the source follower bu�er. Ideally the channel

current of a MOS transistor depends only on the gate�source voltage of the

device. Consequently a MOS transistor biased with a constant current provides

a constant voltage shift from the gate to the source. The circuit has purely

capacitive input impedance and low output impedance, thus it sounds like an

19

In

Out

M1

M2

M3

M4

M5

C

S1S2

S3

Vb1

Vb2

Vcm

Figure 3.4: Simpli�ed schematic of the S/H circuit presented in [18].

ideal solution for bu�ering a charge stored in a capacitor. In the real world

there is two di�erent nonidealities that introduce input voltage dependency into

the gate�source voltage. These are the bulk e�ect, which is the channel current

dependency on the source�bulk voltage, and the �nite output resistance seen

when looking at the drain of the transistor. The output impedance of the current

source employed to bias the source follower has an e�ect as well. The output

impedance is inversely proportional to the channel length of the transistor and

thus it has an increased importance in short channel MOSFETs.

Probably the only way to get rid of the bulk e�ect is to connect the source

and the bulk of the transistor together. This requires that the transistor can

be put in a well of its own, which is possible only for PMOS transistors in

a typical CMOS process using a p-type substrate. The penalty from using a

PMOS transistor is the slower speed compared to a NMOS solution. A S/H

circuit employing a NMOS source follower bu�er implemented in a non-typical

CMOS process is presented in [18]. An implementation using a standard CMOS

process and PMOS source follower is reported in [19]. The S/H circuits from

[18] and [19] are shown in Figures 3.4 and 3.5 respectively.

In Figure 3.4 the e�ect of �nite output resistance of the source follower

transistor M2 is reduced by making its drain�source voltage almost constant

by cascading it with the transistor M1. To keep M2 in saturation its e�ective

threshold voltage is made larger than the threshold voltage of M1 by biasing

its bulk with the diode connected transistor M3. The output impedance of the

bias current source is made large by cascoding the current source transistor M5

with the transistor M4. Due to the �ve stacked transistors the circuit requires

20

R

I

M1M2

C

S1

S2

S3

InOut

Figure 3.5: S/H utilizing a linearized source follower bu�er [19].

a 6 V supply voltage and the signal swing is still limited to 800 mV. The circuit

achieves roughly 60 dBc linearity at 100 MHz clock rate with a 10 MHz signal

frequency.

A lower supply voltage (� 3 V) can be used with the circuit presented in

Figure 3.5. The drain-source voltage of the source follower M1 is bootstrapped

with the circuit consisting ofM2 and R. Although not explained in the reference

the resistor R is used instead of a current source probably in order to minimize

the supply voltage. If a current source was used, connecting the gate of M1

through S1 to ground would cause the current source to drop from saturation

which would slow down the transition to the hold. To keep the current source in

saturation S1 should be connected to a higher potential increasing the required

supply voltage and circuit complexity. The drawback from using the resistor

is the substantially high current �owing through M2. This is due to the fact

that the bias current I determines the minimum voltage on the resistor R which

cannot be very high in order to keepM1 in saturation when its gate is connected

to ground. The current provided by M2 should generate a voltage variation on

the resistor R which is equal to the signal swing. In practice this means that

the average current through M2 during the hold mode can be larger than the

current I. On the other hand R must be much larger than 1=gm2 to make the

drain-source voltage of M1 constant enough. It might be impossible to set

the value of R to satisfy both these and the requirements set by the desired

operating point.

In both the circuits the voltage dependent charge injection from the switch

transistors is avoided by taking the sample by opening the switch S1 slightly

before the input switch S2. Since S1 is connected to a constant potential in both

circuits the charge it injects to the sampling capacitor is constant. Because the

21

capacitor is �oating when S2 is opened its charge injection cannot distort the

sampled voltage. This technique is called the bottom plate sampling and it is

discussed in more detail in Section 4.3.

Although the distortion originating from the charge injection is prevented

a new source of distortion is introduced. Lets consider the basic S/H circuit

with a source follower bu�er in Figure 3.3 and assume that there is a nonlinear

parasitic capacitance from the input of the bu�er to the ground. It is in parallel

with the sampling capacitor and thus the same voltage is sampled into both the

capacitors. There is no charge redistribution in transition to the hold mode,

thus the nonlinear capacitance has no e�ect on the sampled voltage.

Lets now consider either of the circuits in Figure 3.4 or Figure 3.5. In the

sampling mode the input of the bu�er is connected to a constant potential

while the input voltage is applied to the top plate of the sampling capacitor. In

transition to the hold mode the sampling capacitor is turned over by connecting

its top plate to the signal ground. The signal charge is redistributed between

the sampling capacitor and the parasitic capacitor at the bu�er input. Any

nonlinearity in the parasitic capacitance produces harmonic distortion. The

main source of the nonlinear capacitance is the junction capacitance of the

drain-bulk diode of the switch transistor. The capacitive loading e�ect of the

source follower transistor is small since both the gate-source and the gate-drain

voltages are almost constant. To minimize the distortion the sampling switch

should be small and the sampling capacitor large, thus there is a tradeo� between

the speed and the linearity.

3.2.2 S/H Circuit Using Miller Capacitance

In [20] an interesting approach is used to reduce the signal dependent charge

injection. The idea is to use the Miller e�ect to increase the e�ective capacitance

in the hold mode in order to make the voltage step resulting from the charge

injection negligible. The sampling is fast and the switch sizes can be kept small

due to the small physical sampling capacitor value which is not multiplied by the

Miller e�ect in the sampling mode. The proposed circuit is shown in Figure 3.6.

The operation of the circuit is as follows. In the sampling mode both the

switch transistorsM1 and M2 are conducting and thus the opamp is connected

to unity gain feedback. The sampling capacitance is formed of the parallel

combination of the capacitors C1 and C2 both connected to the low output

impedance of the opamp. At the sampling instant the switch transistors M1

22

−

+

C1

C2

M1

M2

x

x1In Out

Clk

A

Figure 3.6: Sample-and-hold circuit using Miller hold capacitance.

and M2 are turned o�. The transistorM2 operates at a constant potential and

thus the charge it injects into C1 does not produce distortion. The transistor

M1, however, injects an input dependent charge into the node x. Now, since

the feedback path around the opamp is broken, the e�ective value of C2 is

multiplied by (A+1), where A is the open loop gain of the opamp. Due to

the increased capacitance the injected charge produces only a negligible voltage

change in the node x.

Since the voltage at the input of the output bu�er is the same before the

sampling and in the hold mode the nonlinear parasitic capacitances do not

distort the signal. The dominating distortion source in this circuit originates

from the fact that the two switches operate simultaneously. The switches are

coupled through the capacitor C1, and thus turning o� M1 introduces some

signal dependence to the charge injected by M2 into the capacitor C1. This

phenomenon is analyzed more thoroughly in the reference.

3.2.3 Charge Domain Gated-gm Sampler

A recent publication [21] proposes a S/H circuit operating in the charge do-

main. The authors present experimental results of a circuit implemented in

a CCD (charge coupled device) process. However, they show by simulations

that comparable results can also be achieved with a state of the art CMOS

23

CLK

Vin+

Vin-

Iout+

Iout-Qref

Pulsedcurrentsource

Charge source Differentialpair

phit

phit

Figure 3.7: Schematic of the charge domain S/H circuit [21] drawn using MOS-FET symbols.

Qout+

Qout-

Figure 3.8: Water reservoir analogy to illustrate the operation of the chargedomain S/H circuit.

technology.

The operation principle of the circuit can be understood with the help of

the Figures 3.7 and 3.8. Figure 3.7, which is replicated from the reference, uses

MOSFET symbols for the CCDs due to the lack of a standard symbol for CCD.

Figure 3.8 represents the same structure using a water reservoir analogy, where

water represents the charge and the elevation the potential.

For each sample a constant reference charge is generated which is modeled

with a pulsed current source in Figure 3.7. This charge is transferred to the

potential well formed by the three leftmost transistor (CCD) pairs. In Figure 3.8

this is analogous to �lling the reservoir with a constant amount of water. The

di�erential input voltage is applied to the gates of the transistors (CCDs) on

the right. The voltages control the potentials in the depleted silicon underneath

24

the transistors. In the analogy of Figure 3.8 this is equivalent to controlling the

heights of the dams forming the right edge of the reservoir.

At the sampling instant the bottom of the reservoir is rapidly pushed up so

that it ends up above the highest possible position of the dams. The water in

the reservoir rushes over the dams to the channels on the right. How the water

is shared between the channels is proportional to the di�erence of the heights

of the dams.

In Figure 3.7 the sampling is done by applying a voltage pedestal phit to

the gates of the devices forming the potential well. The charge in the well

�ows through the di�erential pair to the output of the circuit. The charge is

shared between the positive and the negative output branch in proportion to

the di�erential input voltage. In many cases this S/H circuit does not need an

output bu�er since the output can be connected directly to a SC circuit such

as a pipelined ADC or a ��-modulator.

The presented measurement result show exceptionally good linearity for an

open loop circuit. The SFDR at a 160 MHz clock rate for a 320 MHz, 100 mVpp

signal is 72 dBc. The authors claim to have simulation results which show that

with small modi�cations to the circuit the SFDR will improve almost 20 dB.

Since the circuit has no active components the power consumption is very small.

Some experimental results are needed to con�rm the presented simulation results

indicating that a CMOS implementation will yield similar performance as this

one achieved with a CCD technology.

3.2.4 Switched Transconductance S/H Architecture

A CMOS implementation of a known bipolar S/H architecture (e.g. [22]) is

presented in [23]. The main idea in this architecture is to perform the sampling

by turning o� a MOSFET biased in the saturation region in opposed to the

more common practice to operate the transistor switch in the triode region.

The advantage of biasing the switch in saturation is the fact that then the

transistor channel is pinched o� at the drain end. Consequently the charge

released when the transistor is turned o� is injected to the source of the device,

so it does not distort the sampled signal. However, since the voltage at the drain

of a saturated MOSFET is not strongly de�ned, the switch must be enclosed in

a feedback loop.

A simpli�ed schematic of the architecture is shown in Figure 3.9. The circuit

consists of an opamp, a sampling capacitor and an unity gain output bu�er. The

25

−

+

In

Out

ClkCh

1

Clk

V0

Figure 3.9: A simpli�ed schematic of a S/H circuit using switched transconduc-tance.

input stage of the opamp is represented with an ampli�er symbol and the push-

pull type output stage is drawn with two transistors and a constant voltage

source.

In the sampling mode the feedback loop is closed and the output voltage

as well as the voltage on the sampling capacitor follows the input voltage. The

sampling is done by turning o� the transconductance output stage of the opamp

by shorting the gates of the output transistors to their sources.

In the hold mode the feedback loop is broken and the voltage sampled in

the capacitor is bu�ered by the unity gain bu�er. Due to the feedback in the

sampling mode the linearity of the bu�er and the capacitor are not concerns in

the hold mode. Since the output transistors operate in saturation the distortion

from charge injection is also minimized.

In [23] the authors report 75 dBc SFDR for their pseudo di�erential circuit.

The closed loop architecture limits the sampling rate to 10 kHz.

3.2.5 Closed-Loop S/H Circuit with Resistor Ratio De-

�ned Gain

A closed loop S/H circuit proposed in [24] is shown in Figure 3.10. In the track-

ing mode (the switch closed) the opamp is connected in an inverting feedback

ampli�er con�guration and thus the output voltage of the circuit is�R2=R1 �Vin.

When the switch is opened this voltage is sampled in the hold capacitor CH :

Since the switch is connected to virtual ground it does not introduce a signal de-

26

−

+A

CH

CC

R1

R2

Vin

Vout

Figure 3.10: A S/H circuit, whose gain is determined by resistor ratio.

pendent charge error. The tracking mode bandwidth of the circuit is extended

by adding the capacitor CC in parallel with the resistor R1 to create a zero,

which is used to compensate the pole due to the hold capacitor.

The circuit needs only one clock signal, which makes the implementation

simple. Since the circuit can realize gains other than one it can be used as an

interstage S/H in pipelined ADCs. The circuit can achieve quite a high sampling

rates (50 MS/s in [24] and 150 MS/s with a BiCMOS technology in [25]), but

its track-and-hold nature limits the usable input signal bandwidth far below the

Nyquist frequency. In addition the resistor matching is known to be worse than

capacitor matching in most IC technologies, thus it is preferable to use a circuit

whose gain is determined by a capacitor ratio in applications, where an accurate

gain is needed.

3.2.6 Closed-Loop S/H Circuit with Capacitor Ratio De-

�ned Gain

When a S/H circuit with precise gain (which is generally di�erent from one) is

needed a switched capacitor circuit with a capacitor ratio de�ned gain is the best

solution. Figure 3.11 shows the S/H circuit used in a widely referred pipelined

ADC design [26]. The input voltage is sampled passively in the capacitor(s) C1

and in the hold mode the sampled charge is transferred to the capacitor(s) C2.

The ratio of the held output voltage to the sampled input voltage is de�ned

by C1=C2. During the sample mode the capacitors C2 as well as the opamp's

outputs are reset. The feedback factor of the circuit depends on the capacitor

ratio and thus on the gain. The larger the gain is set, the smaller the feedback

27

−

+

φ φ

φ φ

φ

φφ

φ

φ

φ

φ

C1

C1

C2

C2

Vin+

Vin-

Vout+

Vout-

Figure 3.11: A switched capacitor S/H circuit.

factor becomes, which increases the settling time of the circuit.

A common modi�cation of the circuit of Figure 3.11 achieves faster settling

by a modi�ed sampling con�guration. Instead of resetting the capacitor C2 in

the sample mode it is connected in parallel with C1. Consequently the value of

C1 has to be reduced by the value of C2 to obtain the same gain as with the

original circuit. The reduction of C1 value increases the feedback factor in the

hold mode which in turn speeds up the settling. The improvement is signi�cant

only with small (� 2) gain values.

3.2.7 S/H Circuit without a Reset Phase

The slew rate requirement for a S/H circuit output is set by the di�erence of

successive output levels. Resetting the output of a S/H circuit during the sample

mode makes the requirement often more tight than required by the signal. A

single ended S/H circuit where the output in the sample mode stays in vicinity

of its last hold level is presented in [27]. In [28] the idea is developed a bit

further by extending the length of hold phase to the whole clock period. The

proposed fully di�erential circuit is later employed in [29] (the design is also

reported in [30]).

The circuit from the reference [28] is shown in Figure 3.12. For clarity the

capacitors and switches of only one half circuit are drawn. The sampling is

28

−

+

φ

φ

φ

φ

φ

φ

Vin+

Vout+

Vout-

Vb1

Vb2

C1

C2

C3

Figure 3.12: A half circuit of a fully di�erential S/H circuit without a resetphase.

performed passively with the capacitor C1 the same way as done in Figure 2.9.

During sampling the capacitor C3 is connected between Vout� and the bias

voltage Vb2 which is also the opamp input common mode level. In transition

to the hold mode the sampling capacitor C1 is connected in parallel with C2

and the bottom terminal of C3 is switched to the opamp's negative input. Since

the voltages on capacitors C2 and C3 are complementary they cancel each other

when the capacitors are connected in series con�guration at the beginning of

the hold mode. This naturally requires the capacitor to be equal sized.

The cancellation performs the reset of the hold capacitor C2 thus no sep-

arate reset phase is needed. At the end of the hold mode the capacitor C1 is

disconnected from the feedback loop, but the output voltage remains held by

the capacitor C2. Thus the holding phase is e�ectively extended to overlap

with the next sampling period. This, however, does not alleviate the settling

requirement, since the output must be fully settled before C1 is disconnected.

Due to the lack of reset phase and the large feedback factor the circuit

achieves high sampling rates. A 100 MS/s sampling rate with about 9-bit reso-

lution is achieved in [29].

29

Chapter 4

Sampling with a MOS

Transistor Switch

Usually when used as a switch a MOS transistor is operated in the triode region

(or linear region). Then the equivalent circuit for the transistor is a resistor

whose value is controlled by the transistor gate voltage. When the switch is

closed the value of the on-resistance is in the range from few tens of ohms to

few kilo-ohms. In contrast the resistance of an open switch is so high that in

practice the switch is an open circuit.

In addition to the �nite on-resistance there is also parasitic capacitances

associated with a MOS switch. This is illustrated in Figure 4.1, where a sim-

ple MOS sampling circuit is shown on the left and its equivalent RC circuit

including the parasitics on the right. The capacitances Cp1 and Cp2 are due

Cs

Vin

Cs

Vin

VCLK

RCLK

C1 C2

Cp1 Cp2

RON

Figure 4.1: MOS sampling circuit and its RC equivalent.

30

Vin

Vsmpl

nT (n+1)T

VON

VOFF

slope a

∆tn ∆tn+1

Figure 4.2: Finite slope of the sampling signal V smpl results in an input voltagedependent sampling delay �t. For simplicity the transistor threshold voltage isassumed to be zero.

to the transistor drain and source junction capacitances and the channel-to-

bulk capacitance. The gate-to-source and gate-to-drain overlap capacitances

and gate-to-channel capacitances are represented with the capacitors C1 and

C2. The resistor RCLK models the output impedance of the clock driver. In

the sampling circuit of Figure 4.1 the value of RCLK plays an important role in

the hold mode feedthrough in the high frequency applications, since it together

with C1 and C2 forms a high pass coupling path past RON .

4.1 Voltage Dependent Turn-O� Moment

A MOS switch like the one in Figure 4.1 turns o� when its gate-source voltage

becomes less than the transistor threshold voltage. (This is not completely true,

but used here for simplicity). When the switch is on the source voltage equals

the input voltage. Due to this and the �nite turn-o� slope a of the gate voltage

the delay �t from the moment when the gate voltage starts to fall to the switch

turn-o� moment depends on the input voltage. This is illustrated in Figure 4.2.

The following analysis shows how the voltage dependent delay is re�ected to

the sampled voltage Vout: Making an assumption that the input voltage change

during �t is small an expression for it can be written as

�t 'VON � Vin(nT )

a=VON �A sin(!nT )

a; (4.1)

31

where the last form is obtained assuming a sinusoidal input. The output wave-

form can be approximated by

Vout(nT ) = Vin(nT +�t) ' Vin(nT ) +dVindnT

�t: (4.2)

For a sinusoidal input this is

Vout(nT ) ' A sin(!nT ) +A! cos(!nT ) [VON �A sin(!nT )]

a: (4.3)

Expanding the last term yields

Vout(nT ) = A sin(!nT ) +A!VON

acos(!nT )�

A2! sin(2!nT )

2a: (4.4)

From this it is clearly seen that the input voltage dependent turn-o� moment

results in a harmonic distortion. For example in a circuit where the clock ampli-

tude is 3 V, signal amplitude 0.75 V, sampling rate 100 MHz, signal frequency

50 MHz and the clock fall time 0.1 ns, the level of the resulted second harmonic

is as high as �48 dBc.

There is basically three ways to get around this problem. First making

the slope of the clock waveform steep reduces the distortion. A second more

complicated solution is to make the switch control voltage to track the input

signal [31]. The best solution, however, is to use a circuit topology where the

switch is operated around a constant voltage. This is discussed in more detailed

later in this chapter.

The bulk e�ect was ignored in this discussion. In practice it makes the tran-

sistor threshold voltage signal dependent which is another source of distortion.

4.2 Charge Injection

A conducting MOS switch has a �nite amount of mobile charge in its channel.

When the transistor is turned o� this charge is distributed between the source,

drain and bulk terminals of the device. To design accurate SC circuits the nature

of this charge injection and redistribution phenomenon must be understood.

Through the years the charge injection has been analyzed and discussed in

various papers e.g. [32], [33], [34] and [35].

Consider the circuit in Figure 4.3. There a sampling capacitor is driven by

the voltage source Vin with the source resistance R through a NMOS switch

32

C1 C2Vin

V1 V2

VG

R

Figure 4.3: A circuit model for understanding the charge injection in MOSswitches.

transistor. The capacitances C1 and C2 are associated with the source and

drain terminals of the transistor; C2 including the sampling capacitor. The

distribution of the charge is dependent on the ratio of C1 and C2 as well as the

source resistance R and the waveform of the switch control voltage VG. The

total amount of the channel inversion layer charge is dependent on the voltage

Vin.

The amount of the released charge Qtot can be expressed [35] as

Qtot = CG(VGON � VT ); (4.5)

where CG is the total gate channel capacitance, VGON the transistor gate voltage

in the on-state and VT the e�ective threshold voltage. A �rst order approxima-

tion is that CG is not dependent on the input voltage and VT has a linear input

voltage dependency through the bulk e�ect. In that case the amount of released

charge is linearly dependent on the input voltage, which is experimentally ver-

i�ed in [32] and [33]. To model the charge more accurately the nonlinear bulk

e�ect and voltage dependency of CG have to be taken into account.

As the transistor is turned o� a part of the inversion layer charge is leaked

to the substrate. This phenomenon called charge pumping is due to two e�ects:

capture of charge by the interface traps and recombination in the channel and

the substrate. It is shown in [35] that the substrate leakage occurs only when

the gate voltage turn-o� slope is extremely steep or the transistor channel is

very long, thus in practical switches this e�ect can be ignored.

The remaining question is how the inversion layer charge is distributed be-

tween the drain and the source terminals when the switch is turned o�. This

can be analyzed by using the circuit in Figure 4.4 to model the distributed gate

33

CG

CovCov

C1 C2

g

V1 V2

VG

Figure 4.4: A circuit model for distributed gate-channel capacitance.

VON

VOFF

slope a

Figure 4.5: The gate voltage turn-o� waveform.

C1 C2∆V2

g[VG(t)]

aCG

2aCG

2

Figure 4.6: A simpli�ed MOS switch model for charge injection analysis.

34

capacitance and assuming the gate voltage having a waveform shown in Fig-

ure 4.5 [35]. When the switch is conducting the gate voltage has a value VGONand as the switch is turned o� the voltage is switched to VGOFF with the slope

a. Using this the channel conductance g can be written

g[VG(t)] = �(VG(t)� VT ) = �(VGON � at� VT ); (4.6)

where � = (W=L)�COX . Now the transistor channel during the turn-o� can

be modeled with a time varying conductance g. The injected charge is modeled

with current sources having a value of aCG=2 in parallel with the capacitors C1

and C2 as shown in Figure 4.6. The analysis of this circuit yields a di�erential

equationdV

cT= (T �B)

��1 +

C2

C1

�V + 2T

C2

C1

�� 1; (4.7)

where the normalized factors are

V =�V2

CG2

qa

�C2

(4.8)

T =tqC2

a�

(4.9)

B = (VGON � VT )

r�

aC2(4.10)

Solving the equation (4.7) numerically gives the diagram shown in Figure 4.7.

There the quantity �Q2=Qtot is expressed as function of parameter B. The

family of curves represent the solutions with di�erent C1=C2 ratios. On the

small values of B the total charge is equipartitioned between the two capacitors

regardless of the capacitor ratio. On the other hand when B is large the charge

is partitioned according to the capacitor ratio. The intermediate B values result

a partitioning somewhere between the extreme cases.

Since the parameter B is dependent on the turn o� time through the slope a,

the meaning of the result can be understood as follows. When the transistor is

turned o� rapidly the channel is cut o� before the potential di�erence between

drain and source has time to even out and as a result the channel charge is

equally divided between the drain and source terminals. On the contrary a

slow turn o� leaves time for the drain and source voltages to get equalized,

35

Figure 4.7: Charge partitioning as function of B [6].

which results into a charge partitioning according to the capacitor ratio. In this

analysis the source resistance R is assumed in�nite. A more complete study

with �nite R values is performed in [34] showing that the smaller the source

impedance is the smaller part of the injected charge ends up in the capacitor

C2.

In practical circuits the slope of the gate voltage is usually in the region

where the charge partitioning is dependent on the slope and the capacitor values.

Consequently the amount of injected charge is not well controlled and due to

this, di�erent strategies are used and proposed to overcome the problem. First

the capacitor C1 in parallel with the driving voltage source and the parameter

B can be made large so that the injected charge returns to the driving circuit.

This, however, increases the capacitive load and makes the circuit slow. Another

strategy is to make the capacitors equal to make the charge injection equal as

well. The same can be achieved by making the parameter B much smaller than

1. In the latter two cases the charge injection can be canceled by using a half

sized dummy switch as illustrated in Figure 4.8.

The �rst order approximation of the amount of injected charge (4.5) indicates

that the charge is linearly dependent on the input voltage. In the S/H circuit

of Figure 4.1 this only a�ects the gain of the circuit which is usually not very

harmful. In practice the charge injection has also a nonlinear component which

results in harmonic distortion. Even the linear component alone can cause

distortion in some types of SC circuits e.g. by changing the interstage gain in

pipelined ADCs.

36

W W/2

CS

Vin

CLK CLK

Figure 4.8: Canceling the charge injection with a dummy switch.

When simulating SC circuits in SPICE the designer should be aware that

the charge injection is not completely modeled in all MOS models. Especially

when the slope of the gate voltage is very steep the quasi static transient model

gives incorrect results [36]. In more recent models like BSIM3v3 a more accurate

charge injection modeling is achieved by employing a non-quasi static model.

4.3 Bottom Plate Sampling

The discussion in the previous sections has shown that both the signal dependent

charge injection and the signal dependent turn-o� moment originate from the

fact that the switch transistor sees the input voltage in its source terminal. If

the switch was operated around a �xed voltage the error from both phenomena

would be constant. A constant error is less harmless in many applications and

it is possible to be reduced with a di�erential circuit topology.

In many closed loop S/H architectures the sampling switch is connected to

a virtual ground to avoid the signal dependent errors. An example is shown

in Figure 4.9. The feedback loop includes two opamps which inevitable slows

down the circuit. By using more than one switch the sampling against constant

potential can be achieved without enclosing the switch in the feedback loop.

This well known technique [37] called bottom plate sampling or series sampling

is illustrated in Figure 4.10. The capacitor C is the sampling capacitor and the

capacitor CL is a parallel combination of the input capacitance of the preced-

ing circuitry and the parasitic capacitances associated with switch S2 and the

sampling capacitor.

The idea goes as follows. In the sampling mode the switches S1 and S2 are

conducting while the switch S3 is open and thus the input voltage is sampled

in the capacitor C. At the sampling instant the signal �0 goes down opening

37

−

+

−

+

Vin Vout

CH

φ

Figure 4.9: An example of a closed loop architecture where the sampling switchoperates against a �xed voltage.

Vin

Cφ

φ′φ φ

φ′

φCL

S1S2S3

Out

Figure 4.10: Bottom plate sampling.

S2, which leaves the node Out �oating. Since the switch S2 is always connected

to the ground the charge it injects into the node Out is constant. Slightly later

the capacitor C is disconnected from the input by opening the switch S1. The

charge injection and the input voltage variation during the time gap between

opening S2 and S1 distorts the voltage on C. This, however, is not dangerous

since the sampled signal is in the form of charge at the node Out. This charge

cannot change after S2 is opened because there is no other DC-path from that

node. The sampling is completed by connecting the left hand side terminal of

the capacitor C to the ground by closing the switch S3.

In the hold mode the signal can be taken out from node Out either as a

voltage or as a charge. If Out is connected to a high impedance its voltage is

just an inversion of the sampled input voltage. In practice the load capacitance

CL causes some attenuation and if it is not linear � distortion. Alternatively

the node Out can be connected to a virtual ground which allows to handle the

sample in form of charge.

38

4.4 Nonlinear time constant

In the sampling mode the circuit in Figure 4.1 forms a low pass �lter. Due

to this the maximum frequency that the circuit can track is limited. The 3dB

frequency of the circuit is

f3dB =1

2�RON (Cs + Cp2 + C2); (4.11)

where the clock driver output impedance RCLK is assumed to be zero. In

most circuits operating in the sub gigahertz range the attenuation due to the

�ltering should be easily suppressed below the required level. However, with

large amplitude input signals problems occur already in the frequency range

from tens to couple of hundreds of MHz. This is due to the fact that the time

constant is not constant, but has an input voltage dependency through the

voltage dependent on-resistance and the voltage dependent stray capacitances.

The distortion analysis follows the one we presented in [3]. An assumption

is made that although the frequencies of interest are su�ciently high, they are

always much below the 3dB frequencies related to the RC time constants of the

equivalent circuit. Utilizing this the voltage on the sampling capacitor can be

expressed as

VCs � (1� j!RON (Cs + Cptot))Vin = (1� j!�)Vin; (4.12)

where RON is the switch on-resistance, Cs the sampling capacitor and Cptot the

parasitic capacitance in parallel with Cs. The magnitude of the voltage can be

approximated to be

jVCsj � (1�!2�2

2) � jVinj : (4.13)

If � is assumed constant, an absolute amplitude accuracy of N bits requires

� <1

2(N�1)=2!, f3dB > 2(N�1)=2f; (4.14)

where f3dB is the 3 dB frequency of the sampling circuit and f the frequency

of the input signal. The time constant � is a product of the on-resistance of the

switch and the total capacitance in the sampling node. In a real circuit, they are

both functions of the voltage VCs, which is almost equal to the input voltage.

Thus the polynomial approximation for the time constant can be written as

39

� = �0 + �1Vin + �2V2in + �3V

3in + ::: (4.15)

Substituting this in (4.12) results

VCs = (1� j!�0)Vin � j!�1V2in � j!�2V

3in � j!�3V

4in � ::: (4.16)

This indicates that a time constant linearly dependent on the input voltage

produces second harmonic or in more general odd order voltage dependence

on the time constant produces even order distortion and vice versa. Since the

higher order error components in (4.16) have a di�erent frequency than the

fundamental, the requirement for the absolute accuracy is more strict than

(4.14). In balanced circuits the even order distortion is considerably attenuated

and usually it is not a problem. Thus if the voltage dependent component of the

time constant cannot be suppressed enough to achieve the absolute accuracy,

its shape must be made as linear as possible to avoid the odd order distortion.

4.4.1 Distortion in CMOS and NMOS Switches: Compar-

ison

In CMOS the switch can be implemented with a single NMOS or a single PMOS

transistor. The NMOS switch o�ers a low on-resistance when operated near

the negative supply voltage but the closer to the positive supply the operation

point is set the less conductive the switch becomes. Eventually it is cut o�

one transistor threshold voltage below the supply. The operation of the PMOS

switch is just the opposite: near the positive supply the switch on-resistance is

low increasing towards the negative supply. A CMOS switch (or a transmission

gate) is a parallel combination of an NMOS and a PMOS transistor. It o�ers

a �nite on-resistance in the whole voltage range between the supplies. Another

possibility to achieve the same is to control the single transistor switch with

a voltage greater in magnitude than the supply voltage. The implementation

of this boost voltage, however, increases the circuit complexity. Figure 4.11

illustrates the voltage dependence of the switch on-conductance (inverse of the

on-resistance). For a NMOS switch with two di�erent gate voltages it is shown

on the left and for a CMOS switch on the right.

The trend towards lower supply voltages while trying to maintain the volt-

age swing have made the implementation of satisfactory switch for high signal

frequencies more and more di�cult. The time constant of the sampling circuit

40

VSS VDD

Desiredsignal rangeGon

NMOS

Vgs=3V

Vgs=4V

VSS VDD

Desiredsignal rangeGon

CMOS

Vgs=±3V

Switch on−conductance

Figure 4.11: Switch on-conductance versus signal level.

consisting of the switch and a sampling capacitor is hard to make small enough

to provide the absolute accuracy. A comparison based on simulations between

the distortion characteristics the CMOS switch and the NMOS switch controlled

with a voltage higher than the positive supply is presented next.

Figures 4.12 and 4.13 show the simulated on-resistances and the total sam-

pling capacitances of CMOS and NMOS switches as a function of the input

DC-voltage. The time constant in Figure 4.14 is obtained by multiplying the re-

sistance and the capacitance. The simulations are performed using the BSIM3v3

models for an 0.5 �m CMOS process. The used supply voltage is 3 V, the sam-

pling capacitor 0.5 pF, the channel length of the transistors is 0.5 �m and the

channel width 25 �m for NMOS and 75 �m for PMOS. A 4.5 V gate voltage is

used for the NMOS switch while the gates of NMOS and PMOS transistors of

the CMOS switch are connected to the supply voltage and ground, respectively.

From the capacitance and resistance curves for the circuit using the CMOS

switch one can identify three regions: near the supplies only one transistor is

conducting while in the middle both the transistors conduct. The capacitance

is formed of three components: the capacitance of the sampling capacitor, the

junction capacitances and the capacitances from the transistor channel to the

bulk and the gate. The last component vanishes when the transistor turns o�

causing the pedestal seen in the CMOS curve. Due to the higher control voltage

used with the NMOS switch this strong nonlinearity is not seen. Below the half

supply voltage the time constant of the NMOS switch is almost linear, indicat-

ing that according to (4.16) the distortion is mainly of the second order and

strongly attenuated in the balanced circuits.

41

0 1 2 3DC-VOLTAGE

80

100

120

140

160

180

200

RESISTANCE

Figure 4.12: On-resistance of a sampling switch as a function of input voltage.The solid line represents the CMOS-switch and the dashed line the NMOS-switch.

0 1 2 3DC-VOLTAGE

600f

700f

CAPACITANCE

Figure 4.13: Total sampling capacitance consisting of 0.5 pF sampling capacitorand parasitic capacitance. The solid line represents the CMOS-switch and thedashed line the NMOS-switch.

42

0 1 2 3DC-VOLTAGE

60p

80p

100p

120p

140p

TIME CONSTANT

Figure 4.14: Time constant of the sampling circuit. The solid line represents acircuit using the CMOS-switch and the dashed line a circuit using the NMOS-switch.

In Figure 4.15 the second and the third order harmonic distortions are cal-

culated from the transient simulations. The results are presented as a function

of the PMOS transistor size with three di�erent transistor parameters. The

input signal is a 100 MHz sine wave with a 1.0 Vpp amplitude. In the upper

plots the DC-level is 1.5 V and in the lower ones 1.0 V. As predicted earlier the

NMOS switch, in general, produces less third order distortion than the CMOS

switch. However, the optimum sizing of the transistors of the CMOS switch

can suppress the third harmonic to a very low level as seen in the plot (d).

Unfortunately this minimum is quite narrow and its location depends on the

parameter variations as well as the temperature and the supply voltage.

The above issues suggest that in order to minimize the odd order distortion

the DC-level of the input signal should be low. A single NMOS transistor con-

trolled with a voltage higher than the supply as a switch gives lower distortion

than the parallel connected complementary transistors. If for some other reason

the CMOS switch is used, a proper ratio of the transistor sizes can be found

to minimize the distortion. Lowering the time constant by increasing the tran-

sistor widths is not very e�ective, since even if the on-resistance decreases, the

parasitic capacitance increases.

43

1 2 3 4 5−90

−80

−70

−60

−50

−40

SECOND HARMONIC

dBc

Wp/Wn(a)1 2 3 4 5

−90

−80

−70

−60

−50

−40

THIRD HARMONIC

dBc

Wp/Wn(b)

1 2 3 4 5−90

−80

−70

−60

−50

−40

SECOND HARMONIC

dBc

Wp/Wn(c)1 2 3 4 5

−90

−80

−70

−60

−50

−40

THIRD HARMONIC

dBc

Wp/Wn(d)

Figure 4.15: The levels of the second and the third harmonic versus the PMOStransistor size. The supply voltage is 3.0 V and the signal amplitude 1.0 Vpp.The DC level is 1.5 V in �gures (a) and (b) and 1.0 V in �gures (c) and (d). Sim-ulations using nominal transistor parameters, parameters with fast NMOS andslow PMOS and parameters with fast PMOS and slow NMOS are presented withthe solid, dotted and dashed lines respectively. The horizontal lines representsimulations made for the NMOS-switch and curved lines for the CMOS-switch.

44

VCLK

VDD

Switch

C1

M1

M2

M3

Figure 4.16: A MOS switch with local gate voltage boost circuit.

4.4.2 Lowering Switch On-Resistance with Gate Voltage

Boosting

Although the boosted NMOS switch has good distortion characteristics, the

required boost voltage is a tradeo�. Usually an extra supply voltage outside the

chip is too high a price to pay. Fortunately it is possible to generate the voltage

on chip. A charge pump circuit can be used to power the clock generator or the

clock generator can be driven from the normal power supply while applying the

boost directly to the switches.

A switch with a local charge pump circuit is shown in Figure 4.16 [38]. There

the capacitor C1 is charged to VDD � Vth when the VCLK is high. At the same

time the gate of the switch transistor is hold in the ground by the transistor

M3. When the clock goes down C1 boosts the gate of the switch transistor to

2VDD � Vth. In practice the voltage is somewhat lower due to the parasitic

capacitances.

Another local charge pump circuit is shown in Figure 4.17 [39], [40]. In the

previous circuit the capacitor precharging is done through the diode connected

NMOS transistorM1. This diode switch limits the precharge voltage to VDD �

Vth. In Figure 4.17 the capacitor (now C2) is precharged through a NMOS switch

M2. The capacitor can be charged to VDD since the gate of M2 is controlled

with a boosted voltage generated withM1 and C1 [41]. The well bias for PMOS

transistor M3 is produced with another charge pump.

In the deep submicron IC technologies there is reliability problems with the

voltage boosting circuits discussed so far. To avoid violating the technology

45

VCLK

VDD

VhighSwitch

C1 C2

M1 M2

M3

M4

Figure 4.17: Another local boost circuit for a MOS switch.

VDD

Vin

Figure 4.18: A switch controlled with input tracking gate voltage.

reliability speci�cations the transistor gate�source (or gate�drain) voltage may

not exceed the maximum allowed supply voltage. Taking into account this

condition the switch boosting can still be realized by making the gate voltage to

track the source voltage with an o�set of VDD . This is illustrated in Figure 4.18,

where an open switch with the gate voltage Vin + VDD is shown.

A practical implementation of the input tracking boosting is shown in Fig-

ure 4.19 [42]. There the o�set voltage is realized with the capacitor C3, which

is precharged to V DD during the main switch o� period. To turn on the switch

M11 the precharged capacitor is connected between its source and gate via the

series switches M8 and M9. Turning o� M11 is done by disconnecting the ca-

pacitor C3 and pulling down the gate with M10. The transistor M7 is needed

to prevent the gate�source voltage of M10 to exceed VDD .

A slightly modi�ed version of this circuit is presented in [43]. There the

NMOS transistor M3 is replaced with a PMOS transistor whose gate is tied to

the gate of M11. Consequently the charge pump on the left in Figure 4.19 can

be eliminated.

Prior these circuits the signal dependent gate voltage boosting is utilized

46

VDD

Switch

C1 C2

M1 M2 M3 M4

Vin

C3 M5

M7M8

M9

M10

M11

M12φ

φ

φ

φ

Figure 4.19: A long term reliable switch boosting circuit.

to avoid the signal dependent turn o� moment [31] and to reduce the signal

dependent on-resistance, the parasitic capacitances and the charge feedthrough

[44].

In addition to the increased circuit complexity and possible reliability prob-

lems the use of the boosted voltage may increase the switching noise on the

substrate. Consequently in low frequency applications or when the low distor-

tion is not essential it is preferable to use the CMOS switch.

4.5 Sampling Function

In the previous discussion the e�ect of the �nite on-resistance of a MOS switch

was modeled with a limited bandwidth in the tracking mode. The same thing

can also be thought in a di�erent way. Due to the low-pass �ltering e�ect the

voltage on the sampling capacitor not only depends on the instant value of the

input voltage but also on its previous values. When a sample is taken it is

a weighted average of the input values from the beginning of the time to the

sampling moment. In practice only a short time period has to be taken into

account. The weighting can be modeled with the sampling function and the

averaging with integration as done in the equation (2.5).

In a real circuit the resistance of the MOS switch cannot be changed from

its constant on-value (the nonlinear e�ects are neglected in this discussion) in

the tracking mode to in�nite in a zero time. This is due to the �nite slope of

the transistor gate voltage and the gate voltage feedthrough to the source and

47

drain via the parasitic capacitances. Since there is no single time instant which

can be said to be the sampling moment the sampling must be modeled with the

sampling function.

A through analysis of the NMOS transistor sampling function based both on

analytic formulation and simulations is presented in [45]. The authors de�ne the

aperture time as the time interval which covers 80% of the sampling function

area. Their analysis shows that for very small sampling capacitor values the

aperture time has almost linear dependence on the gate voltage fall time. On

the other hand when the sampling capacitor is large the sampling function is

dominated by the tracking mode time constant, which is typically the case in

S/H circuits. Sub-samplers and digital high speed line receivers are applications

where the bandwidth reduction due to the �nite turn-o� time is remarkable.

48

Chapter 5

Double-Sampling

The clock rate of the switched capacitor circuits is limited by the bandwidth

of the employed opamp, thus in order to achieve a high speed it is essential to

exploit the opamp e�ectively. This chapter introduces a technique to double the

sampling rate of the switched capacitor circuits without a need to increase the

speed of the opamp. This technique called double-sampling was �rst introduced

in [46]. It has been applied in various SC circuits like �lters, ��-modulators

(i.e. [47][48]), pipelined ADCs ([49]) and as a part of this thesis in S/H circuits

([1]�[3]). Just recently another double-sampled S/H circuit was presented in

[50].

−

+

Vin

Voutφ

φ φ

φ

Ci

Cs

Figure 5.1: A switched capacitor integrator.

49

−

+

Vin

Voutφ

φ φ

φ

Ci

φ

φ

φ

Cs1

Cs2

φ

Figure 5.2: A double-sampled SC integrator.

5.1 Principle

A SC circuit can be divided in blocks each containing an opamp and a set

of switches and capacitors. The SC integrator shown in Figure 5.1 can be

used as an example block. The integrator operates in two phases: In the �rst

phase the circuit samples its input, which is usually the output of some other

block, on the capacitor Cs. The second phase can be called integration phase or

ampli�cation phase. During it the circuit performs a charge transfer from the

sampling capacitor to the integration capacitor Ci with the aid of the virtual

ground provided by the opamp.

Since the output of the circuit has to fully settle by the end of the integration

phase it can be sampled by the following circuit block during the integration.

If this is done the opamp is not needed in the sampling phase. Sometimes the

sampling phase is used to autozero the ampli�er i.e. to cancel its input o�set

voltage, but this is not necessary in many applications. Another possibility to

exploit the opamps idle phase is to duplicate the sampling circuitry and operate

the two sampling circuits in opposite clock phases. This way the opamp and

the integration capacitance are shared between the two sampling circuits. The

sampling rate of the resulted double-sampled circuit shown in Figure 5.2 is twice

that of the original circuit. There is, however, only a minor increase in the power

consumption, since it is dominated by the opamp.

The double-sampling can also be applied to the S/H circuit of Figure 2.9

resulting the circuit shown in Figure 5.3. During the �rst clock phase the

input is sampled in the capacitor Cs1 and the capacitor CS2 is connected in

the feedback loop around the ampli�er. In the next clock phase the roles of the

50

−

+Vin

Vout

φ

φ

φ

φ

φ Cs1

Cs2

φ

φ

φ

n1

n2

Figure 5.3: A double-sampled S/H circuit.

capacitors are changed Cs1 being in the hold mode and Cs2 in the sample mode.

5.2 Nonidealities

The double-sampling introduces some nonidealities not present in the conven-

tional SC circuits. Most of them arise from the mismatch between the two

parallel circuits and are basically similar to the nonidealities in parallel ADCs,

which have been analyzed e.g. in [30]. A general analysis concerning the timing

of parallel sampling systems is given in [51]. The nonidealities in the double-

sampled SC �lters have been investigated in [52], however, all the results are not

directly applicable to the double-sampled S/H circuits. Thus in the following

sections the nonidealities of the double-sampled circuits are analyzed taking an

approach better suited for S/H circuits and ADCs.

5.2.1 Memory e�ect

Due to the �nite gain of the opamp a fraction of the previous sample remains

stored in the parasitic capacitance in the input of the ampli�er [53], [48]. Using

51

T 3T 5T0 2T 4T t

x(4T)x(2T)x(0)

T 3T 5T0 2T 4T

x(T) x(3T) x(5T)

t

ε ε ε

Figure 5.4: Time domain representation of a double-sampled signal in presenceof channel o�set.

the z-transform the voltage gain of the circuit in Figure 5.3 can be written

VoutVin

=1

1 + 1A

�Cs+Cp1+Cp2

Cs

��

Cp1ACs

z�1; (5.1)

where A is the DC-gain of the opamp, Cs the sampling capacitor, Cp1 the

opamp input capacitance and Cp2 the parasitic capacitance at the node n1.

The denominator of the equation contains the same error terms due to the �nite

opamp gain as the equation for the circuit of Figure 2.9 and in addition a term

containing z�1. The equation indicates that the double-sampling together with

the �nite opamp gain and the parasitic capacitances adds a low-pass �ltering

e�ect. In the worst case (at the Nyquist frequency) the additional error is equal

to the error due to the opamp input capacitance in the conventional circuit.

5.2.2 O�set

A static DC o�set between the two signal paths can be considered as a constant

value added to every other sample. In time domain this can be written as

y(t) =

1Xn=�1

x(t) � �(t� nT ) +

1Xn=�1

" � �(t� n2T � T ); (5.2)

where " is the magnitude of the o�set and �(t) the Dirac's delta function. The

time domain signal is illustrated in Figure 5.4.

The frequency domain presentation can be obtained with the Fourier trans-

52

f0 fS-fS

0 fS-fSf

0 fS-fSf

Figure 5.5: Frequency domain representation of a double-sampled signal in pres-ence of channel o�set.

form, which results

Y (f) =

1Xn=�1

X(f) � �(f �n

T)�

1Xn=�1

(�1)n" � �(f �n

2T): (5.3)

The equivalent magnitude spectrum is shown in Figure 5.5, where fS = 1=T

represents the clock frequency of the whole system i.e. it is twice the clock

frequency of the individual sampling circuits. The obtained result indicates that

the o�set between the two parallel signal paths results in tones at multiples of

fS=2.

In practice the channel o�set is not very likely a problem in the double-

sampled circuits unlike in the parallel ADCs, since the opamp is common for

both the signal paths.

53

T 3T 5T0 2T 4T t

x(4T)x(2T)x(0)

T 3T 5T0 2T 4T

x(T) x(3T) x(5T)

t

1 1 11-α 1-α 1-α

Figure 5.6: Time domain presentation of a double-sampled signal in presence ofgain mismatch.

5.2.3 Gain Error

If there is a gain mismatch between the parallel circuits the sample sequences

they produce have di�erent amplitudes. In time domain this can be written as

y(t) = 1 �

1Xn=�1

x(t) � �(t� n2T )

+(1� �) �

1Xn=�1

x(t) � �(t� n2T � T ) (5.4)

=

1Xn=�1

x(t) � �(t� nT )

�

1X

n=�1

�(t� nT )� � �

1Xn=�1

�(t� n2T � T )

!; (5.5)

where � is the normalized gain mismatch. Figure 5.6 shows that the gain mis-

match in the time domain is equivalent to multiplying the ideal sample sequence

by a sequence of two alternating constant impulses.

In the frequency domain the multiplication corresponds to the convolution

54

f0 fS-fS

0 fS-fSf

0 fS-fSf

Figure 5.7: Frequency domain representation of a double sampled signal inpresence of gain mismatch.

and thus the Fourier transform gives

Y (f) =

1Xn=�1

X(f �n

T)� � �

1Xn=�1

(�1)n �X(f �n

2T): (5.6)

This is illustrated in Figure 5.7, which reveals that the consequence of the gain

mismatch is the parasitic sidebands around the multiples of fS=2. If the signal

bandwidth exceeds fS=4 the sidebands alias to the signal band degrading the

signal-to-noise ratio. Even if the spectrums do not overlap �ltering is needed to

remove them.

The gain mismatch originating from the capacitor mismatch is a severe prob-

lem in some double-sampled circuits. For example in the ��-modulators the

mismatch down converts the shaped noise energy around fS=2 to the baseband

[47]. However, in the S/H circuit of Figure 5.3 the gain is always one and

independent of capacitor ratios, thus the gain mismatch is not a problem.

5.2.4 Timing Skew

There can be a constant timing skew in the clock signals of the two parallel cir-

cuits. This is illustrated in Figures 5.8 (a) and (b), where the sample sequences

55

taken by each circuit are shown. There is a constant timing error �T in the

sequence y02(t) and thus the sequences can be written

y01(t) =

1Xn=�1

x(t) � �(t� n2T ) (5.7)

=1

2T

1Xn=�1

x(t) � ejn2�t2T (5.8)

y02(t) =

1Xn=�1

x(t) � �(t� n2T � T ��T ) (5.9)

=1

2T

1Xn=�1

x(t) � ejn2�(t�T��T)

2T : (5.10)

The output of the circuit y0(t) is the sum of y01 and y02. In practical circuits

it is held between the samples. If the subsequent signal processing is done in

the discrete time domain, the held y0(t) is resampled resulting in a sequence of

uniformly spaced samples shown in Figure 5.8 (d). This sequence can be written

as

y(t) =

1Xn=�1

x(t) � �(t� 2nT )

+

1Xn=�1

x(t+�T ) � �(t� 2nT � T ) (5.11)

=1

2T

1Xn=�1

x(t) � ejn2�t

2T

+1

2T

1Xn=�1

x(t+�T ) � ejn2�(t� T )

2T: (5.12)

The resampling thus corrects the sample misalignment but retains the incorrect

sample values.

The frequency domain representation for the �rst sample sequence y1(t) =

y01(t) (the sequence without the prime denotes the signal after the resampling)

is

Y1(f) =1

2T

1Xn=�1

X(f �n

2T) (5.13)

56

x(0) x(2T) x(4T)

x(T+∆T) x(3T+∆T) x(5T+∆T) x(7T+∆T)

x(6T)

T

0 2T

3T

4T

5T

6T

7T0 2T 4T 6T

t

t

t

t

T 3T 5T 7T0 2T 4T 6T

T 5T 7T

x(3T+∆T) x(5T+∆T) x(7T+∆T)x(T+∆T) x(6T)x(4T)x(2T)x(0)

x(3T+∆T) x(5T+∆T) x(7T+∆T)x(T+∆T) x(6T)x(4T)x(2T)x(0)

(a)

(b)

(c)

(d)

3T

y1’(t)

y2’(t)

y’(t)

y(t)

Figure 5.8: Time domain representation of a double-sampled signal in presenceof timing skew.

57

and for the second resampled signal

Y2(f) = F

(1

2T

1Xn=�1

x(t+�T ) � ejn2�(t+�T )

2T � ejn2�(T+�T)

2T

): (5.14)

Using the time shift theorem the Fourier transform in (5.14) yields

Y2(f) =1

2T

1Xn=�1

X(f �n

2T) � ej2�f�T � e�

jn2�(T+�T)2T : (5.15)

The output signal is sum of Y1 and Y2 thus

Y (f) =1

2T

1Xn=�1

X(f �n

2T) �h1 + e�jn� � ej2��T (f�n=2T )

i: (5.16)

These equations can be understood with the help of Figure 5.9. There the

magnitude and the phase of the signal spectra are represented in three dimen-

sions � the phase in the polar coordinates and the frequency axis in perpen-

dicular to the phase plane. To ease the drawing the base band signal spectrums

are represented as groups of impulses. The uppermost spectrum is Y1(f), which

is the input signal sampled at rate of fS=2 and thus the baseband spectrum re-

peats in fS=2 intervals. The spectrum in the middle is Y2(f) which, again, is the

input signal sampled at fS=2. The sampling moment, however, is ideally shifted

by half a clock period compared to y1(y). The half period time domain shift

causes the phase of the spectral images at odd multiple of fS=2 to be rotated

180 degrees. The samples, however, do not represent the input signal values at

nT + T=2, but a time �T later. This rotates the edges of the spectral images

in phase plane.

Due to this bending the sum of these two spectrums (the bottom sequence)

has some remains of the spectral images at odd multiples of fS=2, which would

ideally (�T = 0) be canceled out. If the bandwidth of the input signal is greater

than fS=4 these remains alias in the signal band. The wider the bandwidth is the

larger is the error signal, since the phase rotation is proportional to the frequency

o�set from the center of the image. Considering the time domain signal this

sounds reasonable, since the input signal change between the ideal and the actual

sampling moment (i.e. the error) gets larger as the input frequency increases.

When the input is a sinusoidal signal (frequency f) the error is a tone at the

frequency fS=2 � f . In Figure 5.10 the magnitude of this tone is plotted as a

58

fS

0

-fS

f

f

f

-fS

0

fS

-fS

0

fS

phase

Figure 5.9: Frequency domain representation of a double-sampled signal in pres-ence of timing skew.

59

10−4

10−3

10−2

10−1

100

00.1

0.20.3

0.40.5

−100

−80

−60

−40

−20

0

∆Τ/Τf/fs

Mag

[dB

]

Figure 5.10: The magnitude of the error the image as a function of the relativetiming error �T=T and the relative input frequency f=fS.

function of the relative input frequency and the relative timing error. When the

magnitude of the error image is small compared to the fundamental it can be

approximated with 20 log(j��T (f � 1=2T )j) dBc, which is obtained from 5.16

using the small angle approximation.

The sources of the timing error are the device mismatches in the clock gener-

ation circuit and the uneven clock line capacitances. If the clock signals for the

parallel circuits are generated using both rising and falling edges of an external

half speed clock, the deviation of its duty cycle from 50% is seen as the timing

error. These errors can be minimized but not totally eliminated by a careful

layout design and by using a full speed external clock.

The previous analysis treated non-uniformly sampled signal, whose samples

were realigned uniformly by the subsequent signal processing, which is not nor-

mally done for the output signal of a SC �lter. In the time domain this signal can

be expressed with the sum of equations (5.8) and (5.10). Its Fourier transform

yields the following equation for the spectrum:

Y 0(f) =1

2T

1Xn=�1

X(f �n

2T) �h1 + e�jn� � ejn2��T=T

i; (5.17)

60

−

+Vin

Vout

φφ

φ Cs1

Cs2

φ

φ

φ

φ

φ

φS

S0

S1

S2

S3

S4

S5

S6

S7

S8

n0

Figure 5.11: Proposed timing skew insensitive double-sampled S/H circuit.

φ

φ

φS

T

Figure 5.12: Timing of the skew insensitive S/H circuit.

where the main di�erence to the equation (5.16) is that the error is not signal

frequency dependent. The output of a real double-sampled SC �lter is (5.17)

weighted by the sinc function due to the hold operation.

5.3 Proposed Skew Insensitive Circuit

To overcome the timing skew problem we developed a modi�cation which makes

the double-sampled circuits insensitive to the timing errors [4]. There the idea is

to perform the sampling with a single switch rather than two parallel switches.

In Figure 5.11 the technique is applied in the double-sampled S/H circuit.

The sampling is done by the switch S0 clocked with the signal �S (Fig-

ure 5.12). The switches S1 and S2 act as a multiplexer that shares the common

61

sampling switch to the parallel circuits. When the half circuit with the sampling

capacitor Cs1 is in tracking mode the switches S0, S1 and S3 are on and the

switches S5 and S7 o�. The sample is taken by applying a short zero pulse to

switch S0, during which the switch S1 is turned o� followed by the S3 turn-o�.

Next the switches S5 and S7 are closed connecting the capacitor Cs1 in the

feedback loop around the ampli�er.

The gap between turning o� S0 and S1 must be quite short, since the voltage

at the �oating node n0 changes along with the input voltage. The voltage change

causes a part of the sampled signal charge to be distributed to the parasitic

capacitance in that node. When the switch S1 is turned o� the charge in n0 is

isolated distorting the total sampled charge. In addition to making the timing

gap small also minimizing the parasitic capacitance in n0 helps to diminish this

error source.

62

Chapter 6

Dynamic Measuring of S/H

Circuits

The target application of a S/H circuit has a large impact on measuring the

circuit. If the S/H circuit is designed to be used with an ADC integrated on the

same chip, no capability to a drive 50 external load is needed. This, however,

prevents the straightforward full speed measurements. On the other hand in

the ADC applications only the instantaneous value of the S/H circuit output

at the end of the hold phase is of interest. Consequently the continuous time

measurements may give too pessimistic results.

The easiest way to get rid of these problems is to characterize the S/H

circuit together with the ADC. Then it, however, may be di�cult to make the

di�erence between the properties of the ADC and the S/H circuit. The 50

driving capability can be obtained with an on-chip bu�er, yet its implementation

is often even more demanding than the design of the S/H circuit itself. So the

designer can very easily end up into a situation where he is measuring the output

bu�er rather than the S/H circuit.

A commonly used way to characterize the S/H circuits is to use the beat

frequency test [6]. There two S/H circuits are integrated on the same chip

and one is used to measure the other. The measurement setup we used to

characterize the implemented circuits is shown in Figure 6.1. There the output

of the �rst S/H circuit (the one on the left) is sub-sampled with the second

circuit, whose clock signal is obtained by dividing the clock of the �rst circuit

(CLK) with an on-chip divider by some integer N . Now, if the input signal

63

N

N={2,3,4,5,6,7,8}

f in

CLK

out1f out2f

CLK/N

SH SHSignalGenerator

SpectrumAnalyser

ClockSource

0 CLKCLK/N 2CLK/N

f out1

2f out1

Figure 6.1: Measurement setup for beat frequency test.

frequency is within a small o�set �f from the clock frequency of the second

circuit (CLK=N) the signal is aliased to a low frequency �f . In a similar

manner the possible harmonics in the �rst circuit output get aliased to the

frequencies 2�f , 3�f , 4�f , and so on as illustrated in the inset of Figure 6.1.

The beat frequency test provides with a way to investigate the distortion

characteristics (THD and SFDR) of the S/H circuit at high signal frequencies

without a need to bring high frequency signals out from the chip. The second

S/H circuit does not even need to drive a 50 input impedance of the measure-

ment equipment or a baluun, since the low frequency signal can be handled with

an active di�erential-to-single-ended converter constructed of discrete opamps.

Since the second S/H circuit samples the fully settled output of the �rst

one, the measurement setups simulates the actual operation environment in a

front of an ADC on the same chip. Although the output of the second circuit

is measured as continuous time, the introduced error is insigni�cant due to the

fact that the di�erence between the concurrent sample values is very small. Also

the sinc attenuation resulted from the hold operation can be ignored at the low

frequencies.

64

Chapter 7

Prototype Design and

Experimental Results

The goal of this design is to develop a high speed CMOS S/H circuit for parallel

ADCs. An example of a parallel ADC with a front-end S/H circuit is shown in

Figure 7.1. The primary function of the S/H circuit in this application is to relax

the requirement for the accuracy of the timing of the parallel converters. It also

helps to improve the dynamic performance by taking away from the converter

the need to handle a continuous time signal.

The target speci�cations for this design were set as follows: a 10-bit resolu-

tion, a sampling rate higher than 100 MS/s, a 2 Vpp di�erential signal swing

from a 3.0 volt supply and a reasonable power consumption. Two prototypes

have been designed using a 0.5 �m CMOS process with poly-poly capacitors

MUX

ADC

ADC

ADC

ADC

fclk

/4fclk

SH /4fclk

/4fclk

/4fclk

inV outD

Figure 7.1: A parallel ADC with a front-end S/H circuit.

65

and three metal layers. The second circuit is designed to realize the new ideas

and overcome the problems encountered during the design and measurements

of the �rst prototype.

7.1 1st circuit

The design of the �rst prototype circuit is described in the following sections.

First the architecture and the employed circuit blocks are described in detail

followed by presentation of the simulation and measurement results.

7.1.1 Architecture

The architecture of the prototype is shown in Figure 7.2. It is a fully di�eren-

tial version of the double-sampled S/H circuit in Figure 5.3. The di�erential

structure is almost a necessity in the mixed signal environment of ADCs, where

the amount of substrate noise and other disturbances is considerable.

To reduce the noise coupling to the high impedance input of the opamp and

to minimize the input capacitance all the capacitors are laid out in such a way

that their bottom plates are connected to the opamp output. This is due to the

fact that there is a parasitic capacitance from the capacitor bottom plate to the

noisy substrate. For poly-poly capacitors this parasitic capacitance is roughly

10 % of the capacitor value. Fortunately it is often possible to place a well under

the capacitors which signi�cantly reduces the substrate noise coupling.

The signal common mode levels at the input and the output of the circuit

need not to be the same; neither the common mode levels at the input and the

output of the opamp. This can be utilized to adjust the level of the continuous

time input signal in the region where the distortion due to the nonlinear switch

on-resistance is minimized. In the case of the NMOS switches the input signal

level should be as small as possible. There is, however, two reasons which set

a lower limit for the input signal common mode level. First, the negative peak

voltage cannot extend much below V ss in order to prevent the pn-junctions in

the drain and the source of the MOS switch to become forward biased. On

the other hand, if the S/H circuit is driven without DC decoupling the driving

circuit probably cannot provide a signal swing that ranges very near V ss. The

signal levels used in this design are shown in Figure 7.3.

The o�set between the opamp input and output common mode levels in the

hold mode is the same as the di�erence between the input signal common mode

66

Vin+

Vin−

Vout+

Vout−

C1

2C

3C

4C

φ1

φ 2

3φ4φ

φ1’

3φ ’

φ1’

3φ ’

φ1

φ 2

φ 2

φ 2

3φ4φ

4φ

4φS1

S2

S3

S4

S5

S6

S7

S8

S1

S2

S3

S4

S5

S6

S7

S8

Figure 7.2: The designed fully di�erential double-sampled S/H circuit.

67

1.0

2.0

3.0

0

Sampling Hold

opamp input

inpu

t sw

ing

outp

ut s

win

g

input cm

output cm

gnd

[V]

Vss

Vdd

Figure 7.3: Signal ranges and common mode levels in the circuit.

φ1

φ2

3φ

4φ

φ1’

3φ ’

Hold #1Sample #2

Sample #1Hold #2

Sample #1Hold #2

Figure 7.4: Timing diagram for the circuit of Figure 7.2.

voltage and the sampling ground. The maximum tolerable o�set is strongly

dependent on the type of the opamp. From the sampling switch point of view it

is preferable to make the sampling ground voltage as low as possible to reduce

the switch size. For the maximum signal swing and minimum distortion the

output common mode level is set in the half way between the supply voltages.

The architecture employs bottom plate sampling technique to avoid the sig-

nal dependent charge injection from the MOS switches. The applied timing of

the clock signals is shown in Figure 7.4.

68

Vhigh

Vhigh

Vhigh

Vhigh

CLK

CLK

φ1′

φ1=φ4

φ2=φ3

φ3′

Figure 7.5: Clock generator.

7.1.2 Switches

The switches throughout the design are implemented with NMOS transistors.

The distortion due to the nonlinear switch time constant was suppressed below

the target level by controlling the switches with a voltage higher than the 3 volt

supply. This voltage is not generated on the chip but instead an external voltage

source is used to be able to study the dependence of the distortion characteristics

on the voltage value.

Although the bottom plate sampling minimizes the signal dependent charge

injection the signal independent common mode voltage step due to the injected

charge and the clock feed-through can still be a problem, since it may cause the

common mode level in the opamp input to exceed the valid range. By making

the switches S1 and S2 equal in size the problem can be minimized. This is

due to the fact that the switches operate is opposite clock phases and thus the

charges they inject cancel each other.

7.1.3 Clock Generator

Figure 7.5 shows the clock generator designed to produce the clock signals of

Figure 7.4. The input for the circuit is a complementary half speed clock signal

obtained by dividing the full speed clock by two with a divider constructed of

a di�erential D-�ip�op [54] (not shown). This commonly used clock generator

69

relies on cross coupled OR-gates in producing the non-overlapping clock phases.

The non-overlap time is equal to the combined delay of the OR gate and the

three following inverters. The boxed inverters are the switch drivers with the

higher external supply voltage.

7.1.4 Opamp

The speed of the S/H circuit is mainly determined by the slew rate and the

bandwidth of the opamp. The DC-gain and the opamp input capacitance set

the precision of the fully settled hold mode output voltage.

If the opamp input capacitance is neglected the error in the S/H circuit

output voltage according to (5.1) is Vin=A, where A is the DC-gain. To suppress

this error below the 10-bit target level the opamp DC-gain has to be greater than

60.2 dB. Taking into account the parasitic capacitance at the opamp input sets

the gain requirement some decibels higher. In some types of opamps the Miller

e�ect may result in a very large e�ective input capacitance. As far as the DC-

gain (and the Miller capacitance) is linear the only consequence of inadequate

gain is signal attenuation, which is tolerable in most cases.

The output settling time depends on the opamp GBW and the feedback

factor. An expression for the minimum GBW for an OTA type ampli�er is

derived in Appendix A. If the OTA input capacitance is assumed zero the GBW

required for 10-bit accuracy at 200 MHz clock rate is 220 MHz. When one third

of the clock period (a good rule of thumb) is reserved for slewing and the input

capacitance is taken into account the minimum GBW requirement must almost

be doubled. The non-dominant poles and the zeros of the OTA and the zeros due

to the switch on-resistances degrade the phase margin in the open loop frequency

response. If only the lowest non-dominant pole is considered, a 61 degree phase

margin at the gain of 1=f (f=feedback factor) gives the fastest settling. Due

to the other poles and zeroes the optimal value is typically somewhat higher.

The slewing makes the settling a nonlinear phenomenon thus the settling time

cannot be compromised if a good SFDR is needed.

The opamp [39] employed in the S/H circuit is shown in Figure 7.6. It has

two stages: a low gain wide band input stage and a high gain cascode output

stage. The all NMOS signal path o�ers potentially high speed. The main

purpose of the �rst stage is to adjust the signal level suitable for the gain stage

and provide some common mode input voltage range. In addition it produces

few decibels of voltage gain which is determined by gm1=gm3 (the bulk e�ect is

70

Vin+ Vin-Vout+ Vout-

M1 M2

M3 M4

M5M6 M7

M8 M9

M10 M11

M12 M13cmfb

Vcp

Vcn

Vp

Vn

Vp

Vcp

Vcn

Figure 7.6: Two stage fully-di�erential high-speed opamp.

ignored). The total DC-gain of the ampli�er is:

A0 =gm1gm6

gm3

�gds12gds10gm10

+ gds6gds8gm8

� : (7.1)

Since the only high impedance node is at the output, the dominant pole is

determined by the output impedance of the ampli�er and the load capacitance

and thus the GBW of the ampli�er can be written:

GBW =gm1gm6

gm3CL; (7.2)

where CL is the total load capacitance. There is also two non-dominant poles in

su�ciently high frequencies. One is associated with the �rst stage output and

it is proportional to gm3=Cp1, where Cp1 is the parasitic capacitance at that

node. The other pole associated with the cascode node in the signal path is

proportional to gm8=Cp2, where Cp2 is the parasitic capacitance at the cascode

node. The stability is assured by keeping the gain of the �rst stage low i.e.

making the gm3 high. Due to the two non-dominant poles the phase margin has

to be designed somewhat larger than when there is only one non-dominant pole.

Since the opamp is fully di�erential it requires a common mode feedback

(CMFB) circuit. In the SC circuits the best way to implement it is to use

71

4φφ 2

Vout+ Vout−

cmfb

V1

V2

φ 24φ

4φ φ 2

Vout+ Vout−

cmfb

V1

V2 φ 2 4φ

4φ φ 2 φ 2 4φ

Figure 7.7: The double-sampled CMFB circuit.

switched capacitors. The circuit is shown in Figure 7.7. Due to the double-

sampling scheme two parallel CMFB circuits operating in opposite clock phases

are needed. The identical circuits consist of two capacitors that form a capacitive

divider between the di�erential outputs of the opamp. This divider provides the

output common mode voltage which is fed back to the gates of the opamp input

stage load devices. During the half of the clock period, when the circuit is not

active, the nominal o�set voltage is restored in the capacitors by connecting

them between the two voltages that correspond to the nominal output CM level

(V 2) and the nominal bias voltage of the load devices (V 1).

The simulated opamp frequency response is presented in Figure 7.8. It shows

a 450 MHz GBW and 62 degree phase margin at the unity gain frequency and

about 70 degree at the target feedback con�guration. The DC-gain simulated

with the nominal transistor parameters is 62 dB.

7.1.5 Simulations

The operation of the circuit is veri�ed and the performance is estimated by

long transient simulations. Figure 7.9 shows a part of the output waveform at

130 MS/s sampling rate. The FFT spectrum calculated from the same simula-

tion is presented in Figure 7.10. It predicts 75 dBc SFDR for an input signal

72

Figure 7.8: Simulated opamp frequency response.

73

Figure 7.9: Transient waveform at 130 MS/s sampling rate.

whose frequency is one third of the clock frequency and the di�erential am-

plitude of 3 Vpp. For a 2 Vpp signal with a frequency of 1/3 times fS the

simulations show almost as good SFDR at the 200 MS/s sampling rate.

7.1.6 Experimental Results

The circuit was fabricated with a 0.5 �m double-poly triple-metal CMOS pro-

cess. A photograph of the prototype chip containing two S/H circuits and a

programmable divider is shown in Figure 7.11.

The circuit is characterized with the beat frequency test with several sub-

sampling ratios. As an example a sub-sampled spectrum of a 73.3 MHz, 1.75 Vpp

signal, which is sampled at 220 MS/s, is shown in Figure 7.12. The SFDR is

set by the third harmonic which in this case is at the 65.6 dBc level.

In addition to the signal and its harmonics there is an extra spurious fre-

quency at the 25 kHz o�set from the signal peak. It is not generated by the S/H

circuit under test. The same spur (and also a number of its multiples) is seen in

the spectrum of the signal generator which is used as a clock source. It probably

originates from the leakage of the PLL reference in the signal generator.

The SFDR is measured as a function of the signal amplitude at 130 and

220 MS/s sampling rates. The results are shown in Figures 7.13 and 7.14 re-

spectively. There are two curves in both the �gures: a solid curve for a 200 kHz

input signal and a dashed curve for a input signal whose frequency is from a

small o�set of one third of the clock frequency. The results show that the circuit

operates well on both clock rates. As expected the SFDR decreases as the signal

74

0 1 2 3 4 5 6

x 107

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

POWER SPECTRUM

FREQUENCY (Hz)

RE

LAT

IVE

PO

WE

R (

dBc)

Figure 7.10: FFT spectrum calculated from the simulation of Figure 7.9.

Figure 7.11: A chip photo of the �rst prototype.

75

Figure 7.12: Spectrum of a 73.3 MHz @ 1.75 Vpp signal sampled at 220 MS/s.The aliased signal is seen at 33.3 kHz frequency and its harmonics at multiples ofthat frequency. The spur at 25 kHz o�set from the signal peak is not originatedin the S/H circuit.

76

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 340

45

50

55

60

65

70

75

Vpp [V]

SF

DR

[dB

c]

SFDR vs. input level

200 kHz

43.3 MHz

Clock rate: 130 MS/s

Figure 7.13: SFDR as a function of the signal amplitude at 130 MS/s samplingrate.

amplitude is increased. The SFDR is not as good as simulations predict, but it

is still excellent when the reference is the other reported high speed CMOS S/H

circuits. At 220 MS/s the 10-bit resolution is achieved with a 1.8 Vpp signal

from DC up to one third of the clock frequency.

Limitations in the measurement equipment prevented from testing the circuit

at clock rates higher than 220 MS/s. It was neither possible to measure the

circuit with the fS=2 input signal at 220 MS/s due to lack of proper �lter to

remove the harmonics from the test signal. However, at 130 MS/s the SFDR

was even slightly better with the fS=2 than with the fS=3 input signal, which

may be due to the fact that with the fS=2 input frequency the voltage on the

sampling capacitors is almost unchanged between the samples.

An interesting study is the e�ect of the switch control voltage on the SFDR.

The measurement results with a 73.3 MHz signal at 220 MS/s sampling rate

are shown in Figure 7.15. The SFDR dependence on the control voltage is

almost linear from 3.2 V to 4.4 V. Increasing the voltage above 4.5 V does

not give any improvement which indicates that the distortion from the other

sources start to dominate at that level. The 4.5 V control voltage results in a

77

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 340

45

50

55

60

65

70

75

Vpp [V]

SF

DR

[dB

c]

SFDR vs. input level

Clock rate: 220 MS/s

200 kHz

73.3 MHz

Figure 7.14: SFDR as function of signal amplitude at 220 MS/s sampling rate.

4 V maximum switch transistor gate�drain voltage which is a couple of hundred

millivolts larger than the maximum long term reliable value. A better reliability

could have been achieved with a signal dependent gate voltage boosting.

The measurements with odd sub-sampling ratios revealed that there is a

spurious tone at fS=2�f . Most likely it originates from the timing skew between

the parallel circuits. In the worst case, when the input signal frequency is from

a small o�set of the Nyquist frequency, the level of the spur is �61 dBc which

corresponds to a 2.6 ps timing skew.

The power consumption of the circuit without the clock generator was mea-

sured to be 25 mW at the 220 MS/s sampling rate with a 1=3 � fS , 1.75 Vpp

input signal. The performance of the circuit is summarized in Table 7.1.

7.2 2nd circuit

In order to avoid the timing skew problem another version of the S/H circuit

employing the skew insensitive switching proposed in Section 5.3 was designed

and tested.

78

3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 535

40

45

50

55

60

65SFDR vs. switch control voltage (fclk 220MHz, fs 73.3 MHz)

SF

DR

[dB

c]

Voltage [V]

Figure 7.15: SFDR of a 73.3 MHz signal sampled at 220 MS/s rate as functionof the switch control voltage .

Sampling rate 220 MS/sSFDR 65 dBcDi�erential input swing 1.8 VppSupply voltage 3.0 VPower consumption 25 mWActive area 0.06 mm2

Technology 0.5 �m CMOS

Table 7.1: Measured performance.

79

Vhigh

Vhigh

Vhigh

Vhigh

CLK

φ1′

φ1=φ4

φ2=φ3

φ3′

DELAY

D Q

QD

DELAY

Vhigh

φS

Figure 7.16: Clock generator for the second S/H circuit.

7.2.1 Architecture

The architecture of the circuit is a fully di�erential version of the timing skew

insensitive circuit in Figure 5.11. The building blocks except the clock generator

(opamp, switches, CMFB, etc.) are from the �rst prototype.

7.2.2 Clock Generator

The new clock generator is shown in Figure 7.16. The circuit generating the

non-overlapping signals is basically the same as used in the �rst S/H circuit.

The short pulses for the common sampling switch are generated with the circuit

consisting of an inverter, a delay element and a NAND gate. The D-�ip�op

generates the complementary half speed clock signals.

7.2.3 Simulations

The e�ect of the timing skew on the �rst and the second S/H circuit is compared

by adding an intentional timing skew in the clock signals. As expected this has

no e�ect on the skew insensitive circuit. The FFT spectrums for both circuits

calculated from transient simulations with a 10 ps skew are shown in Figure 7.17.

The clock frequency in the simulations is 220 MS/s and the signal frequency one

third of that. An error image with a 53 dBc magnitude is seen at the 38 MHz

frequency in the output of the �rst circuit. This is exactly as predicted by the

theory. There is no sign of this image in the spectrum of the skew insensitive

circuit. Except the image the two spectrums are almost identical which indicates

80

0 1 2 3 4 5 6 7 8 9 10

x 107

−100

−80

−60

−40

−20

0

FREQUENCY (Hz)

dBc

0 1 2 3 4 5 6 7 8 9 10

x 107

−100

−80

−60

−40

−20

0

FREQUENCY (Hz)dB

c

Figure 7.17: The e�ect of a 10 ps timing skew on the spectrum of the �rst(upper plot) and the second (lower plot) prototype circuit.

that the new switching scheme does not degrade the circuit performance.

7.2.4 Experimental Results

The test chip was fabricated with the same 0.5 �m CMOS process as the �rst

chip. A photograph of the chip is shown in Figure 7.18. It turned out that

an unfortunate mistake was made in the beat frequency test setup design. The

same programmable divider that was used with the �rst prototype was applied

without any modi�cations. The new clock generator, however, now included a

frequency division by two and as a result the second S/H circuit on the chip

could be clocked only with the rates fs=4, fS=6, fS=8, etc. The odd sub-

sampling ratios would have been needed to investigate the spectrum image due

to the timing skew. This is not possible with the even ratios since then the

image aliases at the top of the fundamental signal.

Although the obvious fact that the tone due to the timing skew is eliminated

could not be veri�ed the circuit performance was measured with the available

sub-sampling ratios. The results show that the performance is almost identical

to the �rst prototype. This proves that the timing skew insensitive switching

does not degrade other circuit characteristics. A spectrum where a 1.8 Vpp,

81

Figure 7.18: Chip photo of the second prototype.

82

Figure 7.19: Spectrum of the timing skew insensitive S/H circuit. The spectrumis measured at 220 MS/s sampling rate with a 1.8 Vpp input signal having afrequency which is a small o�set from fS=4. The spurs close to the carrier arepart of the spectrum of the used clock source.

fS=4 signal is sampled at 220 MS/s is shown in Figure 7.19. Again, the spurs at

the 25 kHz o�set from the fundamental are due to a poor quality clock source.

83

Chapter 8

Conclusions and Future Work

For comparison some of the state of the art high-speed S/H circuits are collected

in two tables. The division between the tables is made based on the type of

the switch transistor (BJT or MOSFET) thus BiCMOS designs can be found

in both the tables.

The comparison of the sampling rates shows that the realized circuit(s) has

higher sampling rate than any other CMOS design and it is even faster than most

of the bipolar realizations. The sampling rate alone is not enough to determine

the speed of the circuits. Many circuits with a high sampling rate experience a

severe performance loss when the input frequency is increased. Thus the signal

band is included in the table to determine the signal frequency corresponding

to the SFDR �gure. Again the realized circuit performs well even though the

given 75 MHz �gure is probably underestimated.

Since the resolution (around 10 bits) is used as the common factor for the

circuits chosen for this comparison, the SFDR in all the circuits is about the

same. On the other hand the largest and the smallest signal swing di�er by a

factor of 30 which suggests a 30 dB di�erence in SNR! The 1.8 Vpp signal swing

of the realized circuit is one of the best.

There is no clear connection between the supply voltage and the circuit

performance except in the last circuit of the CMOS table where the extremely

low supply voltage is probably the reason for the modest performance. Most

of the architectures does not allow supply voltage scaling thus only the ones

with a supply voltage three volts or less are potentially compatible with todays

technologies.

The power consumption of the realized circuit is moderate compared to the

84

Circuit [11] [12] [14] [16] [17]Type diode

switchswitchedemitterfollower

switchedemitterfollower

switchedemitterfollower

switchedemitterfollower

Sampling rate 200 MS/s 120 MS/s 1 GS/s 300 MS/s 100 MS/sSignal band 10/50MHz 60 MHz 500 MS/s 10/50MHz 10/50MHz

SFDR 65/40 dBc 62 dBc 62 dBc 65/72 dBc 60/53 dBc

Signal swing 1.5 V 1 V 1 V 0.5 V 3 VSupply voltage 3 V 5 V 5.2 V 2.7 V 3 VPower consump-tion

15 mW 40 mW 490 mW 32 mW 10 mW

Technology 20GHzBiCMOS

3GHzbipolar

25GHzbipolar

18GHzBiCMOS

12GHzbipolar

Table 8.1: Published high-speed bipolar S/H circuits.

Circuit this work [18] [25] [21] [29],[30] [50]Type SC,

double-sampled

openloop,sf-bu�er

resistorratiofeedback

chargedomain

SC, non-resetting

SC,double-sampled

Samplingrate

220 MS/s 100 MS/s 150 MS/s 160 MS/s 95 MS/s 40 MS/s

Signalband

75 MHz 10 MHz 10 MHz 320 MHz 50 MHz 1/5 MHz

SFDR 65 dBc 61 dBc 52 dBc 72 dBc >60 dBc 40/55 dBcSignalswing

1.8 V 1.4 V 1 V 0.1 V 2 V 0.6 V

Supplyvoltage

3 V 6 V 3 V - 5 V 1.2 V

Power con-sumption

25 mW 18 mW 5.4 mW 1.6 mW 140 mW 0.6 mW

Technology 0.5�mCMOS

0.8�mCMOS

0.7�mBiCMOS

0.5�mCCD

1�mCMOS

0.5�mCMOS

Table 8.2: Published high-speed CMOS S/H circuits.

85

other circuits, which is can be regarded acceptable.

As a conclusion for the comparison it can be said that the circuit in whole

de�nitely belongs to the state of the art. It has taken the sampling rate of

the CMOS S/H circuits beyond 200 MS/s still achieving the highest resolution

among the pure CMOS reference designs.

In the near future the circuit will be utilized in a 10-bit parallel pipelined

ADC. For that purpose the switch control voltage, which has been supplied

externally, has to be generated on-chip. Probably the best way to do this is

to use the signal dependent gate voltage boosting. Another circuit block that

deserves further investigations is the clock generator. To guarantee a correct

operation with di�erent process parameters and in di�erent temperatures the

nominal non-overlapping time of the clock phases has to be made quite long

and thus it consumes a signi�cant portion of the clock period. Some increase in

the sampling rate can be achieved by using a clock generator with process and

temperature independent non-overlapping times. Utilizing a delay locked loop

(DLL) is one possible way to implement it.

86

Appendix A

Derivation of OTA GBW

Requirement

The small signal model for the S/H circuit in the hold mode is shown in Fig-

ure 8.1 where the OTA is represented with a single pole model consisting of gm,

go and CL. The capacitance CL is the sum of the OTA output capacitance and

the external load capacitance. The capacitance at the OTA input is represented

with Ci and the output conductance with go.

This circuit is used to �nd out the settling time constant using a pulsed

current source ii as the excitation signal. The small signal analysis yields the

following transfer function:

voii

= �gm � sC

s [(gmC + goCi + goC) + s(CiCL + CLC + CCi)]: (8.1)

Using this, the output voltage for a current impulse with total the integrated

go

C

CLCiii

voutvin

gmvin

Figure 8.1: Small signal model for the S/H circuit in the hold mode.

87

charge Q can be written (in partial fraction form):

vo =gmQ

s(gmC + goCi + goC)�

CCiCL+CLC+CCi

+ gmgmC+goCi+goC

gmC+goCi+goCCiCL+CLC+CCi

+ sQ: (8.2)

The corresponding time domain expression is obtained with the inverse Laplace

transform giving

v0 =Q

C + gogmCi +

gogmC�

�1� e

�gmC+goCi+goC

CiCL+CLC+CCit

�

�CQ

CiCL + CLC + CCi� e�

gmC+goCi+goC

CiCL+CLC+CCit; (8.3)

from where the settling time constant can be identi�ed as

� =CiCL + CLC + CCigmC + goCi + goC

: (8.4)

Since gm is large compared to go the time constant can be approximated as

� �CiCL + CLC + CCi

gmC: (8.5)

The well known relation states that the gain-bandwidth product of a single

pole OTA is:

GBW =gm

2�CL: (8.6)

Substituting this to (8.5) yields

� =1

2�GBW�

�1 +

Ci(CL + C)

CCL

�: (8.7)

When the last term due to the feed-forward path is ignored in (8.3), the settling

to N -bit accuracy in the time period T requires

e�T� < 2�N ; (8.8)

which leads to the following requirement for the GBW :

GBW >N ln 2 �

�1 + Ci(CL+C)

CCL

�2�T

: (8.9)

The GBW can also be expressed in terms of the feedback factor f = C=(C+Ci)

88

and the e�ective load capacitance CLtot = CL + CCi=(C + Ci) [55] resulting

GBW >N ln 2CLtot2�TfCL

: (8.10)

89

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