Conference paper On-Chip ESD Protection with Improved High

Holding Current SCR (HHISCR) Achieving IEC 8kV Contact System Level  EOS/ESD symposium 2010 

 For the design of on‐chip ESD clamps against system level ESD stress three main  challenges  exist:  reach  a  high  failure  current,  ensure  latch‐up immunity  and  limit  transient  overshoots.  Bearing  these  in  mind,  high system  level ESD requirements should be within reach. A novel  improved high  holding  current  SCR  is  introduced  fulfilling  all  three  requirements within drastically reduced silicon area.   

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On-Chip ESD ProtCurrent SCR (HH

Sorgeloos Bart, Sofics (formerly known a

phone: ++32-9-21-68This

Abstract – For the design of on-chip Ereach a high failure current, ensure lahigh system level ESD requirements introduced fulfilling all three requireme

I. IntroductionSystem level ESD robustness is impothe reliability for any product. ExteESD protection devices are widelyindustry, but for some innovatapplications there is a trend inducedfactor and operational performance toboard level devices and replace theprotection and thus connect I/O pinsharsh outside world. The on-chip ESD up to increase its failure current whichissues with traditional ESD solutionsleakage, increased load capacitance larger die area. Therefore, IC descustom ESD protection structures wiperformance but within a small silimaintaining the desired IC specificatio

Figure 1: Schematic representation of the cowith local protection between the Rx-input and

tection with Improved HighHISCR) Achieving IEC 8kV

System Level

Backers Ilse, Marichal Olivier, Keppens Bas Sarnoff Europe), Brugse Baan 188A, B-8470 Gistel, Be8-333; fax: +32-9-3-746-846; e-mail: bsorgeloos@sofics.copaper is co-copyrighted by Sofics and the ESD Association

Sofics BVBA BTW BE 0472.687.037 RPR Oostende

ESD clamps against system level ESD stress three match-up immunity and limit transient overshoots. Bshould be within reach. A novel improved high hoents within drastically reduced silicon area.

n ortant to ensure ernal (off-chip) y used in the tive consumer d by cost, form o remove these em by on-chip directly to the clamp is scaled

h leads to many s: increased pad

and especially signers request ith a high ESD con area while

ons.

ommunication chip VSS

This paper presents a case studyproduct where dedicated on-chiprotection is placed at the Rxtransmitter operates in an open dr

II. System Level ESTo fulfil system level ESD requESD pulse shape and test setup IEC 61000-4-2 standard [12], mar

1. High ESD current levels30 ns (According to leve

2. A fast ESD current peakrise time of 0.7ns-1ns.

3. The test must be doperation under powerfunctional component in

Figure 2: The current waveform as defin

h Holding V Contact

art elgium, om

main challenges exist: earing these in mind,

olding current SCR is

y of a communication ip system level ESD x and Tx pins. The rain configuration.

SD approach uirements, the applied

must conform to the rked by: s: 16A current peak at el 4 protection).

k value: 30A within a

done during normal red condition of the nside the system.

ned in the IEC standard

3A.1-1 EOS/ESD SYMPOSIUM 10-167

These standard system level test translate into 3 basic rules that an alevel ESD clamp must comply to:

1. Achieve high ESD current leve

2. Limit voltage overshoot

3. No latched state after the ESD

A misconception is that all the ESD cudirectly through the IO. The system ledefined to perform the test on a syston the application this means that a pcurrent will flow through the shieldipart will flow through the IO. Howepart can still be a lot larger than the recomponent ESD levels (HBM/MM). One prevailing approach in testing forapplying the system level ESD pulseIC, but this is not what the IEC 6100[12] describes. For example, connectorsshell will only be stressed with contathe metallic shell, while those with a ponly be stressed with air discharge. Designing on-chip ESD devices witcapability (16A) does not guarantee level specification will be met. Theduring system level ESD is to avoid asoft failures in the system. These failuby either EMI/EMC or due to IR dropswhich could cause triggering of the PReset) circuit, change state of some regIt is possible to conduct all the systethrough the on-chip ESD device, but a is to provide the customer with an protection featuring acceptable ESD vwith the necessary guidelines timplement the chip on the board in thguidelines ...). The standard approach to protect thesebased on the HHISCR (High holdingThe next 3 sections provide the reasdevice is an adequate protection for sys

1. SCR as a high current capable

Silicon Controlled Rectifiers (SCRs) many ESD protection devices used iThey combine a lot of advantagesleakage/capacitance, low clamping especially high current capability per the SCR into an excellent device for hilevels such as during system level ESD

specifications adequate system

els

pulse

urrent will flow evel standard is tem. Depending part of the ESD ing and another ever this second equired standard

r IEC on chip is e directly to the 00-4-2 standard s with a metallic act discharge on plastic shell will

th high current that the system real challenge

any latch-up and ures are induced s inside the chip

POR (Power On gisters ... em level current

better approach adequate ESD

values, and then o successfully he system (PCB

e applications is g current SCR). soning why this stem level

le ESD device

are one of the in the industry. s such as low voltage and area. This turns igh ESD current

D.

2. Reduction of overshoot circuit

The overshoot of an SCR is maintrigger speed of the clamp (ecircuit)[13]. As will be shown furproperty can be kept below the sensitive node. Especially for overshoot should be limited for to avoid any unrecoverable damprevent a disruption to the statedata).

3. Latch-up safe SCR soluCurrent SCR

Aside from a high current carrylimited overshoot voltage, latchthird requirement for a suiprotection. To improve the latchseveral techniques exist. One apvoltage engineering technique (fdiodes) to attain a holding volsupply voltage [1],[4],[5]. While thup safe, the clamping voltage abe higher, limiting its applicabrequirements. Another approachhigh clamping voltage, is the SCR (HHISCR) approach, pre[1],[2],[9],[10] . The basic idea trigger/holding current above tspec (e.g. 200mA) / normal spethrough external shunt resistorslayout.

Figure 3: HHISCR as presented in [2]

The JEDEC latch-up test is onlatch-up story: the ESD protectitrigger during this test. Howevoff-chip ESD protection, the onturn on during the system levefunctional circuits. To prevent condition changes so the device system level pulse has passe

with a proper trigger

nly determined by the especially the trigger rther in the paper, this failure voltage of the system level ESD,

2 reasons. First of all mage and secondly, to e of the chip (loss of

ution: High Holding

ying capability and a h-up immunity is the itable system level h-up safety of SCRs,

pproach is the holding f.i. by adding holding ltage larger than the his approach is latch-and on-resistance will ility for high current h, which solves this high holding current esented by Mergens

is to increase the the JEDEC Latch-up ecification (Figure 3) s and a special SCR

nly one aspect of the ion device should not er, in the absence of -chip protection must el test to protect the LU in that case, the must turn off after the ed. While the first

3A.1-2EOS/ESD SYMPOSIUM 10-168

condition generally relates to the trigger current of the HHISCR, the second is mainly governed by its holding current. To determine the relevant holding current and voltage of a stand-alone ESD clamp, an ESD stress pulse is superposed on a DC bias level. When the DC bias level is then stepwise decreased in subsequent measurements, the exact holding voltage and current can easily be established in the relevant time domain (Figure 4).

Figure 4: Test set up to determine real holding voltage/current

For the system level ESD protection under normal operation, the SCR must turn off after the ESD pulse has disappeared. In this case the holding current of the SCR must be above the maximum drive current of the PMOS (15mA). Applying the above measurement technique to the ESD clamp shows an effective holding current above 22mA at a holding voltage of 2.45V. This proves that the SCR will turn off after the system level ESD pulse is disappeared. The holding current can be tuned further by the resistors RSN and RSP and by the layout of the SCR body for other applications. Combining the high failure current and the demonstrated latch-up immunity, the HHISCR is a viable option for IO protection in this application. The two remaining constraints are related to area consumption and transient overshoot. The available area was not sufficient to implement the standard HHISCR, an improvement was needed to comply with all specifications. The next section presents an Improved HHISCR device with an area reduction of 22% and a faster SCR turn-on speed.

III. Integrated Trigger Approach The standard HHISCR uses fully silicided poly resistors or metal resistors (1-10 Ohm) and an NMOS

based trigger device. Instead of FS poly resistors, active resistors (N+/PWell) can be used. Figure 5 shows the top view of the implemented diffusion resistors. By applying a proper layout implementation, a parasitic NPN bipolar transistor is formed between the RSN (resistor between anode and G2) and RSP (resistor between G1 and cathode). This NPN bipolar acts as a trigger element replacing the NPN bipolar of the NMOS trigger device. The bipolar is evenly distributed across the resistors as shown in Figure 6 (b,c) for simplicity drawn as 3 separate devices. The upper NPN bipolar is formed between anode and G1, the lower NPN bipolar between G2 and GND and another NPN bipolar is formed somewhere in between. Note that each part of the NPN always sees the same resistance (RSN, RSP or a combination of these) given both resistors are of the same value.

Figure 5: Top view of the resistor implementation

The advantage of this distributed technique is that the SCR is not triggered in only one of the two trigger taps (G1, G2), but simultaneously in both trigger taps improving the turn-on speed and reducing the overshoot of the HHISCR. The basic device operation is as follows (Figure 6/Figure 7):

1. Avalanching starts uniformly over the total junction formed by the resistor RSN, but the current at the anode will increase more compared to the current at the G2 side of the junction: the avalanche current flows through the RSN resistor towards G2 which will induce a voltage drop. The avalanche current will turn on the NPNs between the 2 resistors but the bipolar at the G2/cathode side will conduct proportionally more current than the other bipolars (difference in base-emitter voltage due to resistive drops in RSP for each bipolar).

P+ diffusion

N+ diffusion

Contact

Coupled to anodeCoupled to G2

Coupled to cathodeCoupled to G1

0 1 x-axis

RS

NR

SP

3A.1-3 EOS/ESD SYMPOSIUM 10-169

Figure 6: a) the standard HHISCR with only bipolar) b) the NPN is formed distributed ovetrigger tap

2a. Conduction then spreads upmiddle bipolar

2b. Finally, the current will be dequally over the entire NPN.

3. When enough current flowresistor, to build up a voltage it, the base emitter of the NPNforward biased, inducing feedback and finally turning on

Figure 7: General IV curve of the Improved HHthe different regions 1, 2a, 2b and 3 related to different parasitic elements inside the resistors

It is important to note that elements/resistors must be separateguard rings from the SCR and other cithe formation of unwanted parasitic de

injection in G1 trigger tap (NMOS trigger device – also depr the 2 resistors (RSN, RSP) c) the NPN shown in b injects trig

pwards to the

distributed more

ws through the of 0.7 V across

N or PNP will be the positive

n the SCR.

HISCR highlighting current flow in the

the trigger ed with proper ircuit to prevent vices.

Simulations were performed to ibehaviour of the trigger ddistribution was simulated alindicated in Figure 5). The RSN adivided in different segments. FNPN model was added and a mavalanche current. The substratresistive network. (Figure 8)

DistributedSusbtrate Mo

Cathode

RSNG2

RSP

Iav IQ,c

Figure 8: Simulation model

In Figure 9 the simulated avalalong the x-axis are plotted foravalanche current is the higanode/substrate junction. All theRSN resistor will contribute to thbut the anode/substrate region

icted by its intrinsic NPN gger current in G1 and G2

investigate the current device. The current long the x-axis (as and RSP resistors were For each segment an model to simulate the e was modelled as a

d odel

G1

Anode

Iav IQ,c

lanche current levels r different times. The ghest at position 1: e junction area of the he avalanche current, will always see the

3A.1-4EOS/ESD SYMPOSIUM 10-170

highest voltage during the triggering and therefore conduct the most current. The avalanche current will pull the substrate voltage above ground and the distributed bipolar will start to conduct current.

Figure 9: Simulation of the current behaviour inside the trigger device: avalanche current (Iav) at the RSN resistor

Figure 10 shows the bipolar current distribution along the x-axis. First observation: the bipolar closest to the G2-cathode side of the junction will conduct initially the most current. This is because its base-emitter sees the largest voltage drop. Second observation: the bipolar closest to the anode junction will conduct proportionally more current.

Figure 10: Simulation of the current behaviour inside the trigger device: bipolar current (IQ,c) between RSN and RSP

IV. Analysis

1) Measurement results

Figure 11 compares TLP measurements of the standard and the improved HHISCR devices (100ns pulse width, 10ns rise time) showing a similar clamping behaviour with a small difference in the trigger voltage (Vt1). This is related to the different type of trigger bipolar that is formed. The increase from 8.5V to 8.8V stays within the design window for this design. The most sensitive element is a NMOS Gate oxide (gate source stress in inversion), with a failure level of 13.5V (including safety margins) well above the trigger voltage. Both devices remain within the design window of the I/O pins. A slightly higher failure current for the proposed device is observed due to an increased failure voltage of the trigger bipolar compared to the NMOS based trigger device.

Figure 11: TLP extracted IV curves

-04

-04

-03

-02

-02

-01

0 0.2 0.4 0.6 0.8 1

time 1

time 2

time 3

Ava

lanc

he C

urre

nt d

itst

ribu

tion

111110090908070706050504030202010000

0 0.2 0.4 0.6 0.8 1

time 1

time 2

time 3

time 4

time 5

time 6

time 7

time 8

Bipo

lar C

urre

nt d

itst

ribu

tion

0

1

2

3

4

5

6

7

0 2 4 6 8 10

10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3

HHISCRImproved HHISCR

I D

UT

(A)

V DUT(V)

ILEAKAGE

(A)

0

0.1

0.2

0.3

0.4

0.5

0.6

1 2 3 4 5 6 7 8 9

1 0-8

10-7

10-6

10-5

10- 4

10- 3

I D

UT

(A)

V DUT(V)

3A.1-5 EOS/ESD SYMPOSIUM 10-171

Figure 12 left: parallel implemented resistors; right: anti-parallel implemented resistors

2) Influence of the orientation of the resistors

This section investigates different resistor configurations. In the implementation of figure 5, the resistors were in a parallel orientation (Figure 12 left): the anode connection of RSN adjacent to the G1 connection of RSP and the G2 connection close to the cathode connection. A second possible implementation is to place the resistors anti-parallel (see Figure 12 right).

The difference between the two implementations is that in the parallel implementation (Figure 12a) each bipolar has RSN or RSP in series that will contribute to build up 0.7V over the resistor and over the base emitter junction of the bipolar transistors. In the anti-parallel implementation (Figure 12b), the cathode is adjacent to the anode instead of the G1 connection. This has some implications: not all of the 3 indicated bipolars will contribute equally to create the required voltage build up to turn on the SCR. As seen in Figure 12b, the current flow through bipolar 1 will not contribute to turn on the SCR (this current is flowing

direct from anode to cathode of the ESD clamp, so it will not contribute to forward the base-emitter junctions of the SCR). The TLP results of the two implementations are shown in Figure 13. The trigger current of the anti-parallel implementation has increased from 273 mA to 469 mA without any constraint on the area or value of the resistors.

Figure 13: Influence of the resistor orientation

Q3

12a2bcathode

G1

G2

RSN

RSP

anode

Current flow

Current flowRSN

RSP

Q1 Q2

anode

cathode G1

G2

Current flow

Current flow

RSN

RSP

anode

cathode G1

G2

2a2b 1

Parallel Implemented Resistors Anti-Parallel Implemented Resistors

cathode

G1

G2

RSN

RSP

anode

Q3Q1 Q2

top

vie

wC

urr

en

t flo

wQ1 Q2 Q3

Q1

Q2Q3

0

0.2

0.4

0.6

0.8

1

0 2 4 6 8 10

parallel implemented resistorsanti-parallel implemented resistors

I [A]

V [V]

Increase

of It1

3A.1-6EOS/ESD SYMPOSIUM 10-172

3) Trigger voltage engineering

The trigger voltage of the clamp is than the reference HHISCR (Figure 11the fact that the trigger element is no lobut an NPN formed between two N+ juPwell. One technique to lower this trito add a gate between the resistors Rprevent the formation of oxide in results in an improved and even fasreduction of trigger voltage).

Figure 14: Improving the NPN by adding aresistors

Figure 15:Trigger voltage engineering – TLP IV

0

0.05

0.1

0.15

0.2

4 5 6 7 8

Improved HHISCRImproved MOS-HHISCRHHISCR

I [A]

slightly higher ). This is due to

onger an NMOS unctions and the igger voltage is Rsp and Rsn to

between. This ster NPN (0.4V

a gate between the

V curves

4) Layout optimization The previous implementations adiscrete resistors. The device coufurther by splitting the resistor(Figure 16). The total width oflarge enough to handle the trimproved HHISCR to prevent dcircuit. . . ,With 1 , , The total length of trigger circuitto handle the trigger current, redesign constraint. . . ,With 1 , The third design parameter is thewhich determines the trigger curr

. .With these 3 formulas the tridesigned.

5) Overshoot investigation

The improved HHISCR as proposimilar behaviour as the standapulses. By adding a gate betwetrigger bipolar is improved (smalon-resistance). This is characteranalysis (Figure 17) by:

• An overshoot reduction

• A trigger speed enhancem

9 10V [V]

always consisted of 2 uld be optimized even s in different fingers f the device must be rigger current of the damage of the trigger

, (1) t must be long enough esulting in the second

, (2) e value of the resistor rent

(3)

igger circuit can be

osed in Figure 6 has a ard HHISCR for fast een the resistors, the ller base length, lower rized in the transient

ment

3A.1-7 EOS/ESD SYMPOSIUM 10-173

Figure 16: Optimized layout of the trigger devic

Figure 17: Transient behaviour extracted with system (2ns pulse width – 200 ps risetime)

V. Implementation

The optimal solution is the MOS-HHIparallel resistors drawn according thdescribed in previous section. Thsuccessfully implemented both itechnology (3.3 V domain) and in a 0technology (3.3 V domain). The improved HHISCR has a similcompared to the standard version but thwas decreased by 22%. This savingintegration of the trigger device in layout of the resistors. (Figure 18) The HBM level of the clamp exceedof the tester in line with the expecta

Wb

Wa

RS

N

Wa

RS

N

RS

P

An

od

e

An

od

e

G1

G2

G2

Cat

ho

de

ce

a standard vf-TLP

n

ISCR with anti-he design rules his clamp was in a 0.13um 0.35 um CMOS

lar performance he required area

g is due to the the optimized

ds the 8kV limit ations based on

SCR size. System level tests product level, under powered coany additional protection componpin passed 8kV contact and 15 kchip protection against 8kV HBMapplication since not all the currIO: a proper shield/ground imdischarges a part of the ESD curthe configuration of the boardcustomer requirements will havneeded on-chip ESD protection tsystem-level ESD protection anreal world ESD protection.

Figure 18: Top view of the ESD layout

Wa Wa Wa Wa Wa

RS

N

RS

N

RS

N

RS

N

RS

N

RS

P

RS

P

RS

P

RS

P

RS

P

An

od

e

An

od

e

An

od

e

An

od

e

An

od

e

G1

G1

G1

G1

G1

G2

G2

G2

G2

G2

Cat

ho

de

Cat

ho

de

Cat

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de

Cat

ho

de

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ndar

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CR

(IEC 61000-4-2) on onditions and without nents at the connector kV air discharge. On-M was enough for this rent flows through the

mplementation already rrent. The application, d/connectors and the ve an impact on the to achieve the desired d more important the

Impr

oved

HH

ISC

R

3A.1-8EOS/ESD SYMPOSIUM 10-174

The high current ESD level is achieved while the leakage is below 330 pA (VDD +10%) and 33 nA at elevated temperature (125°C). (Figure 19)

Figure 19: Low leakage at room and elevated temperatures

Conclusion High current levels, limited overshoot and latch-up safety are the key aspects for a successful system level implementation. This paper showed that optimized layout of the HHISCR [11] can reduce the needed area to reach system level ESD requirements by integrating the trigger device into the resistor layout.

Acknowledgements The authors would like to thank Natarajan M Iyer for his valuable suggestions to improve the structure of the paper.

References [1] M. Mergens, “Advanced SCR ESD Protection

Circuits for CMOS / SOI Nanotechnologies”, CICC 2005

[2] M. Mergens, “High Holding Current SCR (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation.”, EOS/ESD 2002

[3] T. Smedes, “Relations between system level ESD and (vf-)TLP”, EOS/ESD 2006

[4] M. Ker, “Overview of On-Chip Electrostatic Discharge Protection Design With SCR-based Devices in CMOS Integrated Circuits”, IEEE Trans. Device and Materials Reliability, June 2005

[5] C. Russ , “GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes.”, EOS/ESD 2001

[6] M. Roseeuw, “On-Chip ESD Protection Achieving 8kV HBM Without Compromising the 3.4Gbps HDMI Interface”, RCJ 2009

[7] V.A. Vashchenko, ”System Level and Hot Plug-in Protection of High Voltage Transient Pins“, EOS/ESD 2009

[8] D. Robinson-Hahn, “Is System-Level ESD Testing Valid for ICs?”, Power Electronics Rechnoloby, september 2009

[9] US 6,803,633, “Electrostatic Discharge Protection Structures Having High Holding Current For Latch-Up Immunity”

[10] US 7,064,393, “Electrostatic Discharge Protection Structures Having High Holding Current For Latch-Up Immunity”

[11] US 2010/0008002, “High Trigger Current Silicon Controlled Rectifier”

[12] IEC 61000-4-2, Edition 2.0

[13] G. Wybo. “Characterizing the Transient Device Behavior of SCRs by means of VFTLP Waveform Analysis”, EOS/ESD 2007

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

0 1 2 3 4 5 6 7 8 9 10

curr

ent (

A)

Voltage (V)

25C

85C

125C

3A.1-9 EOS/ESD SYMPOSIUM 10-175

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3A.1-10EOS/ESD SYMPOSIUM 10-176

Sofics Proprietary – ©2011

About Sofics

Sofics  (www.sofics.com)  is  the  world  leader  in  on‐chip  ESD  protection.  Its patented  technology  is  proven  in more  than  a  thousand  IC  designs  across  all major foundries and process nodes. IC companies of all sizes rely on Sofics for off‐the‐shelf  or  custom‐crafted  solutions  to  protect  overvoltage  I/Os,  other  non‐standard  I/Os,  and  high‐voltage  ICs,  including  those  that  require  system‐level protection on the chip. Sofics technology produces smaller I/Os than any generic ESD configuration. It also permits twice the IC performance in high‐frequency and high‐speed applications. Sofics ESD solutions and service begin where the foundry design manual ends. 

Our service and support

Our business models include • Single‐use, multi‐use or royalty bearing license for ESD clamps • Services to customize ESD protection 

o Enable unique requirements for Latch‐up, ESD, EOS o Layout, metallization and aspect ratio customization o Area, capacitance, leakage optimization 

• Transfer of individual clamps to another target technology • Develop custom ESD clamps for foundry or proprietary process • Debugging and correcting an existing IC or IO • ESD testing and analysis 

Notes

As  is  the  case with many  published  ESD  design  solutions,  the  techniques  and protection  solutions described  in  this data  sheet  are protected by patents  and patents  pending  and  cannot  be  copied  freely.  PowerQubic,  TakeCharge,  and Sofics are trademarks of Sofics BVBA. 

Version

May 2011

  

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