on the design of a photonic network-on-chip
DESCRIPTION
Presented for HPCAN Session by : Millad Ghane. Assaf Shacham , Keren Bergman, Luca P. Carloni. On the Design of a Photonic Network-on-Chip. NOCS’07. Why NoC ?. Scaling Transistor Speed and Integrity Tighter Logic Power Dissipation Increasing Number of Cores per Chip - PowerPoint PPT PresentationTRANSCRIPT
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On the Design of a Photonic Network-on-Chip
Assaf Shacham, Keren Bergman, Luca P. Carloni
Presented for HPCAN Session by: Millad Ghane
NOCS’07
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Why NoC ?
Scaling Transistor Speed and Integrity Tighter Logic Power Dissipation
Increasing Number of Cores per Chip Bottleneck: Global Intrachip Communications▪ Bandwidth▪ Power
Performance-per-watt
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Why Optic ?
Low Power Dissipation Ultra-high Throughput Minimal Latency End-to-end Transmission
No Repeating No Regeneration No Buffering
A silicon ring
resonator
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Hybrid Architecture
Photonic Interconnection High Bandwidth Messages
Electronic Interconnection Low Bandwidth Messages Short Control Messages
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Photonic Properties
Advantages Bit-rate Transparency▪ Not Switching by Every Bit of Data▪ Switching Once per Message
Low Loss in Optical Waveguide▪ Independence of Transmission Distance
Disadvantages No Storage Element E/O and O/E Conversions▪ Off-chip Lasers
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Packet Life
D
D
SSending path-setup packet
Electronic Network
Optic Network
S
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Packet Life
D
S D
SSending optical packet
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Packet Life
D
S D
SSending path-teardown packet
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Packet Life
D
S D
SSending path-blocked packet
path-teardown packet
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Building Blocks
70 µm
70 µm
Photonic Switching ElementElectrical Router
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Building Blocks Problems No Injection/Ejection Port Not Deadlock-Free
Wide Turns
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Approach
Injection
Torus Address
Ejection
Gateway Switch
Injection Switch
Ejection Switch
Torus Network Nodes
Access Points Address
Format
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Deadlock Solution
Injection-Ejection Blocking [previous slide]
Intra-dimentional Blocking (Torus Network) Virtual Channel Flow Control▪ Circuit Switching
terminate-on-timeout packet
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Simulation Parameters
POINTS Simulator Based on OMNET++
36-core CMP 6x6 planar
Chip size: 20 x 20 mm Uniform Traffic 3 Cases
Deadlock Message Size Optimization Increasing Path Diversity
2
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Message Size Optimization Long path-setup latency
Nonoseconds Super fast transmission
Overhead Ratio:
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Message Size Optimization (cont.) Message Duration: 50ns Message Size: 2KB Suitable for
DMA Trans
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Increasing Path Diversity PD=2
Less Hardware Less Overhead
Difference
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Q & A ?
Thanks !