on the improvement of statistical timing analysis

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On the Improvement of On the Improvement of Statistical Timing Statistical Timing

AnalysisAnalysis

Rajesh GargRajesh GargNikhil JayakumarNikhil Jayakumar

Sunil P. KhatriSunil P. Khatri

Department of Electrical & Computer Department of Electrical & Computer Engineering,Engineering,

Texas A&M University, College Station.Texas A&M University, College Station.

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OutlineOutline

MotivationMotivation Previous WorkPrevious Work Our ApproachOur Approach

Phase 1Phase 1 Phase 2Phase 2

Propagating Arrival TimesPropagating Arrival Times

ExperimentsExperiments ResultsResults Conclusions & Future WorkConclusions & Future Work

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MotivationMotivation

Increasing process variation has Increasing process variation has necessitated necessitated statistical analysis of timing.statistical analysis of timing. Alternative to performing static timing analysis Alternative to performing static timing analysis

over several process corners.over several process corners. Useful way to get better yield estimates.Useful way to get better yield estimates.

Current approaches to statistical timing Current approaches to statistical timing are are not readily being acceptednot readily being accepted by chip by chip designers.designers. Time consumingTime consuming PessimisticPessimistic

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SSTA-Statistical Static Timing SSTA-Statistical Static Timing AnalysisAnalysis

Based on the principles of Based on the principles of Static Timing Static Timing Analysis (STA).Analysis (STA). STA propagates arrival times using SUM, STA propagates arrival times using SUM,

MAX operations.MAX operations. SSTA: implement SUM and MAX operations SSTA: implement SUM and MAX operations

for for delay distributionsdelay distributions.. Identify only structurally long paths.Identify only structurally long paths.

Such Such paths may not be sensitizable!paths may not be sensitizable!

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SSTA- Sources of PessimismSSTA- Sources of Pessimism

Spatial CorrelationsSpatial Correlations Path CorrelationsPath Correlations Approximation of PDFs by Gaussian Approximation of PDFs by Gaussian

distributions.distributions. Approximation when calculating MAX of two Approximation when calculating MAX of two

distributions.distributions. False paths.False paths. Assumption that gate delay can be represented Assumption that gate delay can be represented

by a by a singlesingle Normal distribution. Normal distribution.

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Our ContributionsOur Contributions

Eliminate False pathsEliminate False paths Use a Use a sensitizablesensitizable timing analysis tool. timing analysis tool.

Delay for Delay for each input transitioneach input transition of a gate is of a gate is represented by a Normal distribution.represented by a Normal distribution. Use the particular Normal distribution corresponding Use the particular Normal distribution corresponding

to input transition of a gate that results in large to input transition of a gate that results in large sensitizable delays.sensitizable delays.

In SSTA, the delay of a gate is represented by a In SSTA, the delay of a gate is represented by a single Normal distribution. single Normal distribution.

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Previous WorkPrevious Work ““False-path-aware Statistical Timing Analysis and False-path-aware Statistical Timing Analysis and

Efficient Path Selection for Delay Testing and Efficient Path Selection for Delay Testing and Timing Validation”, J.-J.Liou et.al (DAC 2002)Timing Validation”, J.-J.Liou et.al (DAC 2002) First perform First perform traditional SSTA.traditional SSTA. Then, attempt to find sensitizable paths.Then, attempt to find sensitizable paths. Assume delay of a gate is represented by a Assume delay of a gate is represented by a single single

Gaussian Gaussian Ignores difference in input arrival times.Ignores difference in input arrival times.

Our Approach: Our Approach: First find sensitizable input vector transitionsFirst find sensitizable input vector transitions, then , then

perform statistical timing analysis.perform statistical timing analysis. Allows us to consider the actual input transitions Allows us to consider the actual input transitions

occurring at the inputs of each gate.occurring at the inputs of each gate. Takes input arrival time differences into consideration.Takes input arrival time differences into consideration.

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Our ApproachOur Approach

Phase 1Phase 1 Find set of sensitizable critical delay Find set of sensitizable critical delay

transitions. This yields a more accurate transitions. This yields a more accurate analysisanalysis

Phase 2Phase 2 Perform Statistical Timing Analysis on the Perform Statistical Timing Analysis on the

vector transitions from Phase 1.vector transitions from Phase 1. Exploit information on input transition at each Exploit information on input transition at each

gate (from Phase 1) to get a yet more gate (from Phase 1) to get a yet more accurate analysis.accurate analysis.

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Phase 1: Finding Sensitizable Phase 1: Finding Sensitizable Delay-Critical Vector TransitionsDelay-Critical Vector Transitions

Use the Use the sensesense package in SIS to find the package in SIS to find the maximum sensitizable delaymaximum sensitizable delay.. Sense uses a SAT solver to verify if a Sense uses a SAT solver to verify if a

particular delay is sensitizable.particular delay is sensitizable. Starts with longest structural delay (from static Starts with longest structural delay (from static

timing analysis).timing analysis). Keeps reducing delay in fixed steps until a Keeps reducing delay in fixed steps until a

sensitizable maximum delay D is foundsensitizable maximum delay D is found Implicitly eliminates false paths.Implicitly eliminates false paths.

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Modified the Modified the sensesense package to return package to return allall the the primary input vector transitions that cause the primary input vector transitions that cause the largest delays.largest delays. Returns primary input vectors that cause these large Returns primary input vectors that cause these large

delays.delays. Our modification also generates all possible previous Our modification also generates all possible previous

values on the primary inputs that cause the output to values on the primary inputs that cause the output to transition.transition.

Insert complement of largest sensitizable vector Insert complement of largest sensitizable vector in the SAT instance for in the SAT instance for sensesense and run and run sensesense again iterativelyagain iteratively Repeat until a user-specified number of delay-critical Repeat until a user-specified number of delay-critical

transitions is collected.transitions is collected.


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Phase 2: Compute Output Delay Phase 2: Compute Output Delay DistributionsDistributions

Perform Monte-Carlo analysis on set of Perform Monte-Carlo analysis on set of delay-critical vector transitions.delay-critical vector transitions.

Propagate arrival times using information Propagate arrival times using information on the transition occurring (from Phase 1).on the transition occurring (from Phase 1). Utilize delay distribution for the actual input Utilize delay distribution for the actual input

transition observed at each gate. transition observed at each gate.

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For regular Static Timing Analysis (for falling output)For regular Static Timing Analysis (for falling output) Delay = MAX{ (ATDelay = MAX{ (ATaa + MAX(D + MAX(D0000→11→11, D, D01→1101→11)) , )) ,

(AT(ATbb + MAX(D + MAX(D0000→11→11, D, D10→1110→11)) })) }

ab ab →→ ab ab Delay (ps)Delay (ps)

00 00 →11→11 55.355.3

01 01 →11→11 46.546.5

10 10 →11→11 42.742.7

0 10

a

bc

a

b

c

35

55.3ps

55.3ps

90.3

= 35+55.3 = 90.3 = 35+55.3 = 90.3

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Propagating Arrival TimesPropagating Arrival Times More accurate estimate for falling output (used in our More accurate estimate for falling output (used in our

approach)approach) Delay = MAX{ (ATDelay = MAX{ (ATaa + D + D0000→11→11), (AT), (ATbb + D + D1010→11→11) }) }


00 00 →11→11 55.355.3

01 01 →11→11 46.546.5

10 10 →11→11 42.742.7

0 10

a

bc

a

b

c

35 77.7

55.3ps

42.7ps

90.3

= 35 + 42.7 = 77.7= 35 + 42.7 = 77.7

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For regular Static Timing Analysis (for rising output)For regular Static Timing Analysis (for rising output) Delay = MAX{ (ATDelay = MAX{ (ATaa + MAX(D + MAX(D1111→00→00, D, D11→0111→01)) , )) ,

(AT(ATbb + MAX(D + MAX(D1111→00→00, D, D11→1011→10)) })) }


1111→00→00 30.530.5

1111→01→01 50.550.5

1111→10→10 53.053.0

0 10

a

bc

35

50.5ps

53.0ps

88.0

c

a

b

= 35+53.0 = 88.0= 35+53.0 = 88.0

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Propagating Arrival TimesPropagating Arrival Times More accurate estimate for rising output (used in our More accurate estimate for rising output (used in our

approach)approach) Delay = MIN{ (ATDelay = MIN{ (ATaa + D + D1111→01→01), (AT), (ATbb + D + D1111→00→00) }) }

a

bc

0 10 35

50.5ps

30.5ps

88.0

c

a

b

60.5= 10 + 50.5 = 60.5= 10 + 50.5 = 60.5


1111→00→00 30.530.5

1111→01→01 50.550.5

1111→10→10 53.053.0

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Plot of output delay with different input arrival times.Plot of output delay with different input arrival times. STA and our new approach are compared with SPICESTA and our new approach are compared with SPICE One input transitioning at a fixed time.One input transitioning at a fixed time. Swept transition time of other input Swept transition time of other input

NAND2: 00→11 NAND2: 11→00

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Propagating Arrival TimesPropagating Arrival Times Similarly for a 3-input Similarly for a 3-input NAND3NAND3 gate with inputs gate with inputs

{a,b,c} and output {O}.{a,b,c} and output {O}. For For falling output transitionfalling output transition – all inputs need to – all inputs need to

switch to logic 1.switch to logic 1. 000000→100→110→111→100→110→111 ATout = MAX{ (ATATout = MAX{ (ATaa + D + D000 →111000 →111),),

(AT(ATbb + D + D100 →111100 →111),),(AT(ATcc + D + D110 →111110 →111) }) }

For For rising output transitionrising output transition – only one of the – only one of the inputs needs to switch to logic 0.inputs needs to switch to logic 0. 111111→011→001→000→011→001→000 ATout = MIN{ (ATATout = MIN{ (ATaa + D + D111 →011111 →011),),

(AT(ATbb + D + D111 →001111 →001),),(AT(ATcc + D + D111 →000111 →000) }) }

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Standard-cell library of 8 cellsStandard-cell library of 8 cells INV1X, INV2X, NAND2, NAND3, NAND4, NOR2, INV1X, INV2X, NAND2, NAND3, NAND4, NOR2,

NOR3, NOR4. NOR3, NOR4. Used SPICE to characterize the cells.Used SPICE to characterize the cells.

Used 0.1um BPTM process.Used 0.1um BPTM process.

ExperimentsExperiments

ParameterParameter Nominal ValueNominal Value σσ

LL 0.1 u0.1 u 0.005 u0.005 u

VTnVTn 0.2607 V0.2607 V 0.013 V0.013 V

VTpVTp 0.3030 V0.3030 V 0.01515 V0.01515 VVariations applied

Created table of values for mean and standard deviation Created table of values for mean and standard deviation of the delay for all possible transitions for a set of loads.of the delay for all possible transitions for a set of loads.

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Delay Distribution exampleDelay Distribution example Delay of a gate cannot be represented by a Delay of a gate cannot be represented by a

single Gaussian distribution.single Gaussian distribution. Depends on input transitions.Depends on input transitions.

NAND2: Rising output transition NAND2: Falling output transition

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ExperimentsExperiments Phase 1Phase 1

Compute top 50 delay-critical vector transitions.Compute top 50 delay-critical vector transitions. Phase 2Phase 2

Use knowledge of input transitions at each gate Use knowledge of input transitions at each gate from Phase 1.from Phase 1.

Propagate arrival times (using method Propagate arrival times (using method discussed).discussed).

Propagate 1000 times Propagate 1000 times For each transition, choose a random value of delay For each transition, choose a random value of delay

from a Gaussian distribution.from a Gaussian distribution. Use values of Use values of and and from a pre-characterized table for the from a pre-characterized table for the

particular vector transition appearing at the gate.particular vector transition appearing at the gate. Use same Use same + + nndelay point for all input transitions of gatedelay point for all input transitions of gate

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ExperimentsExperiments

Compared our approach (StatSense) with Compared our approach (StatSense) with Monte-Carlo based SSTA (10000 MC Monte-Carlo based SSTA (10000 MC iterations).iterations).

Compared results for a set of ISCAS and Compared results for a set of ISCAS and MCNC benchmark circuits.MCNC benchmark circuits.

Also compared results from 50 critical Also compared results from 50 critical vector transitions versus 25 critical vector vector transitions versus 25 critical vector transitions.transitions. 1000 MC runs for each vector transition.1000 MC runs for each vector transition.

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ResultsResults

Our approach (StatSense) is Our approach (StatSense) is significantly less pessimisticsignificantly less pessimistic.. Takes Takes ~2.3X more time to run (50000 MC runs compared to ~2.3X more time to run (50000 MC runs compared to

10000)10000)

Ckt

SSTA StatSense with 50 vectors

μ (ps) σ (ps) μ+3σ (ps) runtime (s) μ (ps) σ (ps) μ+3σ (ps)μ+3σ Ratio runtime(s)

runtime ratio

alu2 1008.39 19.08 1065.63 278.8 661.25 17.69 714.32 0.67 1991.5 7.14

alu4 1234.77 18.21 1289.4 560.2 753.01 23.74 824.23 0.64 3386.8 6.04

apex6 680.51 10.95 713.36 632.2 447.66 26.36 526.74 0.74 895 1.41

apex7 489.79 8.16 514.27 207.5 427.17 12.89 465.84 0.9 260.6 1.25

C499 737 11.29 770.87 419.4 617.92 14.55 661.57 0.86 481.6 1.15

C1355 714.82 8.59 740.59 484.8 418.08 11.47 452.49 0.61 578.1 1.2

cordic 669.99 8.6 695.79 657 578.18 18.5 633.68 0.91 657.23 1

i6 496.16 22.8 564.56 353 449.55 19.84 508.52 0.9 609.5 1.73

i7 496.25 21.76 561.53 514.3 449.31 20.6 511.11 0.91 494.9 0.96

rot 781.23 13.75 822.48 571 501.65 17.24 552.72 0.67 1343.6 2.35

x1 319.34 10.4 350.54 261.5 269.43 13.7 310.1 0.88 277.14 1.06

AVG 0.79 2.29

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ResultsResults

StatSense with 25 vector transitions takes only 50% more time than SSTA.StatSense with 25 vector transitions takes only 50% more time than SSTA. Runtime is not 5X (for 50 vector transitions) or 2.5X (for 25 transitions)Runtime is not 5X (for 50 vector transitions) or 2.5X (for 25 transitions)

If there is no transition at output of a gate, If there is no transition at output of a gate, delay computations in the fanout of a gate delay computations in the fanout of a gate can be avoided. can be avoided.

No such pruning possible in SSTA.No such pruning possible in SSTA.

Ckt

SSTA StatSense with 50 vectors StatSense with 25 vectors

μ+3σ (ps) runtime (s)μ+3σRatio

runtime ratio

μ+3σRatio

runtime ratio

alu2 1065.63 278.8 0.67 7.14 0.68 4.42

alu4 1289.4 560.2 0.64 6.04 0.63 5.74

apex6 713.36 632.2 0.74 1.41 0.77 0.716

apex7 514.27 207.5 0.9 1.25 0.91 0.62

C499 770.87 419.4 0.86 1.15 0.86 0.57

C1355 740.59 484.8 0.61 1.2 0.61 0.6

cordic 695.79 657 0.91 1 0.9 0.54

i6 564.56 353 0.9 1.73 0.9 0.83

i7 561.53 514.3 0.91 0.96 0.91 0.65

rot 822.48 571 0.67 2.35 0.67 1.42

x1 350.54 261.5 0.88 1.06 0.91 0.54

AVG 0.79 2.29 0.8 1.51

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Example – apex7Example – apex7

Delay histogram is significantly less pessimistic.Delay histogram is significantly less pessimistic. Circuit delay is not a Gaussian distribution.Circuit delay is not a Gaussian distribution.

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Conclusions and Future WorkConclusions and Future Work

Current statistical timing analysis approaches Current statistical timing analysis approaches are pessimistic.are pessimistic. Pessimism due to false paths and Pessimism due to false paths and Assumption that delay of a gate can be represented Assumption that delay of a gate can be represented

by a single Gaussian distribution.by a single Gaussian distribution. Our approach is Our approach is significantly less pessimisticsignificantly less pessimistic.. Future workFuture work

Decrease runtimes.Decrease runtimes. Explore methods to find the minimum number of Explore methods to find the minimum number of

vector transitions required to get a realistic statistical vector transitions required to get a realistic statistical timing result.timing result.

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THANK YOU!THANK YOU!

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Use the Use the sense sense package in SIS to find the maximum package in SIS to find the maximum sensitizable delay.sensitizable delay. Sense uses a SAT solver to verify if a particular delay is Sense uses a SAT solver to verify if a particular delay is

sensitizeable.sensitizeable. Starts with longest structural delay (from a static timing analysis).Starts with longest structural delay (from a static timing analysis). Keeps reducing delay in steps till a delay D is sensitizable.Keeps reducing delay in steps till a delay D is sensitizable.

Implicitly eliminates false paths.Implicitly eliminates false paths. Modified sense package to return all the primary input Modified sense package to return all the primary input

vector transitions that causes this maximum delay.vector transitions that causes this maximum delay. Returns current primary input vector that causes this maximum Returns current primary input vector that causes this maximum

delay.delay. Also, generate all possible previous values of the primary input Also, generate all possible previous values of the primary input

vector that cause the output to transition.vector that cause the output to transition. Insert complement of largest sensitizable vector in Insert complement of largest sensitizable vector in

sense’s SAT instance and run sense again.sense’s SAT instance and run sense again. Repeat till a large-enough (user-specified) set of delay-critical Repeat till a large-enough (user-specified) set of delay-critical

transitions is collected.transitions is collected.

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Propagating Arrival TimesPropagating Arrival Times Naïve estimateNaïve estimate

Delay = MAX(ATa, ATb) + D00Delay = MAX(ATa, ATb) + D00→→1111 = 35+55.3 = 90.3 = 35+55.3 = 90.3


00 00 →11→11 55.355.3

01 01 →11→11 46.546.5

10 10 →11→11 42.742.7

0 10

a

bc

a

b

c

35

55.3ps

55.3ps

90.3

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ResultsResults

testtest

on the improvement of statistical timing analysis

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