on the simplicity of converting · 8/21/2013 · amir moradi, oliver mischke embedded security...

On the Simplicity of Converting Leakages from Multivariate to Univariate

21. Aug. 2013

Amir Moradi, Oliver MischkeEmbedded Security Group + Hardware Security GroupRuhr University Bochum, Germany

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Embedded Security Group

Outline Definitions, Masking, etc. Target masking scheme The story behind our findings Practical issues

CHES 2013 | Santa Barbara | 21. Aug 2013 Amir Moradi

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Masking Well‐known SCA countermeasure


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Masking Well‐known SCA countermeasure to make the SC leakages independent of expected intermediate values


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Masking Well‐known SCA countermeasure to make the SC leakages independent of expected intermediate values Randomness is required


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Masking Well‐known SCA countermeasure to make the SC leakages independent of expected intermediate values Randomness is required Let’s consider the most common one, Boolean Masking


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Sbox

kp S(p⊕k)


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Sbox

kp S(p⊕k) masked

Sbox

kp

m

S(p⊕k)⊕m'm m'→


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Univariate vs. Multivariate Attacks

Sbox

kp S(p⊕k) masked

Sbox

kp

m



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Sbox

kp S(p⊕k) masked

Sbox

kp

m



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Sbox

kp S(p⊕k) masked

Sbox

kp

m



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Sbox

kp S(p⊕k) masked

Sbox

kp

m



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Sbox

kp S(p⊕k) masked

Sbox

kp

m



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Sbox

kp S(p⊕k) masked

Sbox

kp

m


DPA/CPA/MIA


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Sbox

kp S(p⊕k) masked

Sbox

kp

m


DPA/CPA/MIA bivariate MIA

combining: DPA/CPA


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Sbox

kp S(p⊕k) masked

Sbox

kp

m



combining: DPA/CPA

multiply: 2nd order bivariate


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Sbox

kp S(p⊕k) masked

Sbox

kp

m



combining: DPA/CPA

multiply: 2nd order bivariatesquaring: 2nd order univariate


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Sbox

kp S(p⊕k) masked

Sbox

kp

m



combining: DPA/CPA

multiply: 2nd order bivariate

addition: 1st order bivariate

squaring: 2nd order univariate


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Masking in Hardware

maskedSbox

m

i⊕m S(i)⊕m'


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Masking in Hardware Pre‐computing the masked tables in software

maskedSbox

m

i⊕m S(i)⊕m'


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– Sequential operations, Time consuming, Low efficiency

maskedSbox

m

i⊕m S(i)⊕m'


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– Sequential operations, Time consuming, Low efficiency High efficiency is desired in HARDWARE

– amongst the main reasons

maskedSbox

m

i⊕m S(i)⊕m'


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– amongst the main reasons ad‐hoc/heuristic schemes

maskedSbox

m

i⊕m S(i)⊕m'


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– amongst the main reasons ad‐hoc/heuristic schemes Processing the mask (m) and masked data (i⊕m) simultaneously

maskedSbox

m

i⊕m S(i)⊕m'


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– joint distribution of SC leakages mainly because of GLITCHES– possible attacks

maskedSbox

m

i⊕m S(i)⊕m'


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Systematic schemes

maskedSbox

m

i⊕m S(i)⊕m'


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Systematic schemes– Threshold Implementation, Security against 1st order attacks

maskedSbox

m

i⊕m S(i)⊕m'


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Systematic schemes– Threshold Implementation, Security against 1st order attacks

Desired: security against univariate attacks of any order

maskedSbox

m

i⊕m S(i)⊕m'


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Target Scheme Prouff, Roche: Higher‐Order Glitches Free Implementation of the AES

Using Secure Multi‐party Computation Protocols. CHES 2011.


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Using Secure Multi‐party Computation Protocols. CHES 2011. Multi‐party computation + Shamir’s secret sharing


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Using Secure Multi‐party Computation Protocols. CHES 2011. Multi‐party computation + Shamir’s secret sharing Basic GF(28) operations, e.g., addition is easy


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– Multiplication needs more effort


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– Multiplication needs more effort An Sbox computation


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– Multiplication needs more effort An Sbox computation

Our goal– Hardware implementation using minimum settings– Using a Virtex‐5 FPGA (SASEBO‐GII)


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Target Scheme ‐ Design


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Target Scheme ‐ Performance


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Target Scheme ‐ Performance 66 clock cycles for Inversion, 66 clock cycles for Affine

– One Sbox in 132 clock cycles


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– One Sbox in 132 clock cycles One full SubBytes in 132 × 16 = 2112 clock cycles


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– One Sbox in 132 clock cycles One full SubBytes in 132 × 16 = 2112 clock cycles One full MixColumns + AddRoundKey in 12 × 16 = 192 clock cycles


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Hard to convince the industry sector?


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Hard to convince the industry sector? getting close to software?


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Hard to convince the industry sector? getting close to software? Gaining univariate resistance at what price?


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Target Scheme ‐ Evaluation


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Target Scheme ‐ Evaluation A variant by processing all three shares at the same time


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Target Scheme ‐ Evaluation


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Target Scheme ‐ Evaluation Original Design, 3MHz


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Measurement Setup


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Measurement Setup


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Measurement Setup


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Measurement Setup


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Measurement Setup


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Measurement Setup


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Measurement Setup

Standard Setup


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Measurement Setup

Standard SetupAmplified Setup


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Target Scheme – Evaluation (Standard Setup) Original Design, 3MHz


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Standard vs. Amplified Setup Exemplary Design


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SAKURA‐G


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SAKURA‐G


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Efficiency as a Factor


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Efficiency as a Factor


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Efficiency as a Factor Original Design, Standard Setup, 24MHz


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Summing Up / Future Issues


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Summing Up / Future Issues Cost of univariate resistance

– security‐performance tradeoff– processing the shares consecutively


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a light at the end of the tunnel by [pure] masking in hardware?


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a light at the end of the tunnel by [pure] masking in hardware?– slowly reaching the software performance?

• making a processor by giant hardware?


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• making a processor by giant hardware?– relatively easy ways to combine the leakages

• measurement setup & high clock freq.


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What to do when evaluating a countermeasure / product?


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What to do when evaluating a countermeasure / product?– without any addition/modification on measurement setup?

• not fair, the attacker may do it


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What to do when evaluating a countermeasure / product?– without any addition/modification on measurement setup?

• not fair, the attacker may do it

– with any sophisticated measurement setup?• not fair, its security relies on a univariate leak‐free scheme


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Thanks!Any questions?

Embedded Security Group, Ruhr University Bochum, Germany

[email protected]

on the simplicity of converting · 8/21/2013 · amir moradi, oliver mischke embedded security...

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