on wafer small signal characterization beyond 100 ghz for...

On wafer small signal characterization beyond 100 GHz for compact model assessment

Sebastien Fregonese#1, Marina Deng#1, Marco Cabbia#1, Chandan Yadav#1, Soumya Ranjan Panda #1&2, Thomas Zimmer#1

#1Université Bordeaux / CNRS, laboratoire IMS, FRANCE

#2IIT Madras, India

#1 [email protected]

WS-01 Recent advances in SiGe BiCMOS: technologies, modelling & circuits for 5G, radar & imaging

http://tima.univ-grenoble-alpes.fr/taranto/

- 2 -WS-01 - Recent advances in SiGe BiCMOS: technologies, modelling and circuits for 5G, radar and imaging

• Motivation

• EM simulation vs Measurement up to 500 GHz

• HBT measurement up to 500 GHz

• Conclusion and Outlooks

Outline


Motivation

Accurate S-parametermeasurements above 110 GHz =

big challenge

RF circuit/system design

Accurate compact modelsRelies on

Extraction of specific parametersValidation

Transistor HF Characterization Challenges


• Calibration & De-embedding Issues

Motivation

Standard procedure (2-step calibration)

Reference plane after calibration

Vectorial Network Analyzer (VNA)

Port 1 Port 2

mmW head mmW headRF probes

Impedance Standard SubstrateFrom Cascade Microtech

1Off-wafer

calibration on ISS



Motivation

Different electrostatic environment

calibration range of validity ?

Reference planeafter calibration

Ref. plane afterde-embedding(DUT terminals)

2On-wafer

de-embedding



Motivation

Different electrostatic environment


Reference planeafter calibration

Ref. plane afterde-embedding(DUT terminals)

Same electrostatic environment


2On-wafer

de-embedding

1On-wafer TRL

calibration


• S parameters measurement above 110 GHz requires to answer the following questions:

• Which calibration & de-embedding method should I use ?

• Do I really measure my DUT ? Impact of adjacent structures

Impact of probes

=> Need for reproducing measurement results with EM simulation tools

Motivation


EM simulation vs Measurement up to 500 GHz

SOLT on ISS De-embedding

Extraction of SOLT

parameters using ISS TRL

Simulation of :ThruReflect (open, Short) LinesLoad

Simulation of :DUTPad openPad short Intrinsic DUT

ISS SOLT


• Characterisation of the ISS calibration kit for SOLT


Interferometry image of the through from the ISS (GGB-CS15)

Data sheet of

CS15 delivered by Pico-probe GGB

industries used for 50-125 µm probe

pitch

EM simulation for 50 µm probe pitch (extracted from TRL at 60 GHz and 250

GHz)

Open 3.25fF 3.2-3.4fF

Short 2pH 1.5 pH-2.5pH

Load 1.5fF 1.4-2.2fF

Through 1.13ps 1.10ps


• Silicon test structures:


M1 Cu

M2 Cu

M3 Cu

M4 Cu

M6 Cu

M7 Alu

M5 Cu

Two thickcopper + onealuminiumlayer

Four thincopper layers

Infineon’s B11HFC BEOL

Reflect pad open

Line of 160µm

Thru of 50µm

Pad short

Transistor open Meander line.

Load

The probe pitch is 50 µm




Extraction of SOLT




ISS SOLT


• Pad short & Pad open


-4

-3

-2

-1

0

1

2

3

4

0 100 200 300 400 500

mag

(Sii)

(d

B)

freq (GHz)

Measurement with SOLT cal.

EM sim. with SOLT cal.

0

30

60

90

120

150

180

0 100 200 300 400 500

ph

ase(

S ii)

(°)

freq (GHz)



PAD SHORT after SOLT calibration

Measurement vs Simulation

-4

-3

-2

-1

0

1

2

3

4

0 100 200 300 400 500

mag

(Sii)

(d

B)

freq (GHz)



-120

-90

-60

-30

0

30

60

90

120

150

180

0 100 200 300 400 500p

has

e(S i

i) (°

)freq (GHz)



PAD OPEN after SOLT calibration

Measurement vs Simulation

Ref. plane

Ref. plane




Extraction of SOLT




ISS SOLT


• Calibration and de-embedding : transistor open


-3

-2

-1

0

1

0 100 200 300 400 500

mag

(S2

2)

(dB

)

freq (GHz)

Measurement Simulation with SOLT cal.

EM intrinsic

SOLT ISS

-180

-120

-60

0

0 100 200 300 400 500

ph

ase(

S 22)

(°)

freq (GHz)

Measurement Simulation

EM intrinsic

SOLT ISS

Ref. plane



TRL on wafer with Zc correction

Simulation of :ThruReflect LinesLoad

Simulation of :DUTPad openPad short

Intrinsic DUT

On wafer TRL

simulation


• Calibration and de-embedding : transistor open


-3

-2

-1

0

1

0 100 200 300 400 500

mag

(S2

2)

(dB

)

freq (GHz)

Measurement Simulation with SOLT cal.

EM intrinsic

SOLT ISS

-3

-2

-1

0

1

0 100 200 300 400 500

mag

(S2

2)

(dB

)

freq (GHz)


EM intrinsic

TRL on wafer

-180

-120

-60

0

0 100 200 300 400 500

ph

ase(

S 22)

(°)

freq (GHz)


EM intrinsic

SOLT ISS

-180

-120

-60

0

0 100 200 300 400 500

ph

ase(

S 22)

(°)

freq (GHz)


EM intrinsic

TRL on wafer

Ref. plane


• Calibration and de-embedding : meander line


-5

-4

-3

-2

-1

0

1

2

3

0 100 200 300 400 500m

ag(S

ij) (

dB

)

freq (GHz)


EM intrinsic

SOLT ISS

-5

-4

-3

-2

-1

0

1

2

3

0 100 200 300 400 500

mag

(Sij)

(d

B)

freq (GHz)


EM intrinsic

-200

-150

-100

-50

0

50

100

150

200

0 100 200 300 400 500

ph

ase(

S ij)

(°)

freq (GHz)


EM intrinsic

-200

-150

-100

-50

0

50

100

150

200

0 100 200 300 400 500

ph

ase(

S ij)

[°]

freq (GHz)


EM intrinsic

SOLT ISS

Ref. plane


• Limitation of the SOLT ISS parameters:• Frequency dependence

• Probe dependence

• Substrate to probe coupling• Probe dependence

• Cal-kit material and wafer material

• Limitation of the de-embedding

=> TRL on ISS is used to identify these 3 limitations



• SOLT on ISS and TRL ISS with pad-open pad-short de-embedding and on wafer TRL versus intrinsic simulation


-4

-3

-2

-1

0

1

0 100 200 300 400 500

mag

(S2

2)

(dB

)

freq (GHz)

On wafer TRL ZCISS cal TRL and de-embeddingISS cal SOLT and de-embedding

intrinsic

-180

-150

-120

-90

-60

-30

0

0 100 200 300 400 500

ph

ase(

S 22)

(deg

)

freq (GHz)

On wafer TRL ZCISS cal TRL and de-embeddingISS cal SOLT and de-embedding

intrinsic

• ISS SOLT and TRL give similar results on the phase but deviate slightly from the intrinsic result from 50 GHz

Deviation is due to electrostatic environment and/or de-embedding procedureSOLT calibration itself and parameters cannot explain the deviation of the

phase


• Impact of adjacent structures:


EM simulation @ 500 GHz

Too dense layout !


• Impact of adjacent structures:


Ref. plane

With adjacent devices in Thru,

Refl., Line and DUT

-2

-1

0

0 100 200 300 400 500

mag

(S2

1)

(dB

)

Frequency (GHz)

Measurement + TRL cal.

EM sim. +TRL cal.

-2

-1

0

0 100 200 300 400 500

mag

(S21

) (d

B)

Frequency (GHz)

Measurement + TRL cal.

EM sim. with neighboring structures +TRL cal.

Adjacent structures modifies the result


• Impact of probe topology• On wafer calibration (STMicroelectronics B55 technology)


EM sim. setup

IEEE ICMTS 2018IEEE ICMTS 2018

220 GHz Picoprobe model


• STMicroelectronics B55 technology• On wafer TRL + short-open de-embedding

• Improved test structures (Pads layout, more space between structures, …)

• Measurement vs HICUM compact model with substrate extension

Application to the HBT

-40

-30

-20

-10

0

10

20

30

0 100 200 300 400 500

Mag

(S)

[dB

]

freq [GHz]

HBT B550.09*4.8µm²VBE=0.85 VVCB=0 V

S21

S12

S11

S22

-180

-120

-60

0

60

120

180

0 100 200 300 400 500

Ph

ase(

S) [

°]

freq [GHz]

HBT B550.09*4.8µm²VBE=0.85 VVCB=0 V

S21

S12

S11

S22

Characterisation & modelling is uncertain above 350 GHz

HICUM Meas.


• STMicroelectronics B55 technology

Application to the HBT

-10

0

10

20

30

40

50

0 100 200 300 400 500

H2

1[d

B]

freq [GHz]

HBT B55 AE=0.09*4.8µm²VCB=0V

VBE=0.85V

-10

-5

0

5

10

15

20

25

30

35

40

0 100 200 300 400 500U

[d

B]

freq [GHz]

HBT B55AE=0.09*4.8µm²VCB=0V

VBE=0.85V

HICUMMeasurement HICUM

Measurement


• The simulation methodology has been proven to be able to accurately reproduce the impact of the measurement methodology and set-up

• ISS calibration (SOLT or TRL) with OS de-embedding is not accurate above 200 GHz

• Adjacent structure have an impact on measurement results => requires optimized layout

• HBT: On wafer TRL and especially SO de-embedding => to be verified above 350 GHz

Conclusion

The research leading to these results has received funding from the European Commission'sECSEL Joint Undertaking under grant agreement n° 737454 - project TARANTO - and therespective Public Authorities of France, Austria, Germany, Greece, Italy and Belgium.

Thank you



• Our recent references:

• S. Fregonese et al., Comparison of on-wafer TRL calibration to ISS SOLT calibration with open-short de-embedding up to 500 GHz, IEEE Trans. Thz Sci., 2019

• S. Fregonese et al., On-wafer characterization of silicon transistors up to 500 GHz and analysis of measurement discontinuities between the frequency bands, , IEEE Trans. on MTT 2018

• M. Deng, “RF Characterization of 28 nm FD-SOI Transistors Up To 220 GHz”, EUROSOI ULIS, 2019

• C. Yadav et al., On the Variation in Short-Open De-embedded S-parameter Measurement of SiGe HBT upto 500 GHz, 2019 GeMiC

• C. Yadav et al., Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz, 2019, ICMTS

References

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