IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 20001

INVITED PAPER Special Section on Analog Circuits and Related Topics

Low Voltage Analog Circuit Design Techniques: A Tutorial

Shouli YAN† and Edgar SANCHEZ-SINENCIO†,

SUMMARYLow voltage (LV) analog circuit design techniques are ad-

dressed in this tutorial. In particular, (i) technology considera-tions; (ii) transistor model capable to provide performance andpower tradeoffs; (iii) low voltage implementation techniques capa-ble to reduce the power supply requirements, such as bulk-driven,floating-gate, and self-cascode MOSFETs; (iv) basic LV buildingblocks; (v) multi-stage frequency compensation topologies; and(vi) fully-differential and fully-balanced systems.key words: analog circuits, amplifiers, transistor model, bulk-driven, floating-gate, self-cascode, NGCC frequency compensa-tion, fully-differential and fully-balanced systems.

1. Introduction

The market and the need to develop efficient portableelectronic equipment have pushed the industry to pro-duce circuit designs with very low voltage (LV) powersupply, and also often constrained to low power (LP)consumption. The last case always applies to im-plantable medical electronic devices. The trend is ad-dressed to both analog and digital circuits. This is atremendous challenge since many new products are notonly required to operate with 3V or less, but need tohave superior performance and lower cost to competein an industry with fast turn around time. This com-petition has also stimulated the creation of a number ofstartup companies, where circuit design ideas are vitaltools to contend.

In this tutorial, we discuss the key issues in lowvoltage analog circuit design. The new smaller sizeprocess technologies offer opportunities to operate athigher frequencies consuming less power. For ana-log circuits, this fact partially applies since it is oftenthe case that additional current is needed to keep thesame performance when the power supply voltage isdecreased. Furthermore, for sub-micron technology itwould not be possible to use voltage doublers to en-hance the circuit performance due to low breakdownvoltage of the transistors.

Another important design aspect is the transistorregion of operation. For instance, with transistors oper-

Manuscript received September 12, 1999Manuscript revised September 12, 1999

†The authors are with Analog and Mixed-Signal Center,Electrical Engineering Department, Texas A&M University,College Station, TX 77843-3126, U.S.A. This work hasbeen partially supported by the Mixed-Signal Group, TexasInstruments, Inc.

ating in strong inversion, it is often the case that morepower is used than the required to meet the specifi-cations. Optimal designs involve minimum power con-sumption and/or silicon area while meeting design spec-ifications. Designers should explore having transistorsoperating in non-conventional regions of operation. Theextreme cases of weak inversion and strong inversion of-ten do not provide a good tradeoff between frequencyresponse, power consumption and silicon area. Thuswe should consider a one-equation transistor model forall regions [1, Chapter 2], [2], [3], which allows design-ers to optimize the circuit performance at minimumcost. Next we will discuss how bulk-driven and floating-gate techniques can help to produce efficient LV circuitswith reduced power supply restrictions. Some of thebasic building blocks such as current mirrors, differen-tial pairs, and class AB output structures capable tooperate in LV are explored and discussed.

In conventional 5V analog circuits, the use of cas-code (stacking of devices) circuits yielding high out-put impedance is attractive and easy to use. However,for less than 2V supply, the cascode circuits are oftennot feasible due to the reduced voltage headroom avail-able. This implies that growing circuits vertically is notpractical for low voltage design, the natural option is togrow horizontally. However, this horizontal design styleimplies circuits in cascade require a sound design [3]–[5] to maintain stability and high performance. Thisis because cascade circuits have poles and zeros thatpotentially might yield an unstable system when theyare connected in closed loop. Thus, by judicious ma-nipulating pole and zero positions, a circuit meetingarbitrary specifications can be designed.

In low voltage analog design, fully-differential orbalanced structures are ubiquitously used due to theadvantages of higher CMRR and PSRR, lower even or-der distortion, and wider signal swing range. We willaddress this issue in Section 6.

2. Technology Considerations and an All Re-gion One Equation MOS Transistor Model

2.1 Technology Considerations

Threshold voltage is not proportionally reduced forscaled down technologies. A natural solution is theuse of a multi-threshold process technology. Unfortu-

2IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

nately, this kind of technology is more expensive andfrequently not easy to reproduce. Some design advan-tages can be obtained by using BiCMOS technology atthe expense of an additional cost, since more fabrica-tion steps are involved. It has been the case that de-signers using BiCMOS technology produce circuits withbetter performance than CMOS based designs. How-ever after some time, the CMOS designers come withingenious design techniques to match BiCMOS circuitperformance. The competition between these two tech-nologies will continue, in particular in high frequencies.For microwave frequencies GaAs technology is currentlyflourishing. However one competitive technology, theSiGe, is a serious contender especially for above 1.5GHz applications. Also SOI (silicon on insulator) isa hard-radiation tolerant technology with competitiveattributes in some applications.

2.2 All Region One Equation MOS Transistor Model

In the past, low power consumption usually was lesscritically considered among key design specifications.But today, both increased circuit density of current fine-line CMOS technology and battery-operated portableequipment necessitate low voltage low power systemdesign. For CMOS analog circuits, when the transis-tors operate in weak inversion region, gm/ID reachesthe maximum, hence the minimum power consumptioncan be achieved due to the small quiescent current atthe expense of large silicon area and slow speed. WhenMOS transistors operate in strong inversion, however,although good frequency response and small area areobtained, non-optimum larger power is consumed, andVDS(sat) is high. For most analog circuits, the besttradeoff among area, power and speed can be achievedwhen the transistors work in moderate inversion region[3]. But conventional MOS transistor models providedifferent sets of equations for weak and strong inver-sion regions [6], even in computer simulation tools [7].Although some complex bridging equations are used inthe intermediate region, large errors or discontinuitiesof the transistor small signal parameters are often un-avoidable. Moreover, it is impossible for circuit design-ers to predict circuit performance in moderate inversionwith simple hand calculations. Most designers often as-sume conservative ways to make the MOS transistorswork in strong inversion, with power consumption andspeed higher than needed, thus avoiding an optimal de-sign. In recent years, some attempts of MOS modelinghave been made to have one-equation model for all theoperation regions [1, Chapter 2] [2], [8].

A current based model with one-equation for allregions including weak, moderate, and strong inversionwith good accuracy was proposed in [1, Chapter 2], [2],which has been successfully applied in low power ana-log circuit design [1]–[3]. This physically based modelwhich preserves the structural source-drain symmetry

10−1

100

101

102

10−1

100

101

Normalized Power ConsumptionNormalized fT Normalized Silicon Area

Inversion Level ( )f

fT

f TN

orm

aliz

ed P

ower

Con

sum

ptio

n,

, a

nd S

ilico

n A

rea

i

Power Consumption

(Silicon area for a specific L)Aspect Ratio (W/L)

Fig. 1 Normalized power consumption, fT , and silicon areav.s. if .

and charge conservation of the MOSFETs has infiniteorder of continuity for all operation regions. In addi-tion to its computer-implemented version [9], it is alsoextremely useful for analog circuit design by hand cal-culations. The details of this model are beyond thescope of this paper. What we are interested in here ishow it can be used to optimize the circuit performancein terms of power consumption and speed. A useful setof design equations for a saturated MOSFET using thismodel is given by:

φtngmID

=2

1 +√1 + if

(1a)

if =IDIS

(1b)

IS = µnCoxφ2t

2W

L(1c)

fT ∼= µφt2πL2

2(√1 + if − 1) (1d)

VDS(sat)

φt∼= (√1 + if − 1) + 4 (1e)

W

L=

gmµCoxφt

1√1 + if − 1

(1f)

where, ID — the drain current of the MOS transis-tor, gm — the transconductance in saturation, n— theslope factor, φt — thermal voltage, and if = ID/IS —the inversion level of the MOS transistor.

MOS transistors work in weak inversion for if < 1,strong inversion for if > 100, in between is the mod-erate inversion. Small if requires large aspect ratioW/L and area, and large if means small area and highspeed but large current and power consumption [2], asdepicted in Fig. 1 for different tradeoffs between area,fT and power consumption. A general expression forVGS , if the MOSFET is saturated and VSB = 0, can be

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL3

written as

VGS = VT + nφt[√1 + if − 2 + ln(

√1 + if − 1)] (1g)

Eq. (1g) shows that, for strong inversion, VGSreduces to the well-known approximation (VT +√2nID/[µCox(W/L)]. For deep weak inversion VGS

becomes (VT +nφt[ln(if/2)−1]). Note that for a MOS-FET working in strong inversion, VGS = VT + a fewhundred of mV; for weak inversion, VGS is below VT ,typically by some tens of mV; and in moderate inver-sion, VGS is slightly above VT .

In [1, Chapter 2], [2], a simple common-sourceamplifier was designed using the above current-basedmodel. The model was further utilized in designing lowvoltage low power 3-stage and 4-stage NGCC [4] am-plifiers [3], a 5-fold of power consumption saving wasachieved in [3] with the same specifications of voltagegain, bandwidth, and settling time compared with [4].

For illustration purpose, a design procedure for anamplifier utilizing the current-based model may consistof: 1) Obtain the transconductance (gm) as a functionof GBW and load capacitance; 2) Determine fT fromthe speed specifications. Usually, fT should be 3 to 10times larger than the GBW or the highest frequency atwhich the circuit operates. 3) Obtain inversion level if

from fT (Eq. (1d)), i.e. if =(fT πL

2

µφt+ 1)2

− 1. 4) De-rive other parameters, such as, working currents, geom-etry ratios, and drain-source saturation voltages fromEqs. (1a), (1f), and (1e) respectively. Interested readersare referred to [1]–[3] for detailed information.

3. Circuit Strategies to Reduce Power SupplyConstraints

3.1 Challenges of Low Voltage Analog Circuit Design

Because the threshold voltage and drain-source satu-ration voltage of fine-line CMOS technologies do notscale down at the same rate as the supply voltage ordo not scale at all, with low supply voltage, analogdesigners face many difficulties and challenges due tothe limited voltage headroom. Some circuit structureswhich can only operate with higher supply voltage withdesirable properties and high performance lost their va-lidity in low voltage environment. Instead, alternativecircuit structures or even system topologies have to beinvestigated. Let us take a cascode structure as an ex-ample. Cascode and regulated cascode structures areubiquitously used in analog circuits operating in highersupply voltages, because of the high output impedanceand hence high voltage gain without degrading the fre-quency response [10]. We will compare the low voltageperformance of cascode and non-cascode structures [5],which are shown in Fig. 2. Assume that both ofMc andMs carry the same amount of current IL, VT = 0.75V ,and VDS(sat) = 0.2V (in strong inversion). To make M1

IL IL

vIN v

IN

VB1

VB2

VB

VB3

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 30

0.2

0.4

0.6

0.8

1

1.2

Norm

aliz

ed G

BW

( G

ain

Bandw

idth

)

1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 30

20

40

60

80

100

120

Power Supply Voltage

Norm

aliz

ed S

ize (

Mc

and M

s )

W/L ratio of cascode W/L ratio of non−cascodeGBW of cascode GBW of non−cascode

M1

M3

M4

M2

Ms

M1

McM2

RL RL

(a) (b)

(c)

VxVx

Mc

Ms

Ms

Mc

Fig. 2 Cascode and non-cascode structures, (a) A cascodegain stage plus output stage, (b) A simple gain stage plus outputstage, (c) normalized transistor size and normalized GBW (atnode Vx) v.s. power supply.

in Fig. 2(a) work properly, and to leave some marginfor mismatching, a slightly higher VDS than the mini-mum (VDS(sat)) is required. Let’s further assume thismargin voltage is VDS(margin) <= 0.1V . Since the volt-age swing (at Vx) of cascode structure is less than thatof the simple non-cascode structure, the W/L ratio ofMc is expected to be larger than that of Ms, in thatway both IL’s in Fig. 2(a) and (b) are equal. Fig. 2(c)shows the curves of the normalized minimum W/L ra-tios of Mc and Ms and GBW (at node Vx) v.s. supplyvoltage. We observe that the cascode structure intro-duces unreasonable Mc size increase and hence unde-sirable frequency degradation due to the large parasiticcapacitance when voltage supply drops below 1.5V. Ascascode structure is not suitable for low-voltage oper-ation, we have to use simple non-cascode structures insub-1.5V applications.

Because simple non-cascode stage has a relativelylow voltage gain (gm/go) compared with cascode struc-ture (with a gain of g2

m/g2o), we have to cascade simple

stages to obtain a comparable gain to that of cascodestructures. Amplifiers are designed such that when con-nected in closed loop they do not present stability prob-lems. This often implies, for the amplifier, to have onedominant pole close to the complex frequency plane ori-gin, and the rest of the poles located as far as possible

4IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

from the origin [6], i.e. parasitic non-dominant polesshould be placed at high frequencies. Typically push-ing poles to higher frequency implies increased powerconsumption, thus designers should determine the re-quired phase margin and settling time that satisfy re-quirements without spending more power than the nec-essary. With multistage amplifiers, because each stagecontributes one pole at comparable frequencies, the sta-bility condition becomes difficult, and clever frequencycompensation techniques have to be developed [4], [11],We will address this issue in Section 5.

Low supply voltage also poses challenges forswitched capacitor (SC) circuits, one of the most im-portant techniques for realizing analog signal process-ing, because of the difficulties involved in driving somecritical switches in the signal path [12], [13]. There area number of solutions for low voltage SC circuits, in-cluding [1, Chapter 10]: 1) using low threshold MOS de-vices; 2) voltage multiplier or clock boosting techniques[14]; and 3) switched Op Amps [13], [15], [16]. The firstis expensive and not compatible with main stream dig-ital CMOS technologies. Moreover, the switches have alarge sub-threshold leakage current when being turnedoff. The second is widely used in industry, however,it may not be able to be applied in future technologieswhich can not withstand the high boosted clock voltage.The third can only be utilized for low speed systems be-cause of the intrinsic delay involved in switching on andoff the Op Amps. Due to the limited space, we will notcover the SC design limitations [1, Chapter 10] furtherin low voltage environment.

Another issue for LV design is dynamic rangedegradation. Dynamic range is defined as the ratio ofmaximum allowable signal voltage swing (or power) un-der some distortion specifications, over the noise floor.Since the supply voltage, as well as the signal swing,decreases, the noise floor keeps at a relatively constantlevel, the dynamic range is degraded.

A transistor should conduct some biasing draincurrent to perform any signal processing task. For aMOSFET, we have to overcome the threshold voltageVT to make it operate. The threshold voltage VT doesnot scale down with the same rate as the maximumallowable power supply voltage when the feature sizeof modern CMOS processes decreases, mainly becauseof the sub-threshold current considerations for digitalcircuit in the mixed-signal environment [17] and thewide spread of VT value for sub-micron technologies[18]. There are two techniques which can partially over-come the difficulties introduced by the relatively highVT : 1) Bulk-driven MOSFETs, 2) Floating-gate MOS-FETs. Another useful structure for LV applications isself-cascode MOSFET, which could improve the out-put impedance without much degradation for fT andvoltage swing.

N Channel

n+

SiO2

P well

B S G D

N substrate

n+

Depletion layer

G

D

B

S

VB

M1

IB

vI

vO

IB

vO

vIJ1

(b)

(a)

Fig. 3 Bulk-driven MOS transistor, (a) cross section and sym-bol of an N-channel MOSFET in P-well technology, (b) bulk-driven MOSFET is similar to a JFET transistor.

3.2 Bulk-Driven MOSFETs

A. Guzinski et al proposed bulk-driven MOS transistorconcept in 1987 [19], as active components in an OTAdifferential input stage. It was later used in an OTA-Cfilter of a CMOS telephone circuit [20]. The originalpurpose of the bulk-driven differential amplifier was toyield a small gm and to improve linearity. In [21] a 1-VOp Amp was designed utilizing the depletion charac-teristic of the bulk-driven MOS transistors to have arail-to-rail common-mode input range and to meet thelow supply voltage requirement.

The cross section of an N-channel MOSFET struc-ture is illustrated in Fig. 3(a). For a conventional MOS-FET, conductivity of the channel, hence the drain cur-rent ID, is controlled by the gate-source voltage VGS .Bulk-source voltage VBS could also affect ID, whichis normally a parasitic effect, and may introduce un-wanted gmb and degrade the signal path. But if wekeep VGS constant as a bias voltage, and apply signalat the bulk gate (the P-well), we could obtain a JFETlike transistor (Fig. 3(b)). Note that we use gmb insteadof gm in the signal path, the former is considerably lessthan the latter by a factor of 0.2 to 0.4, and the inputcapacitance is (Cb,sub + Cbs) instead of (Cgs + Cgb).

Desirable characteristics of bulk-driven transistorsare: i) Depletion characteristics avoid VT requirementin the signal path, voltage swing for low voltage supplyis increased, and minimum operational supply voltageis pushed to its limit. ii) We can use the conventionalfront gate to modulate the bulk-driven MOS transistor.

Unfortunately, there are also some disadvantages:i) The transconductance of a bulk-driven MOSFET issubstantially smaller than that of a conventional gate-driven MOS transistor, which may result in lower GBWand worse frequency response. ii) The polarity of thebulk-driven MOSFETs is technology related. For a P

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL5

(N) well CMOS process, only N (P) channel bulk-drivenMOSFETs are available. This may limit its applica-tions. iii) The equivalent input referred noise of a bulk-driven MOS amplifier is larger than a conventional gate-driven MOS amplifier because of its smaller transcon-ductance. iv) Prone to turn on the parasitic bipolartransistors, which may result in a latch-up problem.

3.3 Floating-Gate MOSFETs

Another technique to reduce the supply requirementof low voltage analog circuit is the floating-gate tech-nique. Floating-gate MOS transistors have been usedin digital EPROM or EEPROM for decades, but theyare not so widely used in analog circuits. A number ofpapers have been published for applications of floating-gate technique in analog circuits, such as floating-gateCMOS analog trimming circuit [22], neural networkcomponents, multipliers [23], D/A converters[24] andamplifiers [25]–[27].

The layout and circuit symbol of a multi-inputfloating-gate MOSFET is depicted in Fig. 4. Thefloating-gate MOSFET is similar to a conventionalMOSFET in the sense that the floating-gate is equiv-alent to the gate of a conventional transistor, exceptthat the voltage of floating-gate VFG is not controlleddirectly but by the control gates through capacitancecoupling. The floating-gate voltage can be expressedas

VFG = (QFG + CFG,DVD + CFG,SVS + CFG,BVB

+n∑i=1

CGiVGi)/CΣ (2)

where QFG is the static charge on the floating-gate, and

CΣ = CFG,D + CFG,S + CFG,B +n∑i=1

CGi is the total

capacitance seen at the floating-gate.The drain current ID v.s. VGS characteristic is sim-

ilar to that of conventional MOSFET if we treat VFG,Sof the floating-gate MOSFET as VGS of a conventionalMOSFET. Note that because VFG is dependent on VDdue to the parasitic CFG,D, the output impedance isconsiderably degraded and is lower than that of theconventional MOSFET [1].

An exciting property of floating-gate MOSFET isthat the electric isolation from the floating-gate to othernodes is so ideal that the electric charge can stay therefor several years with the variation of less than 2% inroom temperature [1, Chapter 5]. We can change theequivalent threshold voltage seen from the control gatesby varying the amount of static charge on the floating-gate. The static charge QFG can be changed in threeways[1, Chapter 5]: 1) ultra-violet light shining, 2) hot-electron injection, and 3) Fowler-Nordheim (FN) tun-neling. In ultra-violet light, the SiO2 layer becomestemporarily conductive, and the static charge can leak

Poly I

Poly II

N Diffusion

Metal

VG1

VG2

VG3

S D

VG1

VG2

VGn

CG1

CG2

CGn

CFGB

CFGS

CFGD

(a) Layout

(b) Schematic Symbol

(c) Equivalent Circuit

VG1VG2

VGn

Fig. 4 Multi-input floating-gate MOSFET, (a) layout, (b)schematic symbol, (c) equivalent circuit

M1

M2vG

vD

vS

Fig. 5 Self-cascode MOSFET

away. Programming using hot-electron injection canbe easily controlled, but need a large current. FN tun-neling requires small current, however, a high voltagefrom 14 to 30V, depending primarily on the oxide thick-ness of the process, is required. By these programmingtechniques, we can change the equivalent VT seen fromthe control gates to have a low VT MOSFET, but therelatively complex programming circuits and/or higherprogramming voltage limit its low voltage applications.

Note that for MOSFETs with the same aspectratio and bias drain current, bulk-driven and multi-input floating-gate transistors have the same drain cur-rent noise [28] as the conventional MOSFETs, however,smaller equivalent transconductance of the former tworesults in a higher input referred noise voltage.

3.4 Self-Cascode MOSFETs

Self-cascode configuration [29] shown in Fig. 5 providesa high output impedance with larger voltage headroomthan the conventional cascode structures. The lower(upper) transistor M1 (M2) operates in non-saturation(saturation) region. For (W/L)2 >> (W/L)1, the cir-cuit behaves like a single M1 operating in saturationregion but without severe channel-length modulationeffects. The output resistance is roughly proportionalto (W/L)2/(W/L)1 and VDS(sat) = VGS −VT the sameas in a single MOSFET. Note that it is not necessaryto have different VT1 and VT2 for the circuit to operateproperly. However, it could help to improve the outputimpedance [30], [31] to have VT1 > VT2.

A number of excellent discussions from various as-pects on low voltage low power analog and mixed-signalcircuit and system design could be found in [1], [32].

6IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

4. Low Voltage Analog Building Blocks

In this section, we will discuss basic analog buildingblocks for low voltage design, including current mirrors,differential input stages, and output stages.

4.1 Low Voltage Current Mirrors

For modern CMOS technologies with shorter channellengths, smaller voltage gain (due to short channel ef-fect) and lower supply voltage impose many constraintson the performance and circuit structures of the currentmirrors.

Desirable characteristics of LV current mirrors are:i) low AC equivalent input resistance rin, and smallDC voltage drop at the input node; ii) high outputimpedance, thus the output current is independent onthe output voltage, whether in DC or AC; iii) low out-put compliance voltage†, such that maximum voltageswing at the output node is allowed; iv) good frequencyresponse for high frequency applications; v) a linearcurrent transfer ratio B. In most cases B should beconstant and ideally is set by the transistor geome-try ratios. In current-mode data converters, a precisetransfer ratio over a wide current range is required.

The simplest current mirror is shown in Fig. 6(a).Other current mirror structures are mainly focused onthe following design objectives: i) increase the outputimpedance but keep output compliance voltage as smallas possible; ii) lower input resistance; iii) decrease in-put DC voltage drop; iv) to have an accurate currenttransfer ratio.

Cascode or regulated cascode structures (Fig.6(b,c)) can be used [6], [28] to increase the outputimpedance. Fig. 6(b) is the basic cascode structureand it can be enhanced vertically to more levels [34]with the cost of increased compliance voltage. Reg-ulated cascode is a good technique to increase outputimpedance without degradation of output voltage swingat the expense of an extra amplifier (Fig. 6(c)), whichcan be an Op Amp [10] or a simple common-source volt-age gain stage [35]. There are a number of transistorlevel implementations of cascode and regulated cascodestructures (Fig. 6(e,f)), following the basic structures ofFig. 6(b),(c) and (d) [6], [28], [35], [36]. The symmetri-cal structure of Fig. 6(d,e,f) renders a more accuratecurrent transfer ratio depending on the matching prop-erty of the left half and right half of the circuit. Activeinput (Fig. 6(g,h))[33] could considerably lower the in-put impedance, and has a well controlled input biasvoltage, it can be used in some high precision applica-tions. Care must be taken to ensure the stability of the

†Compliance voltage is defined as the minimum DC out-put voltage drop at which the output branch of the currentmirror remains in saturation and still has a high outputimpedance [6, pp. 380-381].

Iin Iout

M1 M2

(W/L)1 (W/L)2

Vmirror Iout

McVcas

VmirrorMm

Iout

McVref

Vmirror

Areg

Mm

(a) (b)

(d)

(c)

(f)

(e)

(h)(g)

IoutVrefIin

Mc

MmM1

M2

Vmirror

Iin

MmM1

Mc

Iout

Vcas

M2

IB 4I B

M410

M310

Mc70

Mm80

IoutIB4I B

M810

M710

M570

M680

Iin

Vref

Aact

IoutIin

M1 M2

Iout

Iin Vref

M1Mm

Mc

Fig. 6 Current mirrors, (a) simple, (b) cascode output, (c)regulated cascode output, (d) symmetrical regulated cascodestructure, (e) one implementation of (d), (f) high swing cur-rent mirror, (g) active-input current mirror [33], (h) active-inputregulated-cascode current mirror [33].

(a) (b)

(d)

(c)

(e) (f)

Iout

Iin

M1 M3

IB IB

M2 M4

M5

IoutIin

M1 M3

M2 M4X

Iout

M1 M3

IB IB

M2Vcas

Iin

Iout

M1 M2

Iin

ROB

AFB

Iout

Iin

M1 M2

VddIB1

M3 M4

IB2

Vshift

Iout

Iin

M1 M2

Fig. 7 Low voltage current mirrors, (a) high swing currentmirror with input current injected to the source of M3, (b) Pro-danov’s structure [38], (c) Itakura’s structure [39], (d,e) Ramirez-Angulo’s current mirror with input level shift [40], (f) F. You’sstructure [41].

feedback loop [33], [37] in the active-input and/or reg-ulated cascode structures. Table 1 summarizes the keycharacteristics of simple, cascode (only output part),and active-input (only input part) current mirrors.

In addition to the structures in Fig. 6 which aresuitable for 3-V operation, there are a number of otherLV current mirrors. For some LV circuits, a low voltagedrop less than one VGS over the input node of the cur-rent mirror is required. Besides the active-input struc-ture (Fig. 6(g,h)) which can satisfy this requirementwith a properly selected Vref , some other structuresare illustrated in Fig. 7(a,b,d,e). Fig. 7(a) is similarto Fig. 6(f), whereas the input current is injected to

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL7

Table 1 Circuit characteristics of simple, cascode(only output), and active-input(onlyinput) current mirrors

Simple Cascode Reg. Cascode [28] Active Input [33]Input conductance gm1 + gds1

∼= gm1 / / gm1Aact

Output conductance gds2gds,mgds,c

gm,c

gds,mgds,c

Areggm,c/

DC input voltage VGS / / Vref

Min. output comp. voltage VDS(sat) 2VDS(sat) 2VDS(sat) /

the source instead of the drain of M2, with the advan-tage of a lower input voltage drop. For Fig. 7(b) and(c), the bottom transistors (M1 and M3) of the “cas-code” structure operates in the ohmic region, thus alower output compliance voltage by about 0.2 to 0.4V is achieved compared with conventional high swingcascode structure (Fig. 6(f)). An attractive feature ofFig. 7(b) is its extremely low input voltage drop dueto ohmic region operation of M1, which may be lessthan 0.1V. However, it is more sensitive to mismatchthan conventional topologies. An Op Amp is used inFig. 7(c) to force M1 and M3 to have the same VDShence the drain currents with the same value assumingthey have the same aspect ratio. A possible modifi-cation to the circuit in Fig. 7(c) is to inject the in-put current at the source of M2 (node X) to obtain avery low input voltage drop, with some minor changesto the biasing circuitry. The cost we have to pay forthe low voltage operation of Fig. 7(a)-(c) is a slightlydegraded frequency response. One attractive LV tech-nique to reduce headroom voltage limitations is the useof floating voltage sources (level shifting) [1], [40], [42].A level shifter is utilized in Fig. 7(d) to have a low inputvoltage (VGS − Vshift), one possible implementation isdepicted in Fig. 7(e) [40]. Another novel low voltagecurrent mirror mainly used to implement LV tail cur-rent of differential amplifiers was proposed [41] with anegative output resistance which is approximately given

by ro = −ROB(W/L)M1

(W/L)M2.

Observe that the simple current mirror (Fig. 6(a))has mainly one pole in the transfer function and be-haves as a first-order low-pass filter, other more elabo-rated current mirrors have multiple poles. For instance,the input stage of Fig. 6(f) and Fig. 7(a) behaves as asecond-order filter, and the designer should size tran-sistors and/or bias currents for optimal settling timeand frequency response, i.e., Q < 1/

√2 or equivalent

(gm2Cp2)/(gm1Cp1) < 1/2, where Cp1 and Cp2 are theparasitic capacitance at the drains of M1 and M2 re-spectively, and gm1 and gm2 are the transconductanceof these two transistors.

4.2 Differential Input Stages

Differential input stage plays an important role in theOp Amps or OTAs. Its design directly affects the per-formance of the whole amplifier such as input CMR

R2

R1

vIvO

(a)

vOvI

R1 R2

vOvI

(b) (c)

vI-

vI+

vO+

vO-R1

R1

R2

R2

(d)

Fig. 8 Op Amp configurations, (a) inverting configuration,(b) non-inverting configuration, (c) voltage follower (or voltagebuffer, a special case of (b)), (d) fully-differential configuration.

Table 2 Input common-mode swing of Op Amp configura-tions

Configuration Input common-mode voltage swingInverting ∼= 0

Non-inverting VSUP R1/(R1 + R2) †Voltage follower rail-to-railFully-differential vI,CM R2/(R1 + R2)

† VSUP is the total power supply voltage.

(Common-Mode Range) and CMRR (Common-ModeRejection Ratio). Fig. 8 illustrates Op Amp workingconfigurations, with input common-mode (CM) swingrequirements summarized in Table 2. Note that OpAmp non-inverting single-ended configuration, espe-cially the voltage follower, needs a large input CMswing. For inverting single-ended configuration, the in-put CM swing is nearly zero. Fully differential systemsusually have common-mode feedback (CMFB) circuitryto control their output CM voltages. Thus most ofthe amplifiers in a fully-differential system have a nearzero CM input swing, except the amplifiers which di-rect couple the signals coming from the outside worldat the very front of the signal processing chain. OTAsare often used in open loop, either single-ended or fully-differential configurations. For OTA single-ended con-figurations, one of the differential inputs usually di-rectly wires to AC ground, rendering an input CMswing as one half of the differential-mode (DM) swing.In fully-differential configurations, the CM input volt-age of an OTA or Op Amp is fixed by the CMFB cir-cuitry of the previous stage. In most cases, the inputCM swing for OTAs is not a critical issue. The ACground of the system should be carefully selected toyield a maximum input and output voltage swing.

For systems designed with 3V or higher supplyvoltage (more precisely, with VSUP > VTP + VTN +4VDS(sat)), N-P complementary rail-to-rail input stagecan be adopted, as shown in Fig. 9(a). The problemof this simple structure is that in the central part of

8IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

Table 3 Summary of some constant gm techniques for N-P complementary input stage

Principle ∆gm † Slew Rate Comments1 keep IN + IP constant [43], [44] 6% for weak inver-

sion, 40% for stronginversion

Constant Work well in weak inversion, not suitablefor high speed application

2 keep√

IP +√

IN [45], [46]

or√

KP,N( WL

)N IN +√

KP,P ( WL

)P IP

[47] constant

About 10%measured[47].

√2 times

variationDepends on quadratic characteristic ofMOSFETs, which is not accurately fol-lowed by short channel transistors, andalso has some error introduced by weakinversion operation in takeover.

3 4 times IN or IP when only one pairoperates [45]

+15% systematic vari-ation at the 2 takeoverregions

2 timesvariation

1) Same with case 2, but we can change 4to other numbers for short channel tran-sistors. 2) +15% systematic gm variation.

4 Back up pair with current switches [48]or 6-pair structure [49]

+20% systematic vari-ation at the 2 takeoverregions

Constant Constant slew rate but +20% systematicgm variation.

5 Maximum/minimum current selection[50]

5% (strong in-version) and 20% (weakinversion)

Constant Small gm variation (for strong inversion)and constant slew rate.

6 Electronic zener [51] 8% Constant Same with case 2.7 Level shift [52] ±4% after tuning, 13%

before tuningConstant gm variation is sensitive to VT and supply

voltage changes.

† ∆gm represents the gm deviations from its nominal value.

Vi+ Vi-

M1 M3 M4 M2

Mb1 Mb2IN

IPIB

Mb3Mb4

Cur

rent

Sum

mat

ion

To

subs

eque

nt s

tage

s

VC

MR

,P

Vdd

-Vss

VC

MR

,N

P Pair N Pair

VGS,M1,2

VDS(sat),Mb4

VDS(sat),Mb2

VGS,M3,4

(a) (b)

Common Mode Input Voltage ( vI,CM )

-Vss Vdd

gm Ngm P

Only P pairoperates Only N pair

operates

gm T, the sum ofgm N and gm P

Transconductance

Both P and Npairs operates

(c)

Vio

(mV

) CM

RR

(dB)

0

2

4

VI,CM(V)0 0.5 1.0-1.0 -0.5

60

70

80

906

CMRR

Vio

(e)

(d)

vI

Op Amp with CMdependent Vio

vO

Equivalent circuitwith ideal amplifier

vIvO

~

Nonlineardependency

Fig. 9 N-P complementary CMOS rail-to-rail input stage, (a)basic configuration, (b) CM swings of N and P pairs (CMRP andCMRN ), (c) gmT variations with input CM voltage, (d) the ef-fect of CM dependent input offset voltage, (e) Vi,cm and CMRRv.s. VI,CM of (d).

the CM swing, both of N and P pairs operate, ren-dering a total transconductance (gmT ) which is abouttwice of that when the CM voltage is close to eitherof the supply rails and only the P or N pair is operat-

ing. Constant transconductance (gm) rail-to-rail inputstage is necessary to have an optimized frequency com-pensation and better linearity. There are a number ofconstant gm techniques reported in literature, some ofthem are summarized in Table 3.

Because of the input offset voltage difference be-tween the N and P pairs, the input referred offset volt-age (Vio) of the input stage, hence, that of the wholeamplifier will change with the common-mode (CM) in-put voltage swing. The input offset voltages of the N(VioN ) and P (VioP ) pairs, consist of systematic offsetvoltage, introduced by signal path asymmetry, and ran-dom offset voltage, due to the mismatches of some criti-cal components. The dependence of input offset voltageVio on the CM voltage gives rise to total harmonic dis-tortion, or THD, at the output of the amplifier, whichcan not be suppressed by the external feedback loop,as shown in Fig. 9(d). This effect greatly degrades theTHD performance of the whole buffer amplifier. Nor-mally Vio variation could be several mV even when verycareful circuit design and layout have been performed.Assuming the input offset voltage variation is as low as2mV, and signal amplitude is 2.8Vp-p, the THD causedby the Vio variation could be as high as about -54dB,which is not sufficient for some high precision applica-tions. The direct consequence caused by CM dependentVio is the degraded CMRR, especially at the takeoverregion between N and P input pairs (Fig. 9(e)). A tech-nique to minimize the CMRR degradation is by reduc-ing the variation slope of the input offset voltage withthe input CM level [53]. This can be achieved by mak-ing the takeover region as large as possible. However,this is limited by the available headroom voltage whichbecomes a serious problem for LV applications.

For very low voltage supply (say 1.5V), to main-

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL9

VB

Vi+ Vi-

IB

Io+ Io-

(a)

M1 M2

IB

VB

Vi+ Vi-ViFG+

ViFG-

Io+ Io-

C1

C2 C2'

C1'

(b)

M1 M2IB

Io+ Io-

Vi-

Vi+

VB

(c)

Fig. 10 Floating-gate and bulk-driven MOS input stages, (a)floating-gate MOS input stage, (b) equivalent circuit of (a), (c)bulk-driven MOS input stage.

tain a rail-to-rail CM input voltage swing is extremelydifficult, because of the VGS requirement of MOSFET,which usually consumes a large portion of the supplyvoltage. For inverting configuration (single-ended), in-put CM swing is nearly zero. Although the input CMvoltage need to be close to VDD (for N input pair) orVSS (for P input pair) to make the input stage oper-ate in very low voltage environment, it is not a severeproblem as judicious voltage shifter [42] in the inputstage can be devised, especially for sampled data cir-cuits [15], [16]. For non-inverting configuration, espe-cially for voltage buffer, wide CM input swing is neces-sary.

Floating-gate MOSFET differential pair can beused to obtain a rail-to-rail input CM range [27], asillustrated in Fig. 10(a) with the equivalent circuit inFig. 10(b). VB can be directly wired to VDD for simplic-ity and the widest CM range. The rail-to-rail input CMrange is intrinsically obtained by attenuating the inputvoltage. Define kin as kin = C1/CΣ (Fig. 10(b)), theinput voltage attenuation factor. Where C1 is the ca-pacitance of the input control gate, and CΣ is the totalcapacitance seen from the floating-gate. Note that theinput referred noise is increased by the factor of 1/

√kin,

compared with that of non-attenuated conventional dif-ferential pair, assuming the same gm is achieved. Withfloating-gate static electric charge QFG and VB = VDD,to obtain an rail-to-rail swing, we need to satisfy

VSUP >=VFGS,M1 −QFG/CΣ + VDS(sat),IB

1− kin

=VT − VQ + VDS(sat),M1 + VDS(sat),IB

1− kin(3)

for VQ < VT − VSUP,D

where VQ = QFG/CΣ, which is the equivalent voltageshift introduced by QFG, and VSUP,D is the voltagedrop between VDD to the drains of the M1 and M2.The lower supply voltage rail-to-rail operation requiresa smaller attenuation factor kin. By altering VQ, thecircuit may yield a better low voltage performance. IfVQ = VT − VSUP,D, we can obtain

VSUP >=VSUP,D + VDS(sat),M1 + VDS(sat),IB

1− kin

Usually, VSUP,D is around 0.2 to 0.4V if folded-cascodestructure is used. Assuming all VDS(sat)’s are 0.2V (for

strong inversion), the minimum voltage supply is given

VSUP,min =0.7

1− kin(V )

Unfortunately, altering VQ often requires complicatedcircuits and/or high programming voltages [1, Chapter5].

Low voltage rail-to-rail CM input swing can also beachieved using bulk-driven differential pair (Fig. 10(c))[21]. This type of input stage requires very low volt-age supply, about (VGS + VDS(sat)). Its shortcoming isthat the transconductance changes dramatically (about2 times) with the CM input voltage.

Another technique to realize near rail-to-rail CMinput swing is using resistive dynamic level shift [54],[55], as depicted in Fig. 11. When supply voltage dropsto below (2VT +4VDS(sat)), the N-P complementary in-put stage (Fig. 9(a)) does not provide a rail-to-rail CMinput range, as illustrated in Fig. 11(a). The problemcan be solved if four level shifters are inserted betweenthe direct inputs and the gates of the input stage tran-sistors Fig. 11(b). Because active components cease tooperate under small voltage headroom, we have to re-sort to passive components, i.e. resistors, to realize thelevel shifters. The bipolar version of this concept wasproposed in [54], and a 1-V near rail-to-rail input andoutput bipolar Op Amp was successfully implemented.Without level shift, the minimum supply voltage fora bipolar N-P complementary input stage to render arail-to-rail input CM range is about 1.5V. Thanks tothe dynamic level shift, the amplifier [54] could still op-erate with near rail-to-rail CM input range when thesupply voltage reaches 1V. As illustrated in Fig. 11(c),the input voltage is applied to the P and N differentialpairs through voltage level shift resistors RL1 ∼ RL4.The level shift currents, as well as the level shift volt-ages (VSHIFT ), which are shaped through a feedbacknetwork (not in the figure), change with the CM inputvoltage, as shown in Fig. 11(d). Fig. 11(d) also illus-trates the curves of the base voltages of the input tran-sistors v.s. CM input voltage vICM . The input stagehas a constant gm over the whole CM range by con-trolling the tail currents of the NPN and PNP inputpairs to have a constant total current. When vICM isclose to the positive (negative) supply, N (P) pair op-erates with VSHIFT = 0, when vICM shifts towards thecentral part of the supply voltage, the level shift cur-rents as well as VSHIFT start to increase, rendering arelatively constant CM voltage at the N (P) pair baseswhich keeps the N (P) pair operative. VSHIFT comesto its maximum, when vICM reaches the central pointof the supply voltage.

A 1-V rail-to-rail input Op Amp of CMOS version(Fig. 11(e)) was implemented by Duque-Carrillo et al[55] following the idea of [54]. The working principleof the level shift current generator is illustrated in Fig.11(f). The level shift current v.s. vICM characteristic is

10IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

M2

M1

M4M3

vI+ vI-

V1

V2 V4

V3vSHIFT

vSHIFT

vSHIFT

vSHIFT

R10 R11

R8 R9

Q8 Q9

Q11

Q10Q2

Q1

Q4Q3

vI+ vI-

To

next

sta

ge

VB2

RL1

RL3

RL2

RL4

IL1 IL2

IL3 IL4

V1

V2 V4

V3

N-P complementary input stagewith dynamic level shift

Current summation

VC

MR

,PVdd

-Vss

VC

MR

,N

P Pair N Pair

VGS,M1,2

VDS(sat),Mb4

VGS,M3,4

VGS,M3,4

CM

vol

tage

Vdd

-Vss

N pair operates

P pair operates

Dead zone, neitherN pair nor P pairoperates

Vdd

-Vss

M2

M1

M4M3

vI+ vI-

RL1

RL3

RL2

RL4

N-P complementary input stagewith dynamic level shift

Current summation

vI+ vI-

Lev

el-S

hift

Cur

rent

Gen

erat

or

To

next

sta

ge

IL

Vdd

-Vss

M10 M12

M11

M9

M5M7

M8M6

ML1 ML2 ML3

ML4

ML6ML7 ML8

ML5

M14

M13M12

M11

vI+

vI-

IP

IN

IL

I L=

I MA

X -(

I P+

I N)

IMAX

IB

IB

0.2 0.4 0.6 0.8 1.0

VI,CM (V)

INIP

IL=IMAX -(IP+IN)

M2M1

vI+ vI-

RL1

vI+ vI-

Lev

el-S

hift

Cur

rent

Gen

erat

or To

next

sta

geIL

Vdd

-VssM5

M7

M8M6

IB IBITAIL

ML1ML2 ML3

ML4

ML6ML7 ML8

ML5

(a)

(b)

(c)

(d)0.2 0.4 0.6 0.8 1.0

VI,CM (V)

VI,CM

V1 and V 3

V2 and V 4

V1~V 4 andVSHIFT (V)

0.4

0.2

0.6

0.8

1.0

VSHIFT

(e)

(f)

(g)

(h)

(i)

0.2 0.4 0.6 0.8 1.0

IL

V I,CM (V)

Fig. 11 Rail-to-rail input stage with dynamic level shift, (a) the N-P complemen-tary input stage (Fig. 9(a)) has a dead zone in the central part of the CM swing whenVSUP < 2VT + 4VDS(sat), (b) the problem can be solved by four level shifters, (c) 1-Vbipolar rail-to-rail input stage [54], (d) V1 ∼ V4 and VSHIF T v.s. CM input voltage, (e)1-V CMOS rail-to-rail N-P complementary input stage [55], (f) the working principle oflevel-shift current generator in (e), (g) IP , IN , and IL v.s. vICM , (h) rail-to-rail P-channelinput stage [55], (i) level-shift current v.s. vICM in (h).

shown in Fig. 11(g). The transconductance of this am-plifier is not constant due to its simple design. AnotherOp Amp with a rail-to-rail CMR for a 1-V operationwas implemented in the same paper [55] only with a Pdifferential pair. Figs. 11(h) and (i) show the circuitschematic and level-shift current characteristics, respec-tively. The distortion performance is much better thanin the previous case of Fig. 11(e), as a consequence ofonly using one differential pair, and therefore, no prob-lem with the offset voltage variation exists. However,the price paid is a more difficult design, high input off-set current, and low input impedance. The problem ofthe resistor area is more critical in the approach rep-resented in Fig. 11(e) compared with Fig. 11(h), 4 re-sistors are used instead of 2. Note that the input CMrange is reduced within the supply rails by the compli-ance voltages of the level current sources, usually, oneVDS(sat) if simple non-cascode structures are used.

4.3 Low Voltage Output Stages

According to the types of loads, the driving capabilityof the output stages differs. For switched capacitor cir-cuits which have high impedance capacitive loads, class

A output stage is a good choice. Simple non-cascodecommon-source amplifier can be used, as well as thecascode and regulated cascode structures (Fig. 6(b)-(d)) to obtain a large voltage gain at the expense ofreduced output swing [10]. For other applications, es-pecially when the amplifier needs to drive off chip lowresistive or high capacitive load, like earphone, class Bor class AB output stage has to be utilized to have alarge driving capability, and at the same time, a smallquiescent current to save power especially in battery op-erated equipment. The output stage usually consumesmost of the power of the amplifier in such cases. For lowvoltage designs, a rail-to-rail output swing is desirableto efficiently utilize the power supply voltage.

Common-drain voltage follower output stage (Fig.12(a)) is rarely used in low voltage design due to itssmall output voltage swing as a result of stacking ofVGS,P and VGS,N . Instead, we have to use common-source class AB configurations (Fig. 12(b)). Comparedwith the common-drain voltage follower, this kind ofoutput stage has a higher output impedance, and usu-ally a higher voltage gain. For Fig. 12(b), some re-quired or preferred characteristics are: i) a large enoughtransconductance to satisfy the stability condition [4];

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL11

(a) (b) (c) VIN

IQ quiescent current

IP

IN

IMIN

IP, IN, and |IO|

|IO |

|IO |

vI,P

vI,N

vO

Mn

Mp

VB

VB=|V GSP |+V GSN

Vdd

-Vss

vO

vI,N

vI,P

Mn

Mp

Vdd

-Vss

IP

IN

IO

Fig. 12 Class AB output stage, (a) common-drain voltagefollower (can not be used in low voltage amplifiers), (b) common-source structure which features a rail-to-rail swing, (c) idealinput-output transfer characteristic for class AB output stage.

ii) small quiescent current IQ and large output currentwhen driving heavy load (i.e. small resistance or largecapacitance) to fully utilize the power from the volt-age supply; iii) rail-to-rail output swing as discussedbefore; iv) the output stage should have a fast switch-ing speed or a small switching delay between the N andP transistors, in order to minimize crossover distortionat high frequencies. The switching delay is introducedby charging and discharging the parasitic gate capaci-tors of the output transistors. When one transistor isturned on and driving the load, the other transistor cannot switch off completely, instead, it should conduct asmall amount of current for fast turn-on at next halfof the signal period. The ideal input output transfercharacteristic is shown in Fig. 12(c).

There are basically two categories of the CMOSclass AB output stage depending on how the quiescentcurrent is controlled: i) without feedback loop [56], [57],and ii) with feedback loop [5], [43], [45]–[47], [58], [59].Usually, the latter has a better accurate control overthe quiescent current and can operate at lower supplyvoltage, but with a reduced speed and may have stabil-ity problem because of the feedback loop.

Monticelli’s class AB output structure [56] asshown in Fig. 13(a) is widely used in low voltage de-signs. The input currents iI1 and iI2 can be obtainedfrom simple or cascode transconductor illustrated inFig. 13(b and c), which can be further improved byregulated cascode structure similar to Fig. 6(c) to havea higher gain. One desirable property of this struc-ture is that, with a sound design, the output transis-tors will never cut off, and it can have a larger volt-age gain depending on the impedance of the currentsources IB ’s and the output impedance of the driv-ing circuitry. The minimum supply voltage require-ment of this structure is (2VT + 3VDS(sat)), which isabout 2.2V for VT = 0.75V . But with the minimumvoltage supply, the driving capacity is near zero, be-cause the over-drive voltage for the output transistorsis only (VSUP − 2VT − 2VDS(sat)). One nice analy-sis of this structure by R. F. Wassenaar et al can befound in [1, pp. 264-266]. The bias currents IB ’s canbe merged with previous driving stage, possibly a rail-to-rail constant gm input stage, with the advantage of

(a)(b)

(c)

iI1

iI2

IB IB

IBIB

M2

M1

M4

M3

M5

M6

Mp

Mn

Vdd

-Vss

vO

M3 M4

M1 M2

Mb

IB

vI

to iI1

to iI2

Vdd

-Vss

M3A M4A

M1A M2A

MbA

IB

vI

to iI1

to iI2M1B

M2BVBN

VBP

M3A

M4AMbB

Vdd

-Vss

Vdd

-Vss

vO

VBP

VBN

IBIB3

IB IB3

Mp3

Mn3Mn2

Mn1

M2

M1

Mp2

Mp1

M3

M4

iI1

iI2

IB2

IB2

(d)

M3 Vdd

-Vss

M4 Mp1

Mp

Mp2

Mn2

Mn1

Mn

M1 M2

Mb

IB

VBN

VBP

vI

vOA

B

1:m

1:m

(e)

Fig. 13 Class AB output stage without negative feedbackloop, (a) Monticelli’s class AB output stage[56], (b) simple and(c) cascode input transconductors for (a), (d) You et al’s classAB output stage[57], (e) a new class AB output stage.

compact circuit structure and lower current consump-tion [44], [60].

You et al’s structure [57] illustrated in Fig. 13(d)has a minimum supply voltage of (VT + 2VDS(sat))(about 1.2V for VT = 0.75V ) and has a very goodclass AB behavior. In this circuit, Mn2 (Mp2) has asmaller aspect ratio (W/L) than Mn1 (Mp1). In qui-escent condition, Mn1 and Mn2 (Mp1 and Mp2) workin saturation region, Mn1 and Mn (Mp1 and Mp) forma current mirror with the current transfer ratio of m.When VA and VB increase (decrease) due to the in-put voltage change, the incremental resistance at nodeB (A) tends to increase as Mn1 (Mp1) will be drivenout of saturation to linear region due to the increase ofVGS,Mn2 (VSG,Mp2), a larger voltage gain will result atnode B (A). The price paid is its relatively low gain,because of the low impedance at node A and B in Fig.13(d).

A new class AB structure is proposed and de-picted in Fig. 13(e). This circuit has some similar-

12IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

M1 M2

Mn

Mp

M4M3Mb

Class ABfeedback control

( nonlinear )

IB

vI

vO

Vdd

-Vss

vB

vAiFB,A

iFB,B

iP

iN

iO

M1 M2

Mn

Mp

Mp1

Mn1

M4M3Mb

Class AB currentfeedback control

( nonlinear )

IB

vI

vO

Vdd

-Vss

vB

vAiFB,A

iFB,B

1:m

1:m

iP

iN

iO

iP1=iP/m

iN1=iN/m

(a) (b)

Fig. 14 Class AB output stage with negative feedback loop,the class AB control block may sense the vGS (a) or drain cur-rents (b) of the output transistors.

ity with Monticelli’s structure with improved over-drive voltage for the output transistors by VT , whichis VSUP − VT − 2VDS(sat) for our proposed structure,whereas, VSUP −2VT −2VDS(sat) for Monticelli’s struc-ture, with the cost of a slightly increased bias current.This improvement is very desirable in low voltage ap-plications due to the increased driving capability.

The characteristics of these three class AB struc-tures are summarized in Table 4.

The working principle of the class AB control witha feedback loop is depicted in Fig. 14. The class ABcontrol block may sense the vGS (Fig. 14(a)) or thedrain currents (by Mn1 and Mp1, Fig. 14(b)) of theoutput transistors, and generates currents iFB,A andiFB,B (usually iFB,A = −iFB,B) and feeds them backto some high impedance nodes in the signal path, mostoften, the gates of the output transistors. Note thatthe common-mode voltage of VA and VB controls thedifference of iP and iN , which actually is the outputcurrent iL; whereas the difference of VA and VB con-trols the common-mode current of iP and iN , whichis the quiescent current of the output transistors. Theclass AB feedback control intrinsically has a nonlinearbehavior, which can be implemented by nonlinear cir-cuitry. There are several implementations of the classAB control block in Fig. 14(a)(b), mainly including,i) minimum selectors [45], [59], [61], which are derivedfrom [58], and ii) MTL (MOS Translinear Loop) [62]based [1, pp. 259-263], [46], [47].

5. Multi-Stage Frequency Compensation [4]

In Section 3.1, we have discussed the difficulties in-volved in the design of high gain very low voltage am-plifiers because of the stability considerations of multi-stage structures. NGCC (Nested Gm-C Compensa-tion) [4] is an excellent multi-stage frequency compen-sation technique which could lead to a simple designprocedure and better predictable performance com-pared with NMC (Nested Miller Compensation) [11]and other multi-stage frequency compensation tech-niques. We will reformulate the equations in this sec-tion by considering the parasitic capacitors in the in-ternal nodes, since in LV LP design, transistors usually

work in moderate inversion region, internal parasiticcapacitance frequently can not be ignored. The newequations presented in this section could render opti-mized smaller values of frequency compensation capac-itors as well as the transistor transconductances. Hencea low power design, meeting the constraints of noise andmatching considerations, is feasible.

Fig. 15(a) is a simple 2-stage amplifier without fre-quency compensation. Although the DC voltage gainachieved is

gm1gm2

go1gL, which is higher than that of one

stage non-cascode amplifier, there are two poles presentwhich are located at: ωp1 = go1/Cp1 and ωp2 = gL/Cp2.Miller frequency compensation capacitor Cm can beadded to yield a one dominant pole frequency response,as shown in Fig. 15(b). The gain can be expressed as

Av(s) = A01− s/z

s2/(p1f2) + s/p1 + 1(4)

where A0 =gm1gm2

go1gL, z =

gm2

Cm, p1 =

gm1

CmA0=

f1

A0,

f1 =gm1

Cm, f2 =

gm2

CL(1 + Cp1/CL + Cp1/Cm).

One RHP (Right Half Plane) zero z =gm2

Cmis in-

troduced due to the direct high frequency signal paththrough Cm, which degrades the stability of the am-plifier in close loop. A gmf1 feedforward path couldbe used to eliminate the RHP zero. This techniqueis depicted in Fig. 15(c). The transfer function of theamplifier is still like Eq. (4), but the zero changes to

z =1

Cmgm2

− gmf1(Cm + Cp1)gm1gm2

When gmf1 = gm1Cm

Cm + Cp1, z goes to ∞, thus Eq. (4)

yields

Av(s) = A01

s2/(p1f2) + s/p1 + 1(5)

We can increase the voltage gain A0 by addingmore stages. Extending two-stage amplifier to three-stage we can obtain the structure as illustrated inFig. 15(d). The topology can be further extendedin a nested fashion to n stages as depicted in Fig.15(e). Generally, for an n-stage NGCC amplifier, de-

fine ki =CpiCmi

and mi =CmiCL

(i from 1 to n− 1), when

gmfi = gmiCmi

Cmi + Cpi(i from 1 to n− 1), the transfer

function of the amplifier is

Av(s) =A0

sn

p1∏

ni=2 fi

+ sn−1

p1∏n−1

i=2 fi+ · · ·+ s2

p1f2+ s

p1+ 1

(6)

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL13

Table 4 Characteristics of the class AB output stages illustrated in Fig. 13.

Monticelli’s [56] You’s [57] ProposedMin. supply voltage 2VT + 3VDS(sat) VT + 2VDS(sat) 2VT + 3VDS(sat)

Max. Vov of output transistors VSUP − 2VT − 2VDS(sat) VSUP − VT − VDS(sat) VSUP − VT − 2VDS(sat)

Voltage gain (Av) High Low HighCan Av be improved by cascode? Yes No Yes

CL

gL

gm1vi vo

Cp1 go1

gm2

CL

gL

gm1vi vo

Cp1 go1

gm2

Cm

CL

gL

gm1vi vo

Cp1 go1

gm2

Cm

gmf1

CLgLgm2

vi vo

gm3

Cm2

gmf1

Cm1

gmf2

gm1

CL

gLgm(n-1)

vi vo

gmn

Cm(n-1)

gmf1

Cm2

gmf(n-1)

gm1 gm2

gmf2

Cm1

(a) (b)

(c)

(e)

(d)

Fig. 15 Two-stage cascade, Miller compensated, and NGCC(Nested Gm−C Compensation) amplifier topologies, (a) 2-stagecascaded amplifier, (b) Miller compensated 2-stage amplifier, (c)Gm − C feedforward principle, (d) 3-stage NGCC amplifier, (e)n-stage nested Gm − C compensation topology.

where A0 =

(n−1∏i=1

gmigoi

)gmngL

, p1 =gm1

Cm1A0=

f1

A0,

f1 =gm1

Cm1, fi =

gmiCmi

11 + ki

(i from 2 to n − 1), and

fn =gmnCL

1(1 +

∑n−1i=1

miki

1+ki

)(1 + kn−1)

.

Detailed NGCC amplifier design methodology, sta-bility, bandwidth and settling considerations, as well asCMOS implementations and experimental results, arefound in [3], [4].

6. Fully Differential and Fully Balanced Sys-tems

In mixed-signal analog/digital systems, the switchingoperation of the digital circuits is extremely harmful tothe analog subsystem, since it pollutes the power supplyvoltage as well as substrate potential of the chip, and

couples to the analog circuits through electro-magneticeffects. Most digital noises are present in common-mode fashion, thus fully-differential configurations arehighly desirable for low voltage systems since it is in-trinsically immune to common-mode noises. Other ad-vantages of fully-differential configuration are highersignal voltage swing and lower even order distortion.

The input and output signals of a fully-differentialsystem can be either voltage or current. In our con-text, we only discuss voltage-mode circuits. For afully-differential system as shown in Fig 16(a), thedifferential-mode (DM) and common-mode (CM) inputand output voltages are defined as, vI,DM = vI+ −vI−,vO,DM = vO+ − vO−, vI,CM = (vI+ + vI−)/2 andvO,CM = (vO+ + vO−)/2. Where vI,DM , vO,DM arethe DM input and output voltages, respectively. vI,CMand vO,CM are the CM input and output voltages.

For an amplifier with simple resistive feedback(Fig. 16(b)), the DM voltage gain is given by,

Av,DM,cl =vo+ − vo−vi+ − vi−

=Av,DM,ol

R2R1+R2

Av,DM,olR1

R1+R2+ 1

∼= R2

R1(7)

where Av,DM,ol is the DM open loop voltage gain,whereas Av,DM,cl is the DM close loop voltage gain.Observe that, the output common-mode (CM) volt-age, (vO+ + vO−)/2, can be any value and the cir-cuit still remains in equilibrium condition. The feed-back network in Fig. 16(b) only affects the differential-mode (DM) signal, the CM output voltage remains inopen loop and is not well defined. In practice, theCM output voltage has to be fixed to a certain value,such that the output stage is not saturated or cut off,thus the DM signal can reach its maximum voltageswing. Therefore a feedback loop which controls theCM component of the output voltage, called common-mode feedback (CMFB), has to be inserted into thefully-differential system. The conceptual model, usingsingle-ended amplifiers, of a fully-differential Op Ampwith CMFB loop is shown in Fig. 16(c). The CMFBloop is redrawn in Fig. 16(d) with the CM voltages be-fore CMFB (v′O,CM = (v′O++v′O−)/2) and after CMFB(vO,CM = (vO+ + vO−)/2).

The DC CM output voltage is set to VREF due tothe CMFB amplifier in the negative feedback loop, thusthe CM output voltage signal can be expressed as

vO,CM =v′O,CM

ACMFB + 1(8)

14IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000

(a)

(b)

(c)

(e) (f)(g)

(d)

FullyDifferential

System

vo+

vo-vi-

vi+

vi-

vi+

vo+

vo-R1

R1

R2

R2

A

vI-

vI+

vO+

vO-

(vo+

+v o-

)/2 Output CMVoltage

Extraction

VREF

A' CMFBvO,CM

(vO++vO-)/2

vO+

vO-

rp

rpCp

Cp

vI,DM

-vI,DM

Gain stages shared by DM and CM

CM first stage

DM first stage

DM first stage

VREF CLgm3

vO-gm4

Cm3vI,DM

gmf3

Cm2

Cm1

gm2gm1D

gmf2

gmf1D

CLgm3vO+

gm4

Cm3-vI,DM

gmf3

Cm2

Cm1

gm2gm1D

gmf2

gmf1D

VREF

vERR

gmf1C

gm1C

gm1C

gmf1C

(vO+ +vO- )/2- VREFVREF

v'O,CM=(v'O+ +v'O-)/2

vO,CM =(vO+ +vO-)/2

ACMFB

vI-

vI+

vO+

vO-

v'O+

v'O-

(vo+

+v o-

)/2VREF

Main AmplifierCMFB loop

ACMFB

vO,CM

CM OutputVoltage

Extraction

Fig. 16 Fully differential and fully-balanced systems, (a) fully-differential system, (b)a conceptual fully-differential amplifier, (c) conceptual common-mode feedback (CMFB)working principle, (d) simplified diagram of CMFB circuit, (e) CMFB implementation prin-ciple, (f) transform single-ended amplifiers to fully-differential one by simple modification,(g) an example: a fully-balanced NGCC amplifier.

The output CM voltage is attenuated by (ACMFB+1),where ACMFB is the gain of the CMFB amplifier. Notethat Fig. 16(c) can never be used in a practical design,except for one-stage amplifiers. For multi-stage ampli-fiers, because of the CM voltage deviations at the in-ternal (high impedance) nodes, the voltage gain stagesmay be saturated or cut off by the CM voltage offset.We have to apply a CM correction signal (current) tosuitable internal nodes of the amplifier, as shown in Fig.16(e∼f). In this way, all the stages of the amplifier willbe working properly, even if there is a large CM offsetfrom the first stage of the DM amplifier.

Fig. 16(d) indicates that the CM amplifier worksin unity-gain feedback configuration, the stability of theCM loop must be ensured. The stability condition issimilar to that of the main DM amplifier, as long asthe main DM amplifier is unity gain stable. In prac-tice, it is very desirable to achieve similar performancein DM and CM loops. For that reason, both loopsshould share most of the circuitry (Fig. 16(e-f)). How-ever, care should be taken since the CM loop alwayshas some extra poles or zeros introduced by the CMextractor circuitry, especially for high frequency appli-cations. Fig. 16(f) shows that except for the first stage,all other stages are shared by the CM and DM chan-nels. Thus, we just need to copy the input stage fromthe fully-differential main amplifier to the single-ended

(but with two parallel channels) CMFB amplifier.Motivated by the above analysis, the NGCC am-

plifier was extended from single-ended version to fully-differential version [63], by copying the input stage ofthe single-ended NGCC amplifier to the CMFB chan-nel, i.e., we add input transconductor gm1C and gmf1C

for the CMFB amplifier. Good symmetry between DMand CM channels results, as they have the same NGCCtopology. A general design methodology was indepen-dently proposed by Czarnul et al [64] to extend single-ended amplifier to fully-balanced version.

To make the CMFB amplifier and the main dif-ferential amplifier to yield the same frequency response(i.e., the same GBW), it is imposed that

gm1D =gm1

2(9a)

gmf1D =gmf1

2(9b)

and

gm1C = gm1 (9c)gmf1C = gmf1 (9d)

where gm1 and gmf1 are the first stage transconduc-tances of the main and feedforward branches of single-ended NGCC amplifier, as depicted in Fig. 15.

The output CM voltage extractor can be imple-mented via an RC voltage divider for Op Amps, as

YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL15

(a)

(b)

(c) (d)

R R

C C

vO+ vO-

vO,CM

R R

C C

Vdd

-Vss

IB IB

vO+ vO-

vO,CM

M1 M2

vO+

vO-

IB

VREFM1 M2

I1 I1

iERR =I1-I2

VddVB,CM =aV O,CM +b

VREF

-Vss -Vss

M1 M2 M3 M4vO+ vO-

M5 M6

IB IB

Fig. 17 Common-mode voltage detector schemes, (a) RC volt-age divider, (b) common-drain voltage follower and RC volt-age divider, (c) balanced double-differential-pair structure, (d)floating-gate common-mode voltage detector.

shown in Fig. 17(a). But it is not suitable for OTAsbecause the high output impedance is degraded by theloading effect of the RC components. Several high in-put impedance CM extractor have been proposed [65](Fig. 17(b-c)) at the expense of limited DM and/or CMswing and nonlinearity. In fact, for very low voltageapplications, the conventional high-output impedanceCM extractors are not able to operate properly since theamplifier output signals are not large enough to turn-onany MOSFETs. In such cases, one viable solution [42]consists in shifting and attenuating these signal via pas-sive resistor voltage dividers at the expense of reducingthe input resistance of the CM detector. Note that theoutput signal for the balanced double-differential-pairstructure (Fig. 17(c)) is a bias voltage (VB,CM ) capableto generate the bias currents to be injected to appro-priate nodes. The small signal correction voltage ofVB,CM is vb,cm = (vo+ + vo−)gm1/gm6. The high inputimpedance is obtained at the cost of limited DM swing,which is determined by the (VGS − VT ) of M1∼M4 un-der quiescent conditions, and nonlinearity due to thesecond-order effects. A proposed simple CM extractionscheme using floating-gate techniques is illustrated inFig. 17(d). vO+ and vO− have the same coupling ca-pacitance to the floating-gate of M1, thus we can obtainthe average of vO+ and vO− at the the floating-gate, andcompare with VREF . iERR = gm(vCM − VREF ) is theerror current which is proportional to (vCM − VREF ).iERR could be applied to some nodes or mirrored as acorrection current. This CM scheme has a wide linearrange which is not limited by DM swing between vO+

and vO−. A related structure independently developedhas been reported in [66].

One alternative technique to implement a fully-differential system using single-ended Op Amps isvia common-mode feedforward (CMFF) [64]. SimilarCMFF technique was used for pseudo-differential OTAdesign in [12].

7. Conclusions

A number of topics concerning low voltage analog cir-cuit design were reviewed. The one-equation MOSFETmodel for all operation regions is an excellent tool to op-timize circuit performance between different tradeoffs,such as power consumption, silicon area and speed, forLV LP analog design. Although there are some perfor-mance degradations for the bulk-driven and floating-gate MOSFET transistors, they are very useful com-ponents in specific LV applications. Self-cascode struc-ture is a viable way to increase the output impedance ofshort channel transistors. We also reviewed a numberof key building blocks for LV analog circuits. Then, wereformulated the NGCC equations for designing LV LPmulti-stage amplifiers. Fully differential and balancedsystems are revisited in the last part of this paper.

Acknowledgment

The authors want to express their sincere thanks toProf. Takahiro Inoue and his group for the technical,moral and financial supports for this invited paper.We also wish to thank Drs. Schneider, Galup-Montoro,Duque-Carrillo, Cilingiroglu and Ramirez-Angulo fortheir valuable comments and suggestions.

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Shouli YAN was born in Anqiu, P.R. China, in January 1972. He receivedthe B. S. degree in Electronic Engineer-ing and M. S. degree in Computer Sci-ence and Engineering from Shanghai JiaoTong University, P. R. China in 1992 and1995, respectively. He worked as a lec-turer and researcher at Electronic Engi-neering Department of the same univer-sity from 1995 to 1997. Currently he ispursuing his Ph.D. degree in the Depart-

ment of Electrical Engineering, Analog and Mixed-Signal Center,Texas A&M University, College Station. His research interest isin the area of low voltage VLSI analog and mixed-signal circuitdesign. E-mail: slyan@ee.tamu.edu

Edgar SANCHEZ-SINENCIOwas born in Mexico City, Mexico, in Oc-tober 1944. He received the degree incommunications and electronic engineer-ing (Professional degree) from the Na-tional Polytechnic Institute of Mexico,Mexico City, the M.S.E.E. degree fromStanford University, CA, and the Ph.D.degree from the University of Illinois atChampaign-Urbana, in 1966, 1970, and1973, respectively. He worked as a Re-

search Assistant at the Coordinated Science Laboratory, Univer-sity of Illinois (1971-1973). In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nip-pon Electric Company, Ltd., Kawasaki, Japan. From 1976 to1983 he was the Head of the Department of Electronics at theInstituto Nacional de Astrofisica, Optica y Electronica (INAOE),Puebla, Mexico. He was a Visiting Professor in the Departmentof Electrical Engineering at Texas A&M University, College Sta-tion, during the academic years of 1979-1980 and 1983-1984. Heis currently the TI Chair Professor in Analog Engineering atTexas A&M University and Director of the Analog and Mixed-Signal Center. He was the Editor-in-Chief of the IEEE Trans-actions on Circuits and Systems – II for 1997-1999. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984). He is co-editor of the book Low-Voltage/Low-Power Integrated Circuits (IEEE Press 1999). He received the1995 Guillemin-Cauer Award for his work on Cellular Networks.He was also the co-recipient of the 1997 Darlington Award forhis work on high-frequency filters. His present interests are inthe area of active filter design, RF-Communication circuits andanalog and mixed-mode circuit design. He is an IEEE FellowMember. E-mail: sanchez@ee.tamu.edu