opening base station architectures part 2

7/29/2019 Opening Base Station Architectures Part 2

1/6

Opening Base Station Architectures Part 2:

An Inside Look at CPRI

Christian Plante and Jason Wong, Altera Corp.

10/20/2004 5:00 AM EDT

In response to the Open Base Station Architecture Initiative (OBSAI) movement, which was

described inPart 1of this article, Ericsson AB, Huawei Technologies Co., NEC Corporation,

Nortel Networks SA and Siemens AG formed a similar initiative called Common Protocol Radio

Interface (CPRI).

The goal of CPRI is to allow base stations manufacturers and component vendors to share a

common protocol and more easily adapt platforms from one customer to the other. UnlikeOBSAI, CPRI does not specify mechanical or electrical interface requirements. The software

investment needed to design a CPRI-compliant module, however, can be re-used with other

customers despite the need for a new physical and electrical design.

In terms of scope, CPRI has a much narrower focus than OBSAI. As shown inPart 1, OBSAI

looks at the three major data links found in a BTS and calls them reference points (RP1, RP2,and RP3). Conversely, CPRI focuses solely on the link between the radio frequency (RF) and

channel cards found in the BTS.

In the CPRI nomenclature, those two cards are known as the radio equipment (RE) and radio

equipment control (REC) cards, respectively. In other words, CPRI is specifying the sameinterface as the OBSAI RP3 specification. CPRI mainly covers the physical and data link layerof the interface. It also specifies how to transfer the user plane data, control and management

(C&M) plane data and the synchronization plane data over the interface. In the current release,

only 3GPP UTRA FDD, Release 5 is required to be supported.

Even though CPRI was started later than OBSAI, in 2003, the five partner companies managed

to draft a first specification in just four months. Today, CPRI version 1.2 is available fordownload. Let's take a look at the key elements of this spec.

Protocol Overview

Figure 1 provides a protocol overview of CPRI. Each individual block in the protocol overviewwill be described in Layer 1 (L1) and Layer 2 (2) specifications, below. in CPRI, all data, such as

control and management plane HDLC, L1 inband protocols, vendor-specific data, and user plane

(IQ data) data, is be time multiplexed together and transmitted or received by an electricalinterface or an optical interface.
http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.cpri.info/http://www.cpri.info/http://www.cpri.info/http://www.commsdesign.com/design_corner/showArticle?articleID=50500130http://www.commsdesign.com/design_corner/showArticle?articleID=50500130


2/6

Figure 1: Diagram showing the CPRI protocol.

CPRI allows three line bit rate options; it is mandatory for REC and RE to support at least one ofthe line bit rates while maintaining no mandatory physical layer mode. The three line rates are

614.4, 1228.8, and 2457.6 Mbit/s. The higher line rate is always compared to the one that is

immediately lower.

CPRI does not have a mandatory physical-layer protocol. As long as the protocol used by a

designer meets the bit-error-rate (BER) specification, as well as the clock stability and noiserequirement, it can be used. For an optical transceiver, Gigabit Ethernet, 10 Gigabit Ethernet,

fibre channel, and InfiniBand are recommended.

CPRI also recommends two electrical variants: high voltage (HV) and low voltage (LV). HV is

guided by 1000Base-CX specification in IEEE 802.3-2002[1], clause 39 with 100-ohm

impedance. LV is guided by XAUI in IEEE 802.3ae-2002[2], clause 47. LV is recommended forall the data rates while HV is recommended for 614.4 Mbit/s and 1228.8 Mbit/s. CPRI also

mandates 8B/10B encoding for serial transmission over the interface.

Based on the frequency accuracy requirement of +/- 0.05 ppm by 3GPP TS 25.104[8] section

6.3, CPRI has tight jitter and phase noise requirements based on a stable clock signal. These

requirements ensure that overall base station frequency accuracy is met.

Besides frequency accuracy, 3GPP TS 25.104[8] section 6.8.4 requires the time alignment error

in transmit diversity shall not exceed Tc/4. In order to meet the timing accuracy requirement,CPRI requires the absolute delay accuracy excluding the cable length to be +/- Tc/32 or roughly

16 ns.

Other requirements include delay calibration to measure delay due to the transmission medium

and a maximum round-trip delay requirement to ensure the quality of service (QOS). Delay

calibration is a requirement for CPRI since both RE and REC needs to determine the frametiming information of the signals. CPRI defines various reference points in RE and REC for the


3/6

delay to be measured and calibrated. It also provides an example on the delay calibration

procedure in the specification but no specific method is required as long as the delay can bemeasured and calibrated.

The BER requirement for the dataplane is set at 10-12

. This is less stringent than the OBSAI

requirement of 10

-15

.

CPRI Frame StructureThe length of a basic CPRI frame, index X, is 1 Tc or 260.4 ns. Each basic frame is made up of

16 words with index W ranging from 0 to 15.

The first word in each basic frame is used as the control word. The length of the word with index

B varies based on the CPRI line bit rate. For example, B equals 8-bit for 614.4 Mbit/s, 16-bit for

1228.8 Mbit/s, and 32-bit for 2457.6 Mbit/s.

Each byte within a word is addressed with index Y ranging 0 to 3, depending on the line bit rate.

So, 256 basic frames form a hyperframe with index Z and 150 hyperframes form a UMTS radioframe. CPRI denotes the hyperframe number as HFN and UMTS radio frame number as node B

frame number (BFN). In the CPRI specification, each byte is denoted as #Z.X.Y. Figure 2 shows

the CPRI frame hierarchy.

Figure 2 : Diagram showing rhe basic CPRI frame hierarchy.

Data Mapping to the CPRI FrameUser plane data that contains mostly voice-data is made up of the in-phase/quadrature (I/Q)

modulation data. CPRI supports different I/Q sample widths for the uplink and downlink

direction. Depending on the application-layer implementation, sample width (M) ranges from 8to 20 for the downlink and 4 to 10 for the uplink.

There is also a different oversampling ratio (n) specified for the uplink and downlink directions.

The oversampling ratio is always 1 for downlink traffic and 2 to 4 for uplink traffic. I/Q samplesof width M form an antenna carrier (AxC) container that make up one basic CPRI frame.


4/6

As discussed above, in CPRI, there is one control word every basic frame. In other words, there

are 256 control words for every hyperframe. The 256 control words are divided into 64subchannels with four control words for every subchannel. CPRI assigns these specific

subchannels in the hyperframe for various purposes. Besides synchronization and timing

information, C&M data, vendor specific information and L1 inband protocol are being

multiplexed into the subchannels.

Control and Management DataThere are two types of C&M channelsfast and slowthat are supported by CPRI. The fast

C&M channel is based on Ethernet and the slow one is based on HDLC. It is a requirement to

use at least one of the fast or slow channels on a CPRI link. For a passive link considered as alink expansion of an existing link, a C&M channel is not needed.

The slow (HDLC) C&M channel supports a number of different data rates. The 614.4-Mbit/s

line-rate option supports 240- to 480-kbit/s HDLC data. The 1228.8-Mbit/s line-rate optionsupports 960-kbit/s HDLC data on top of the rates supported at 614.4 Mbit/s. A 2457.6-Mbit/s

line rate supports 1920-kbit/s HDLC rate, plus all the HDLC data rates mentioned. As discussedabove, the HDLC frames are mapped to dedicated control word subchannels in a hyperframe.

The fast (Ethernet) C&M channel supports various data rates depending on the line bit rate. For

614.4 Mbit/s, the data rate ranges from 0.48 to 21.12 Mbit/s. For 1228.8 Mbit/s, it ranges from0.96 to 42.24 Mbit/s. The 2457.6-Mbit/s line bit rate supports 1.92 to 84.48 Mbit/s of Ethernet

data.

There are 16 control words reserved for vendor specific information in the slow C&M link. In a

fast C&M link, CPRI supports up to 192 control words for vendor specific information.

In addition to the two C&M channels, CPRI has four layer 1 alarms and each alarm has adedicated bit in the CPRI hyperframe that remotely informs the other side of the connection of

the alarm. The alarms include loss of signal (LOS), loss of frame (LOF), remote alarm indication(RAI), service access point (SAP), and service defect indication (SDI). The actions on both sides

of the connection when the alarm occurs are defined clearly in the CPRI specification.

Layer 2 SpecThe Layer 2 specification for the fast and slow C&M are divided into four sections: Lyer 2

framing, media access control(MAC) mapping, flow control, and control dataprotection/retransmission mechanism.

For the HDLC standard, CPRI basically follows ISO/IEC 13239:2002 (E) [10] with a fewadditions of specifics to CPRI application. For the Ethernet standard, it generally follows IEEE

802.3-2002 [1].

In the physical coding sublayer (PCS) of the CPRI standard, only the encoding/decoding feature

is fully supported. The other main features in the PCS are irrelevant for CPRI purposes. The

Ethernet MAC frame shall be encoded using the 4B/5B code of 100BASE-X PCS as in IEEE802.3-2002 [1].


5/6

Besides C&M data, CPRI specifies the required start-up sequence to bring up a CPRI link. The

start-up sequence is designed to first synchronize Layer 1 byte and hyperframe alignment, andsecond to align capabilities of RE and REC: line rate, C&M link speed, protocol and vendor-

specific signalling. The start-up sequence must find a common match from respective RE and

REC to establish a CPRI link. Some of the transitions in the start-up sequence state machine are

not defined because it is out of the scope of CPRI and is pending individual vendorimplementation.

CPRI ImplementationThe concept of CPRI is similar to OBSAI in using commercially available devices to drive down

the cost of a base station. The delay accuracy requirement of CPRI, however, introducesproblems for many of the existing serializer/deserializer (serdes) deices.

Most serdes have a certain level of uncertainty that is introduced in the serializing and de-

serializing process. The delay uncertainty is usually specified in the number of bits per word.Thus, a serdes with 16-bit bus architecture may have twice the delay uncertainty as a serdes with

8-bit bus architecture because the number of bits per word is doubled. In general, it ischallenging for any serdes to meet the delay accuracy requirement at 614.4 Mbit/s. Meeting thedelay accuracy requirement at 1228.8 Mbit/s will be challenging for serdes with a 16-bit bus

width.

As far as the data-link layer implementation, FPGAs provide the easiest and most flexible

solution. While there are multiple low-cost FPGA solutions on the market that would fit the bill,

should a one-chip solution be desired, only an FPGA with built in SERDES delivers thiscapability.

Figure 3 offers an example of how the CPRI framer can be implemented with the rest of the

system. It is possible to implement all the blocks in the diagram in a single FPGA. In this case, asoft-core embedded processor can be used. Easy bus connection across different blocks can be

made with a bus switch fabric provided by an embedded soft-core processor. By running certain

instructions in hardware custom instructions supported by the soft-core processor candramatically increase system performance on the critical path.


6/6

Figure 3: Example CPRI framer implementation.

For an FPGA solution with architecture similar to Figure 3, the serdes can be internal or external.

An internal serdes removes the requirement to route multiple parallel buses across the serdes and

the FPGA, and simplifies the board design. The functional blocks can be implemented either inhardware or software, depending on the system performance requirement. An embedded soft-

core processor may be used to act as an application layer to handle the control and managementfunctions, as well as any vendor-specific processing. The one-chip FPGA solution provides the

best blend of cost, performance, flexibility, and ease of design for a CPRI solution.

opening base station architectures part 2

Documents