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Status of the OPERA DAQ Status of the OPERA DAQ

D.Autiero, J.Marteau

T.Descombes informatics

S.Gardien, C.Girerd, C.Guérin electronics

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Ethernet mezzanine:

•Common part to all sub-detectors (TT, RPC, PT): the mezzanine is simply plugged on the digital boards (regardless of the standard used: VME for RPC & PT, dedicated board for the TT).

•Implementation: FPGA (readout sequencer), FIFO (temporary storage), -processor (with Ethernet transceiver): MCM ETRAX from AXIS with imbedded LINUX.

•Dimensions: 60mm60mm, 120 pins for external connections.

•Design completed 1st version for mid-April.

•A dedicated test card is being produced in Lyon (electrical tests, tests of communication protocols).

•The up-to-date design has been circulated to the Naples group (RPC).

Ethernet mezzanineEthernet mezzanine

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6 cm6

cm

120 pins ( 4 x 30 )1.27 pitch

EPC2

IDT

72V

3911

0L10

…………………….…………………….…………………….…………………….…. ….…. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …. …………………….…………………….…………………….…………………….

………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………

MCM

FPGA EP20KEFC324

1 2

59 60 61 62

119 120

Ethernet mezzanineEthernet mezzanine

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TT digital board:

•This board is directly plugged at the output of the analog board (2 flat cables on connectors J7 & J8)

•Its main components are: •1 ADC (12 bits), •1 Ethernet mezzanine (FPGA, FIFO, -processor),•1 clock receiver unit (EPLD), •1 high voltage module (ISEG)•1 LED pulser (from BERN)

•Dimensions: 282mm 90mm

•Connectors: 4 Ethernet RJ45 (2 for the clock, 2 for the signal), 1 ( 7V), 1 RS232 (for debug purposes)

•Design under completion: 1st prototype for May.

TT digital boardTT digital board

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HV module LED pulser Ethernet mezzanine

Analog board

Clock EPLD RJ45 conn.

We did not implement the Ethernet repeater in this 1st prototype (cost, # I/O) !!! we have 3 cables / digital board (clk, data, power supply)

TT digital boardTT digital board

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TT digital boardTT digital board

Meeting @ CERN between Lyon & Bern :

•Review of all the parts of the digital board : LAL chips signals, ethernet mezzanine,LED pulser, HV module, clk receiver (fine tuning before freezing the board layout)

•Choice of all the components: ADC’s for charge R/O & for HV R/O, MUX, DAC’s, holddelay components

•Definition of the register R/O convention

•Review of all the signals & connectors from analog digital board

•Discussion about the power supply : fuses ? monitoring ? cooling of the boards (temperature measurement with the 2nd ADC) ?

•Milestones: test with analog board end of june (Bern also developping charge injector)

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Backup DAQ system for : TT modules tests at IReS & prototype tests : •Upgrade of a DAQ board designed for R&D purposes •Uses an Ethernet transceiver from Agilent (BFOOT) •1st prototype successfully tested (hardware & software based on Labview)• 5 boards ordered (TT modules tests + tests in Gran Sasso) should be received end of April

FPGA

ADC

Ethernet transceiver(BFOOT)

RJ45Conn.

NIM outputs

TT digital boardTT digital board

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Power supply distribution for TT (1st proposal) : •2 solutions proposed by ALIMTRONIC based on Wiener products (PL500 modules used in D0 & Minos).•Requirements: 7Vguaranteed for the last connected point, estimated power 10W / node 1.5A / node•Most economical solution:

•1 output for 2 walls (1 sense point between the 2 walls) •32 x 1.5 = 48A / output •PL500 F8 / 48A : 6U power supply unit with 8 outputs 7.6 keuros / module•1 7U crate 1.4 keuros •Pro : cost. Contra : important voltage fall along the line

•Other scheme : •1 output for 8 nodes (1/2 plane)•8 x 1.5 = 12A / output•PL500 F8 / 12A : 3U power supply unit with 8 outputs 4.6 keuros / module•1 4U crate 0.9 keuros•Pros & contra are inverted

PL500: 48A

To 2nd wall

U2

U1

Umin=7V

Sense point: Umax=Umin+ U1+ U2

Power supply distributionPower supply distribution

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General features :

•A common clock is distributed from the GPS master cards in the cavern to each node of OPERA

•The signal distribution is provided through M-LVDS bus (from the O/E converter to the master cards & from the master card to the node cards)

•The system is bi-directional (acknowledge signals + propagation time measurements to adjust delays)

•Commands are encoded in the clock (RESET, REBOOT, CYCLE INCREMENT)

Clock distribution systemClock distribution system

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« Slave » clockin Hall C (receives theGPS signal from the Outside antenna though a 8km optical fiber)

O/E converter card

Master card 0

Node card i

SM2SM1

PCI card

Optical fiber

MLVDSMLVDS

Clock distribution system for TT (62 master cards, 992 nodes)

31 Master cards + 1 O/E converter cardcollected in 1 crate on the top of the detector (+3 additional master cards for the spectrometer)1 optical fiber from the « slave » card / SM

Clock distribution systemClock distribution system

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Master & node cards : •Prototypes have been developped and successfully tested :

• Communication protocols (tested with more than 20 meters cables between master & node)• Choice of serializer/deserializer components (Hotlink) • VHDL code (for the ALTERA EPLD)

•The architecture of the node part has been frozen & implemented in the 1st version of the TT boards•Next step: production of 8 independant node cards (1/2 TT plane) to repeat tests with increasing load

Prototype of master card Prototype of node card

Clock distribution systemClock distribution system

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Cabling & co:

•The 1st prototypes of TT board will not include local Ethernet repeaters.

•We foresee 2 repeaters / plane (1 left + 1 right) with 8 inputs & 1 output.

•We propose to collect the 62 outputs on 2 switches (with Gigabit output) on the top of the experiment to reduce the number of horizontal cables in the cable tray (only 2 Ethernet connections to the electronic room).

•In the 1st scheme, the power supply modules will be located in 8 crates on one side of the experiment (the “most accessible” side) which will facilitate the cabling of the planes.

•The clock master cards + O/E converter will be hosted in 1 crate (standard to be defined) on one side of the experiment if this is compatible with the cable length (to be tested).

Cabling & co. Cabling & co.

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12 boards

RPC controller crate

PT controller crate

11 boards

11 boards

#0 #3016 nodes Optical fiber from slave card

O/E converter

Master cards

Power supply crates

#0 #15

S.M. top view

Ethernet switch

Cabling & co. Cabling & co.

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GPS PCI card architecture (« slave » card in Hall C):

•Receives the GPS clock (we use a standard DATUM 637PCI antenna for tests).

•Distributes the clock through optical fibres & receives signals from the different nodes (2 lines / SM, no optical splitter).

•The idea is to design a new slave card using PCI standard with a “collaboration” from the ESAT company who designs the LNGS GPS system.

•A visit to the ESAT company took place on March, 27th in Torino. We got many informations on software & hardware aspects:

•Date pattern decoding•Readout ‘triggering’•Oscillator choice•Sinus square signals conversion•VHDL code for signal reception

•The 1st prototype of PCI board + O/E converter board is under completion.

GPS distribution systemGPS distribution system

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Optical fiberfrom the master

clock

PLX9080

APEX20KE

EEPROM

HotLink923

HotLink933

TX1HFBR1116T

RX1HFBR2116T

EPC2

PECLLocalbus

To the station

RX2HFBR2116T

10Mhz5.10E-11OC-050

Vectron Int.

Master clock date

Optical fiberto the O/E

converter of SM1 & SM2Data+clock

mixed

Optical fiberFrom the SM1

Optical fiberFrom the SM2

Inputs from GPS receiver(pps, 10Mhz, analog Irig B, digital Irig B)

O/EConverter

Optional for Lab tests

TX2HFBR1116T

Propagation timemeasurement (optional)

GPS distribution systemGPS distribution system