operating system organization

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Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 3

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3Operating SystemOrganization

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Purpose of an OS

The Abstractions

Create the Abstractions

Coordinate Useof the AbstractionsProcesses

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OS Requirements• Provide resource abstractions

– Process abstraction of CPU/memory use• Address space• Thread abstraction of CPU within address space

– Resource abstraction• “Anything a process can request that can block the

process if it is unavailable”• NT uses “object abstraction” to reference resources

– File abstraction of secondary storage use

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DOS -- Resource Abstraction Only

Processor(s) Main Memory Devices

Program

Program

Program

OS Services

Libraries

ROM Routines

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OS Requirements (cont)

• Provide resource abstractions• Manage resource sharing

– Time/space-multiplexing– Exclusive use of a resource– Isolation– Managed sharing

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Abstraction & Sharing


Libraries

ROM Routines

ProgramState

Process

ProgramState

Process

ProgramState

Process

OS Services • Abstraction• Manage sharing

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OS Design Constraints

• Performance• Protection and security• Correctness• Maintainability• Commercial factors• Standards and open systems

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Performance

• The OS is an overhead function should not use too much of machine’s resources

• Minimum functionality is to implement abstractions

• Additional function must be traded off against performance– DOS: one process– UNIX: low level file system

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Protection & Security

• Multiprogramming resource sharing• Therefore, need software-controlled

resource isolation• Security policy: Sharing strategy chosen by

computer’s owner• Protection mechanism: Tool to implement a

family of security policies

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Correctness & Maintainability

• Security depends on correct operation of software trusted vs untrusted software

• Maintainability relates to ability of software to be changed

• If either is sufficiently important, can limit the function of the OS– Guiding a manned spaceship– Managing a nuclear reactor

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Device Management

Device-IndependentPart

Device-DependentPart

Device …Device Device



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Process, Thread, and Resource Management

…Processor

PrimaryMemory

AbstractResources

Multiprogramming

ThreadAbstraction

ProcessAbstraction Generic

ResourceManager

Other

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Memory Management

PrimaryMemory

ProcessManager

BlockAllocation

VirtualMemory

Isolation &Sharing

StorageDevices

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Exclusive Access to a Resource

Process A

SupervisorProgram

A’s ProtectedObject

Processor

Process B

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Processor Modes

• Mode bit: Supervisor or User mode• Supervisor mode

– Can execute all machine instructions– Can reference all memory locations

• User mode– Can only execute a subset of instructions– Can only reference a subset of memory

locations

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Kernels

• The part of the OS critical to correct operation (trusted software)

• Executes in supervisor mode• The trap instruction is used to switch

from user to supervisor mode, entering the OS

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Supervisor and User Memory

UserSpace

SupervisorSpace

UserProcess

SupervisorProcess

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Procedure Call and Message Passing Operating Systems

call(…);

trap

return;

send(…, A, …);receive(…, B, …);

receive(…A, …); …send(…, B, …);

send/receive

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System Call Using the trap Instruction

…fork();…

fork() {…trap N_SYS_FORK()…}

sys_fork()

sys_fork() {/* system function */ … return;}

KernelTrap Table

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A Thread Performing a System Call

User Space Kernel Space

fork();

sys_fork() {

}

Thread

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Basic Operating System Organization


Process, Thread &Resource Manager

MemoryManager

DeviceManager

FileManager

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Libraries Commands

Device Driver

The UNIX ArchitectureInteractive User

ApplicationPrograms

OS System Call Interface

Device Driver

Device Driver

Driv

er In

terf

ace

…Monolithic Kernel Module• Process Management• Memory Management• File Management• Device Mgmt Infrastructure

Trap Table

…

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Microkernel Organization

Device DriversMicrokernel


Libraries

Process

Process

Process

Server Server Server

User

Supervisor

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Windows NT Organization


Libraries

ProcessProcess

Process

SubsystemUser

Supervisor

Subsystem Subsystem

Hardware Abstraction LayerNT Kernel

NT ExecutiveI/O Subsystem

TT

TT

TT T T

T

Process ManagementMemory ManagementFile ManagementDevice Mgmt Infrastructure

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Monitoring the Kernel


Libraries

ProcessProcess

Process

Subsystem Subsystem Subsystem

Hardware Abstraction LayerNT Kernel

NT ExecutiveI/O Subsystem

TT

TT

TT T T

TTaskManager

pview

pstat

Supervisor

User

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4ComputerOrganization

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Stored Program Computers and Electronic Devices

Pattern

Fixed Electronic Device

Variable Program

Stored Program Device

Jacquard Loom

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Program Specification

int a, b, c, d;. . .a = b + c;d = a - 100;

Source

; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a

; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d

Assembly Language

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Machine Language

; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a

; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d

Assembly Language

10111001001100…110111001010000…010100111001100…010111010001100…110111001010000…010100110001100…010111001101100…1

Machine Language

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The von Neumann Architecture

Control Unit(CU)

Central Processing Unit (CPU)

Device

Address BusData Bus

Arithmetical Logical Unit(ALU)

Primary Memory Unit(Executable

Memory)

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The ALU

R1R2

Rn

. . .

Status RegistersFunctional Unit

Left Operand

Right Operand

Result

To/from Primary Memory

load R3,bload R4,cadd R3,R4store R3,a

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Control Unit

3046305030543058

Primary Memory

Fetch Unit

Decode Unit

Execute Unit

PC

IR

Control Unit

load R3,bload R4,cadd R3,R4store R3,a

10111001001100…110111001010000…010100111001100…010111010001100…1load R4, c

3050

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Control Unit Operation

PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase};

• Fetch phase: Instruction retrieved from memory

• Execute phase: ALU op, memory data reference, I/O, etc.

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Primary Memory Unit

MAR

MDR

Command

012

n-1

1234 98765Read Op:

1234

1. Load MAR with address

read

2. Load Command with “read”

98765

3. Data will then appear in the MDR

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The Device-Controller-Software Relationship

Application Program

Device Controller

Device

Softw

are

in th

e C

PU

Abstract I/O Machine

• Device manager• Program to manage device controller• Supervisor mode software

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Device Controller Interface

Command Status Data 0

Data 1

Data n-1Logic

busy done Error code . . .. . .busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)

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Performing a Write Operation

while(deviceNo.busy || deviceNo.done) <waiting>;deviceNo.data[0] = <value to write>deviceNo.command = WRITE;while(deviceNo.busy) <waiting>;deviceNo.done = TRUE;

• Devices much slower than CPU• CPU waits while device operates• Would like to multiplex CPU to a different

process while I/O is in process

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CPU-I/O Overlap

CPU

Device

…

Rea

dy P

roce

sses

CPU

Device

…

Rea

dy P

roce

sses

I/O Operation

CPU

Device

…

Rea

dy P

roce

sses

Uses CPU

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Determining When I/O is Complete

CPU

Device Device Device

Interrupt Pending

• CPU incorporates an “interrupt pending” flag• When device.busy FALSE, interrupt pending flag is set• Hardware “tells” OS that the interrupt occurred• Interrupt handler part of the OS makes process ready to run

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Control Unit with Interrupt (Hardware)

PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest) { memory[0] = PC; PC = memory[1]};

memory[1] contains the address of the interrupt handler

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Interrupt Handler (Software)

interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */

deviceHandler(int i) { finishOperation(); returnToScheduler();}

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A Race Condition

saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+NumberOfRegisters+i] = StatusRegister[i];}

PC = <machine start address>;IR = memory[PC];haltFlag = CLEAR;while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; if(InterruptRequest && InterruptEnabled) { disableInterupts(); memory[0] = PC; PC = memory[1]};

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Revisiting the trap Instruction (Hardware)

executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2 . . . case n: PC = memory[1000+n];// Trap handler n};

• The trap instruction dispatches a trap handler routine atomically

• Trap handler performs desired processing• “A trap is a software interrupt”

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Direct Memory Access

PrimaryMemory

CPU

Controller

Device

PrimaryMemory

CPU

Controller

Device

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Addressing Devices

PrimaryMemory

Device 0

Device 1

Device n-1

PrimaryMemory

Device 0

Device 1

Device n-1

Dev

ice A

ddre

sses

Mem

ory

Add

ress

es

Mem

ory

Add

ress

es

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Polling I/O…// Start the device…While((busy == 1) || (done == 1)) wait();// Device I/O complete…done = 0;

…while((busy == 0) && (done == 1)) wait();// Do the I/O operationbusy = 1;…

busy done

Soft

war

eH

ardw

are

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Fetch-Execute Cycle with an Interrupt

while (haltFlag not set during execution) { IR = memory[PC]; PC = PC + 1; execute(IR); if (InterruptRequest) { /* Interrupt the current process */ /* Save the current PC in address 0 */ memory[0] = PC; /* Branch indirect through address 1 */ PC = memory[1]; }}

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Detecting an Interrupt

CPU

Device Device Device

InterruptRequest flag

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The Interrupt Handler

Interrupt_Handler{ saveProcessorState(); for (i=0; i<Number_of_devices; i++) if (device[i].done == 1) goto device_handler(i); /* Something wrong if we get here */}

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Disabling Interrupts

if(InterruptRequest && InterruptEnabled) {/* Interrupt current process */ disableInterrupts(); memory[0] = PC; PC = memory[1];}

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The Trap Instruction Operation

SMode

TrustedCode

trap

User Supervisor

Branch Table

2

3

1

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Intel System Initialization

ROM

CMOS

RAM

Boot DevicePOST

BIOS

Boot Prog

Loader

OS…Hardware Process

Data Flow

Power Up

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Bootstrapping

Bootstrap loader (“boot sector”)

Primary Memory

1

0x0001000

Fetch Unit

Decode Unit

Execute Unit

0000100

…

PC

IR

BIOS loader 0x0000100

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BootstrappingBootstrap loader (“boot sector”)

Primary Memory

Loader

1

2

Fetch Unit

Decode Unit

Execute Unit

0001000

…

PC

IR

BIOS loader 0x00001000x0001000

0x0008000

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BootstrappingBootstrap loader (“boot sector”)

Primary Memory

Loader

OS

12

3Fetch Unit

Decode Unit

Execute Unit

0008000

…

PC

IR


0x0008000

0x000A000

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Bootstrapping

Bootstrap loader (“boot sector”)

Primary Memory

Loader

OS

12

3

4. Initialize hardware5. Create user environment6. …

Fetch Unit

Decode Unit

Execute Unit

000A000

…

PC

IR


0x0008000

0x000A000

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A Bootstrap Loader Program

FIXED_LOC: // Bootstrap loader entry pointload R1, =0load R2, =LENGTH_OF_TARGET

// The next instruction is really more like // a procedure call than a machine instruction// It copies a block from FIXED_DISK_ADDRESS// to BUFFER_ADDRESS

read BOOT_DISK, BUFFER_ADDRESSloop: load R3, [BUFFER_ADDRESS, R1]

store R3, [FIXED_DEST, R1]incr R1bleq R1, R2, loopbr FIXED_DEST

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A Pipelined Function Unit

Function UnitOperand 1Operand 2

Result

Operand 1Operand 2

Result

(a) Monolithic Unit

(b) Pipelined Unit

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A SIMD MachineALU Control

Unit

ALU ControlUnit

ALU

ALU

ALU

…

(a) Conventional Architecture

(b) SIMD Architecture

operating system organization

Documents

operating systems

modern perspective

pearson education

object abstraction

performancethe os

ability of software

overhead function

osthe abstractionscreate