operating systems : memory managementchester/courses/15o_os/slides/4_mm.pdf · memory management...
TRANSCRIPT
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Initializing Memory andMemory Management in xv6
Chester Rebeiro
IIT Madras
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Outline
• Memory Management in x86– Segmentation
– Virtual Memory
• Initializing memory in xv6– Initializing Pages
– Initializing Segments
• Implementation of kalloc
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x86 address translation
CPU
Logical Address(segment
+offset) Segmentation
Unit
LinearAddress Paging
Unit
PhysicalMemory
PhysicalAddress
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x86 address translation
CPU
Logical Address(segment
+offset) Segmentation
Unit
LinearAddress Paging
Unit
PhysicalMemory
PhysicalAddress
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Segmentation Unit
• Virtual address space of process divided into separate logical segments
• Each segment associated with a segment selector and offset
Heap
StackData
Text
Address Map of Process
Text
Data
Stack
Heap
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Segmentation(logical to linear address)
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Example
Segment Base Limit
0 - -
1 1000 1000
2 4000 500
3 8000 1000
4 9000 1000
Address Map of Process0
Text1000
2000
Data 40004500
Stack8000
9000Heap
10000
1
segment register (eg %CS)
0x3000
pointer to descriptor table
0x3000
100
offset register (eg %eip)
+
3000
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Pointer to Descriptor Table
• Global Descriptor Table (GDT)
• Stored in memory
• Pointed to by GDTR (GDT Register)– lgdt (instruction used to load the GDT register)
• Similar table called LDT present in x86 (not used by xv6!)
047 16
sizebase
GDTR
Segment Descriptor
Segment Descriptor
Segment Descriptor
Segment Descriptor
Segment Descriptor
Segment Descriptor
GDTSize : size of GDTBase : pointer to GDT
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Segment Descriptor
• Base Address– 0 to 4GB
• Limit– 0 to 4GB
• Access Rights– Execute, Read, Write
– Privilege Level (0-3)
Access Limit
Base Address
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Segment Registers
• Holds 16 bit segment selectors– Points to offsets in GDT
• Segments associated with one of three types of storage– Code
• %CS register holds segment selector• %EIP register holds offset
– Data• %DS, %ES, %FS, %GS registers hold segment selector
– Stack• %SS register holds segment selector• %SP register holds stack pointer(Note: Only one code segment and stack segment can be accessible
at a time. But 4 data segments can be accessed simultaneously)
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x86 address translation
CPU
Logical Address(segment
+offset) Segmentation
Unit
LinearAddress Paging
Unit
PhysicalMemory
PhysicalAddress
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Linear to Physical Address
• 2 level page translation • How many page tables are present?
• What is the maximum size of the process’ address space?– 4G
ref : mmu.h (PGADDR, NPDENTRIES, NPTENTRIES, PGSIZE)
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The full Picture
Initialized oncecommon for allprocesses
Each proceshas one
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Virtual Address Advantages(Isolation between Processes)
Text(instructions)
Data
Heap
Stack
Text(instructions)
Data
Heap
Stack
Process AProcess A Process BProcess B
Virtual Memory Physical Memory Virtual Memory
Process APageTable
Process BPageTable
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Virtual Addressing Advantages Paging on Demand
• RAM only loads pages into memory whenever needed
• When new program is executed page table is empty
Page tablefor process
(is stored in RAM)
0
1
2
3
0
0
0
0
0
0
1
2
3
4
5
6
4
5
6
0
0
Present/absent
Present/Absent bit : 1 if entry in page table is valid, 0 if invalidIn x86 : PTE_P
0
0
0
0
0
0
0
0
1
2
3
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Paging on Demand (2)
• As data gets referenced, page table gets filled up.
• Page frame loaded from hard disk
Page tablefor process
(is stored in RAM)
0
1
2
3
0
0
3
0
0
0
1
2
3
4
5
6
4
5
6
0
0
Present/absent
0
0
1
0
0
0
0
0
1
2
3
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Paging on Demand(3)
• As execution progresses, more entries in page table get filled.
• Similarly, more frames in RAM get used
• Eventually, entire RAM is filled
Page tablefor process
(is stored in RAM)
0
1
2
3
1
0
3
2
0
0
1
2
3
4
5
6
4
5
6
0
0
Present/absent
1
0
1
1
1
0
0
0
1
2
3
What next?
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Paging on Demand (4)
• A particular frame is selected and swapped out into disk
• A new page swapped in
• Page table is updated
Page tablefor process
(is stored in RAM)
0
1
2
3
1
0
3
2
0
0
1
2
3
4
5
6
4
5
6
0
1
Present/absent
0
0
1
1
1
0
1
0
1
2
3
Disk(swap space)
Swap out
Swap in
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Virtual Memory achieves SecuritySecurity
• Security– Page tables augmented by protection bits
Page tablefor process
protection bits
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Protection Bits in x86
• PTE_W : controls if instructions are allowed to write to the page
• PTE_U : controls if user process can use the page. If not only kernel can use the page
These are checked by the MMU for each memory access!
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• Making a copy of a process is called forking.– Parent (is the original)
– child (is the new process)
• When fork is invoked,– child is an exact copy of
parent• When fork is called all pages
are shared between parent and child
• Easily done by copying the parent’s page tables
Physical Memory
ParentPageTable
ChildPageTable
Virtual Addressing Advantages (easy to make copies of a process)
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Virtual Addressing Advantages (Shared libraries)
• Many common functions such as printf implemented in shared libraries
• Pages from shared libraries, shared between processes
Process AProcess A Process BProcess B
Virtual Memory Physical Memory Virtual Memory
Process APageTable
Process BPageTable
printf(){ …} printf(){ …}
printf(){ …}
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Virtual Addressing Advantages (Shared Memory)
• Shared memory between processes easily implemented using virtual memories
– Shared memory mapped to the same page
– Writes from one process visible to another process
Process 1
Process 2
Shared memory
kernel
userspace
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back to booting…
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so far…
BIOS
bootloader
• executes on reset. • does POST, initializes devices• loads boot loader to 0x07c00 and jump to it(all in real mode)
Power on Reset
• disable interrupts• Setup GDT (8941)• switch real mode to protected mode• setup an initial stack (8967)• load kernel from second sector of disk to 0x100000• executes kernel (_start)
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Memory when kernel is invoked(just after the bootloader)
• Segmentation enabled but no paging
• Memory map
CPU SegmentationUnit
physicalmemorylogical
addressphysicaladdress
codedata
bootloader
stack
logicalmemory
physical memory
kernel
0x1
0000
0
Slide taken from Anton Burtsev, Univ. of Utah
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Memory Management Analysis
• Advantages– Got the kernel into protected mode (32 bit code) with minimum
trouble
• Disadvantages– Protection of kernel memory from user writes
– Protection between user processes
– User space restricted by physical memory
• The plan ahead– Need to get paging up and running
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CPU SegmentationUnit
physicalmemorylogical
addressphysicaladdress
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OS code are not Relocatable
• kernel.asm (xv6)
• The linker sets the executable so that the kernel starts from 0x80100000
• 0x80100000 is a virtual address and not a physical address
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Virtual Address Space
0
0xffffffff
KERNBASE0x80000000
Virtual
Physical
Device memory
+0x100000
0
0x100000
PHYSTOP
• Kernel memory mapped into every process - easy to switch between kernel and user modes• VA(KERNBASE:+PHYSTOP) PA(0:PHYSTOP) - convert from VA to PA just by +/- KERNBASE - easily write to physical page - limits size of physical memory to 2GB
Kernel Memory
ref : memlayout.h (0200)
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Converting virtual to physicalin kernel space
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What would be the address generated before and immediately after paging isenabled?
before : 0x001000xxImmediately after : 0x8001000xx
So the OS needs to be present at two memory ranges
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Early Kernel Paging Initialization
• Kernel entry point : _start (1036)
Turn on Page sizeextension
Set Page DirectoryWhy 4MB pages? Simplicity(We just want 2 pages)
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4MB Pages
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Kernel memory setup
• First setup two 4MB pages– Entry 0:
Virtual addresses 0 to 0x04000000 Physical addresses 0 to 4MB
– Entry 512: Virtual addresses 0x80000000 to 0x84000000
Physical addresses 0 to 4MB
Why do we need to map this twice?
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First Page Table
courtesy Anton Burtsev, Univ. of Utah
logicalmemory
physical memory
virtual memory
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Enable Paging
• Entry point : _start (1036)
Turn on Page sizeextension
Set Page Directory
Enable Paging
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Stack setup
• Entry point : _start (1036)
Turn on Page sizeextension
Set Page Directory
Enable Paging
Stack setup
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Stack
courtesy Anton Burtsev, Univ. of Utah
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Execute main
• entry point : _start (1036)
Turn on Page sizeextension
Set Page Directory
Enable Paging
Stack setup
Jump to main
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New Address Scheme Analysis
Scheme : enable paging with 2 pages of 4MB each
• Advantages,– Useful for initializing the rest of memory
• (issues with kmalloc …. later!!!)
• Disadvantages– Kernel mapped twice, reducing user space area
– Only 4MB of physical memory is mapped. Remaining is unutilized
xv6 next goes into the final addressing scheme
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(Re)Initializing Paging
• Configure another page table– Map kernel only once making space for other
user level processes
– Map more physical memory, not just the first 4MB
– Use 4KB pages instead of 4MB pages• 4MB pages very wasteful if processes are small
• Xv6 programs are a few dozen kilobytes
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Virtual Address Space
1823
KERNBASE = 0x80000000KERNLINK = KERNBASE + 0x100000PHYSTOP = 0xE000000EXTMEM = 0x100000
Setting Up kernel pages (vm.c)1. stuct kmap
data obtained from linker script, which determines size of code+readonly data
2. Kernel page tables set up in kvmalloc() (1857)
(invoked from main)
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mappages (1779)
• Fill page table entries mapping virtual addresses to physical addresses
• Which page table entry?– obtained from walkpgdir
• What are the contents?– Physical address
– Permissions
– present
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walkpgdir (1754)
• Create a page table entry corresponding to a virtual address.
• If page table is not present, then allocate it.
• PDX(va) : page directory index
• PTE_ADDR(*pde) : page directory entry
• PTX(va) : page table entry
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Using Page Tables (in OS)
• Functions available– mappages (1779) : create page table entries mapping
virtual addresses to physical addresses
– copyuvm (2053): copy a process’s page table into another
– walkpgdir (1754) : return page table entry corresponding to a virtual address
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User Pages mapped twice
0
0xffffffff
KERNBASE
Virtual
Physical
Device memory
+0x10000
Device memory
0
0x10000
PHYSTOP
Kernel Memory
• Kernel has easy access to user pages (useful for system calls)
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(Re)Initializing Segmentation
• Segments– Kernel code
– Kernel data
– User code
– User data
– Per CPU data
ref : seginit (1716)
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Segment Descriptor in xv6
ref : mmu.h ([7], 0752, 0769)
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Loading the GDTR
• Instruction LGDT • Each CPU has its own GDTR
ref : x86.h
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Per CPU Data
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Recall Memory is Symmetric Across Processors
Processor1
Processor2
Processor3
Processor4
front side bus
North BridgeDRAMMemory bus
• Memory Symmetry• All processors in the system share the same memory space• Advantage : Common operating system code
• However there are certain data which have to be unique to each processor• This is the per-cpu data• example, cpu id, scheduler context, taskstate, gdt, etc.
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Naïve implementation of per-cpu data
• An array of structures, each element in array corresponding to a processor
• Access to a per-cpu data, example : cpu[cpunum()].ncli
• This requires locking every time the cpu structure is accessed– eg. Consider process migrating from one processor to another while updating a per-cpu
data– slow (because locking can be tedious)!!!
51ref : proc.h [23]
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Alternate Solution(using CPU registers)
• CPU has several general purpose registers– The registers are unique to each processor (not shared)
• Use CPU registers to store per-cpu data– Must ensure the gcc does not use these registers for other
purposes
• Fastest solution to our problem, but we do not have so many registers
52Content borrowed from Carmi Merimovich (http://www2.mta.ac.il/~carmi/)
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Next best solution(xv6 implementation)
• In seginit(), which is run on each CPU initialization, the following is done.
– GDTR will point upon cpu initialization to cpus[cpunum()].gdt.
– (Thus, each processor will have its own private GDT in struct cpu).
• Have an entry which is unique for each processor
– The base address field of SEG_KCPU entry in GDT is &cpus[cpunum()].cpu (1731)
– %gs register loaded with SEG KCPU << 3.
• Lock free access to per-cpu data– %gs indexes into the SEG_KCPU offset in GDT
– This is unique for each processor
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CPU0 CPU1
GDTFor CPU0
GDTFor CPU1
per-cpufor CPU0
per-cpufor CPU1
%gs %gs
Content borrowed from Carmi Merimovich (http://www2.mta.ac.il/~carmi/)
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Using %gs
• Without locking or cpunum() overhead we have:– %gs:0 is cpus[cpunum()].cpu.
– %gs:4 is cpus[cpunum()].proc.
• If we are interrupting user mode code then %gs might contain irrelevant value. Hence– In alltraps %gs is loaded with SEG_KCPU << 3.– (The interrupted code %gs is already on the trapframe.)
• gcc not aware of the existence of %gs, so it will no generate code messing up gs.
54Content borrowed from Carmi Merimovich (http://www2.mta.ac.il/~carmi/)
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Allocating Memory
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Allocating Pages (kalloc)PhysicalMemory
0
end of kernel
PHYSTOP
used for allocation
Used pageFree page
freelist
• Physical memory allocation done in page granularity (i.e. 4KB)• Free physical pages in a list• Page Allocation removes from list head (see function kalloc)• Page free adds to list head (see kfree)
ref : kalloc.c [30]
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Freelist Implementation
• How is the freelist implemented?– No exclusive memory to store links (3014)
ptr to next free page
ptr to next free page
ptr to next free page
ptr to next free page
freelist
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Initializing the list(chicken & egg problem)
create free list marking all pages as free
at boot
access memory viaPage tables
this needs
Page tables arein memory and need to
be allocatedCreate a page table
this needs
ref : kalloc.c (kinit1 and kinit2)
Resolved by a separate page allocator during boot up, which allocates4MB memory just after the kernel’s data segment (see kinit1 and kinit2).
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For next class…
• revise / learn interrupt handling in x86 processors
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