operation a high performance, low noise, 128- channel readout integrated circuit for instrumentation...

Operation

A High Performance, Low Noise, 128-Channel Readout Integrated Circuit for

Instrumentation and X-Ray Applications

E.Beuville, M.Belding, A.Costello, R.Hansen, S.Petronio

INDIGO OPERATIONS

IEEE NSS N8-4– October 18, 2004

Indigo Systems Background(Merged with FLIR, January 2004)

Infra-Red Systems Manufacturer Imaging and Thermography Surveillance, Firefighting, Industrial, Military… • IR sensor fabrication facility (GaAs, InSb, Bolo) • Readout Integrated Circuit (ROIC) Core Capability

• Large 2D ROIC pixel arrays (1k x 1k at 15um pixel size)• Custom IC (mixed signal)

IR applications X-ray and mammography applications Implantable devices Space applications Instrumentation

INDIGO OPERATIONS


ISC9717 ROIC Description

Design 128 Channels, Low-Noise ROIC for Flat Panel Array and Instrumentation• 80um channel pitch• Low noise charge amplifier (programmable gain)• Low Pass Filter (programmable time constant)• Correlated Double Sampling (programmable gain)• On-Chip ADC (programmable 9 to 14 bits gray-code

output)

Charge Integrator Track-and-Hold 9-14 Bit ADCLow Pass Filter

LPF CDSADC

9 to 14bit

9 to 14bit

2 4 4

Integrator

Gain Time Constant Gain Resolution

T/HLPF CDSADC

9 to 14bit

Gain Time Constant Gain Resolution

T/H

C.D.S. Amplifier

INDIGO OPERATIONS


Applications and Detectors Compatibility

Wide Range of Applications Wide Range of Detectors

Digital X-ray Medical Imaging - Radiography - Fluoroscopy - Mammography - Angiography - Tomography

Flat Panel X-ray Sensors (TFT) - Cesium Iodide (CsI) or other scintillators - Selenium (Se) - Amorphous Silicon - Photodiode

Instrumentation - Airport screening - Non-Destructive Testing - CT scan, PET imaging - Astrophysics applications - Nuclear Science - Industrial Instrumentation

Solid-State Detectors - Silicon Detectors (Si) - Cadmium Zinc Telluride (CdZnTe) - Gallium Arsenide (GaAs) - Germanium (Ge) - Photodiode

INDIGO OPERATIONS


Application to X-ray Flat Panel

ISC9717 reading out TFT flat panel array• Wire bonded or Tape Automated Bonding (TAB)• Programmable readout direction

ISC9717ISC9717

ISC9717ISC9717

14 bits

14 bits14 bits

14 bits

TFT Array (split in 2)

Detector Bias

Column Select Line DATA Line

+

Sensor Pixel

Gate Driver Gate Driver

INDIGO OPERATIONS


ISC9717 Serial Command Register Gain Control (Integrator and CDS)

• Full dynamic range from 48fC (3x105 e-/hole) to 12pC (75x106 e-/hole) Integration While Read mode

• Higher readout rate Integration Then Read mode

• Lower noise Integration time control

• Integration time adjusted by controlling the clock (24us to few ms) Readout direction (left or right)

• Allows the readout IC to be connected on both sides of 2D sensors Averaging mode (two adjacent channels averaged)

• Improved signal-to-noise ratio• Higher readout rates

ADC resolution (9 to 14 bit)• Higher readout rate for lower ADC resolution• Current mode output (reduced clock feedthrough)

INDIGO OPERATIONS


Charge TransImpedance Amplifier (CTIA)

Folded cascode architecture• Differential amplifier large PSRR• P channel input transistors low 1/f noise• Folded cascode high gain and dynamic range• Adjustment of reference hole or electron collection

VREF_ININPUT

VREF_IN = 1.5 to 3.5V

5V

GND

1 2

34

6 5

CF = 0.5pF, 1pF, 2pF, 4pF

1.0V

2.5V range (hole coll.)

4.5V

3.0V range (e- coll.)

VREF_IN=1.5V

VREF_IN=3.5V

INDIGO OPERATIONS


Low Pass Filter (LPF)

Simple first order low pass filter Limit the bandwidth (f-3dB from 32 to 200kHz)

• Noise attenuation RC filter implementation

• RC=1us with Resistor (1Meg) and Capacitor (1pF)• Resistor can be too large to implement (HiRes poly=1k/SQ)

Using transistor’s transconductance gm

• Time constant = CLPF/gm

Programmable time constant• 0.8us, 1.3us, 2.8us, 3.3us• 1us, 2us, 4us, 5us with external voltage adjustment

INDIGO OPERATIONS


Low Pass Filter (Slew / Rise Time Constraint)

Slew rate and settling • Measurement time for 14bit settling increases

for large signal amplitude due to slew rate

VP

t

SR settling

TMt2 t3t1

LPF

SRP

C

I

t

VSR

LPF

SRP

C

I

t

VSR

)()( 11

ttP eV

)(

)( 11tt

P eV

Slew rate:

Settling:

1)2ln(. NI

CVT

SR

LPFPSET

Approximation:

INDIGO OPERATIONS


4.0E-06

6.0E-06

8.0E-06

1.0E-05

0.01 0.1 1 10

Low Pass Filter Implementation

= CLPF/gmCf

out

CLPF

gm

VGS

• At t=0, VGS is large large current large SR large gm small When VLPF reaches VIN

small current (settles with )

VIN

VLPF

non-linear settling linear (no bulk effect) adjustable time constant

RC+SR

LPF

Tsettle

4us

6us

8us

10us

0.01 0.1 1 10Log(VIN)

SPICE sim.

10bit settling

RST

RC+SR

LPF

INDIGO OPERATIONS


Correlated Double Sampling Amplifier (CDS)

Remove offset and CTIA kTC noise• After integrator reset released store and subtract

kTCINTEG Reduces 1/f noise (increases thermal noise) Programmable gain

• X1, x2, x4, x8, x32

+

CLAMP2

TRACKCLAMP1 VREF_CDS

C1

C2

Gain =C1/C2

VREF_CDS

CDS_BIT[0-3]

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

)()( SCDS TfSinC

CfH

2

212 42

f(Hz)

V2/Hz

INDIGO OPERATIONS


Analog-to-Digital Converter One ADC per channel Single slope ADC

• On-chip voltage ramp generator (programmable)• Grey code counter 1 bit changing at a time

RST_ADC

RAMP_IN

VREF_ADC

RST

Signal (held)

t

ramp

RST

Inp

ut

Lat

ch

Latches

14

Cc

VREF_ADC

9-14bitGray Code

CounterGray Code

Counter

INPUT14

INDIGO OPERATIONS


ADC Ramp Generator

Clock = 40ns (twice Master clock)

VLSB = VADJ_RAMP C1

C2+CL

40ns VLSB

C2

VPOS

C1

RAMP_OUT

Non-overlappingclock

C1

GND

CL

RST_ADC

• Slope controlled by VADJ_RAMP

and the C1/(C2+CL) ratio Adjustment of the LSB level from 9bit to 14bit

• Charge pump architecture• Programmable ramp for 9 to 14 bit conversion

VADJ_RAMP

INDIGO OPERATIONS


Current Mode Output

.

CL<30pF

Low Impedance V < 50mV

VPD

Current Mode Receiver

10k

700

1V

0.5mA

ROIC

PN3640

Suggested current mode receiver

• Current mode output (0.5mA) high speed output low voltage output low power reduced clock feedthrough

CLOCK

SYNC

Data OutBIT9 BIT8 BIT7

Data rate = 12.5MHz

INDIGO OPERATIONS


ISC9717 Noise Analysis and Measurements

All noise sources taken into account

+Quantization Noise

BWAmp

VkTC

CLAMP

VkTCcds

T/H

CT/H

T/H

+

SELECT

CF

RST

vAmp

+

v1/f

VkTC

CINT

INT

LPFCC1

CC2

Vout

vLine

VkTCf

Detector Noise

2

222

)(

)()(

S

S

F

SINTEG

Tf

TfSin

C

TfH

)(42

)( 22

12SCDS TfSin

C

CfH

22

21

1

)()(

mLPFLPF

gCffH

+

For detector current integration

INDIGO OPERATIONS


Noise Acquisition

60Hz

No input cap

10pF 100pF 50pF

time

• External input capacitor added on few channels• 60Hz noise pick up from the inputs / test board Removed by subtracting 2 channels (increases the noise by √2)

128 channel

INDIGO OPERATIONS


Noise Measurement

High resolution setting:Cf = 1pF LPF=1usGainCDS = 32ADC = 14bit

• Equivalent Noise Charge (ENC) referred to the input

0

500

1000

1500

2000

2500

3000

3500

4000

0 2E-11 4E-11 6E-11 8E-11 1E-10 1.2E-10

Measurement

0

500

1000

1500

2000

2500

3000

3500

CDET0 20pF 40pF 60pF 80pF 100pF

ENC (e-RMS)

Analysis

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INDIGO OPERATIONS


Noise as a Function of LPF

CDET= 50pFCf = 0.5pF GainCDS = 8ADC = 14bit

ENC 1600e-RMS

Optimum noise for 5us LPF time constant

• Dominant thermal noise (V2RMS) 1/LPF

1000

1200

1400

1600

1800

2000

2200

0.00E+00 1.00E-06 2.00E-06 3.00E-06 4.00E-06 5.00E-06 6.00E-06LPF0 1us 2us 3us 4us 5us1000

1200

1400

1600

1800

2000

ENC (e-RMS)

Analysis

Measurement■▲

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INDIGO OPERATIONS


ISC9717 Averaging Mode Averaging mode

• SNR improvement• Increase readout rate by a factor 2

T/H

CHOLD

T/H

CHOLD

To ADC

AVG

V1

V2

Odd channel

Even channel

VAVG = (V1 + V2) / 2

SNR = (V1 + V2)

2√ (V2n1 + V2

n2)

√2 SNR improvement

INDIGO OPERATIONS


ISC9717 Performance SummarySpecifications Nominal CommentsNumber of channel 128 channel/chip 80um Input bonding pad pitch

Clock frequency 12.5MHz Low voltage differential clock

Integrator gain control CF=0.5pF, 1pF, 2pF, 4pF 2BIT gain control

Charge collection Electrons (≤ 75x106 e-)

Hole (≤ 62x106 hole)

VREF_INTEG = 1.5V for e- collection

VREF_INTEG = 3.0V for hole collection

Low-Pass-Filter time constant 0.8us, 1.3us, 2.8us, 3.3us

(1us, 2us, 4us, 5us)

2BIT (2 capacitors selectable) 10% tolerance

With external voltage adjustment

Correlated Double Sampling Gain = x1, x2, x4, x8, x32 Removes the ROIC kTC and 1/f noise

Crosstalk 0.25% (internal to ROIC)

Total power dissipation 220mW 200mW nominal

ADC resolution 9 to 14 bits (gray code output) Programmable ADC resolution

(ADC frequency=25MHz)

Current mode output 9 to14 output used Parallel output (single ended 0.5mA 20%)

ENC (GINTEG =2mV/fC,

GCDS=32, ADC=9bit)

1200 e-RMS referred to input Measured noise with 50pF input capacitor

Noise depends on systems noise performance


GCDS=8, ADC=14bit)




GCDS=1, ADC=14bit)



INDIGO OPERATIONS


Standard ASIC Product Package

ISC9717 ROICUSER MANUAL

DOC # 400-9717-10 VERSION 2.3October 14, 2003

Copyright Indigo Systems Corporation 2003

Information furnished by Indigo Systems Corporation is believed to be accurate. However, no responsibility is assumed by Indigo Systems Corporation for its use, nor for any infringements of

patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent

or patent rights of Indigo Systems Corporation.

Standard ASICs • By the die in fully tested wafer

form• 487 die / wafer

AMI 0.5um process Typical yield is above 90%

Each wafer:

complete test data on CD-ROM

CD-ROM contains PRISM test data explorer software

Physical database in GDSII format provided on CD-ROM

Complete set of documentation• Design and Users Guide• Technical Application Notes• Physical Interface Drawings

Applications engineering support

successful integration of sensor with ROIC

INDIGO OPERATIONS


Integration While Read Simultaneous integration, A/D conversion and readout Higher frame rate 28.6kHz conversion rate at 9 bit resolution (Clock = 12.5MHz) 1.49kHz conversion rate at 14 bit resolution

Stop CLK for longer integration time

tINTEG=11.68us + 2(N-1)/fCLK

INDIGO OPERATIONS


Integration Then Read Integration, ADC and readout performed sequentially Lower Noise 15.1kHz conversion rate at 9 bit ADC resolution (Clock = 12.5MHz) 1.42kHz conversion rate at 14 bit ADC resolution

Stop CLK for longer integration time

tINTEG=34.4us

INDIGO OPERATIONS


Noise Measurement (1 of 2)

High gain setting:Cf = 0.5pF LPF=1usGainCDS = 32ADC = 9bit

CBOARD 4.0pF

• Equivalent Noise Charge (ENC) referred to the input

CDET

0

500

1000

1500

2000

2500

3000

3500

4000

0 2E-11 4E-11 6E-11 8E-11 1E-10 1.2E-100

500

1000

1500

2000

2500

3000

3500

0 20pF 40pF 60pF 80pF 100pF

ENC (e-RMS)

Analysis

Measurement■

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operation a high performance, low noise, 128- channel readout integrated circuit for instrumentation...

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