operation mode: nmos - university of connecticut school …tehrani/teaching/ece3421/lec-03.… ·...
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3 March 2009 1
Gate
Source
Drain
Ids
Operation Mode: nMOS
VGS < Vtn
Gate
Source
Drain
Ids
VGS > Vtn
VGD > Vtn
Gate
Source
Drain
Ids
VGS > Vtn
VGD < Vtn
Cutoff Linear Saturation
−−=
2)(
2
DSDSTGSnDS
VVVVkI
2
)(2
TGSnDS
VVkI
−=0=DSI
3 March 2009 2
Gate
Source
Drain
Ids
Operation Mode: pMOS
VGS < Vtp
VGD < Vtp
Gate
Source
Drain
Ids
VGS < Vtp
VGD > Vtp
Gate
Source
Drain
Ids
VGS > Vtp
Cutoff Linear Saturation
−−−=
2)(
2
DSDSTGSpDS
VVVVkI
2
)(2
TGSpDS
VVkI
−−=0=DSI
3 March 2009 3
Gate
Source
Drain
Ids
Operation Region: pMOS
VGS < Vtp
VGD < Vtp
Gate
Source
Drain
Ids
VGS < Vtp
VGD > Vtp
Gate
Source
Drain
Ids
VGS > Vtp
Cutoff Linear Saturation
0=DSI
−−=
2)(
2
DSDSTGSpDS
VVVVkI
2
)(2
TGSpDS
VVkI
−=
3 March 2009 4
CMOS Inverter
First-Order DC Analysis
Vin = 0Vin = VDD
• High noise margin
• Ratioless• low output impedance
• extremely high input impedance
• no static power
Vin Vout
VDD
3 March 2009 5
CMOS Inverter: Transient Response
Vin = VDD �0 Vin = 0 � VDD
Low-to-High High-to-Low
To reduce delay:
• Reduce CL
• Reduce Rp,n
• Increase W/L ratio
Output:
CL is composed of the drain diffusion capacitances of the NMOS and PMOS transistors, the capacitance of connecting wires, and the input capacitance of the fan-out gates
3 March 2009 6
NMOS Load Lines
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I DS
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Linear Saturation
VDS= V
GS- V
T
2
3 March 2009 7
PMOS Load Lines
Vin Vout
VDD
3 March 2009 8
CMOS Inverter Load Characteristics
3 March 2009 9
CMOS Inverter VTC
VTC: Voltage-Transfer Characteristic
3 March 2009 10
CMOS Inverter VTC
Vtn Vin
Vout
VDD
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 11
CMOS Inverter VTC
Vtn Vin
VDD
Vout
Vout - |Vtp|
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 12
CMOS Inverter VTC
• Set pMOS Linear IDS equal to nMOS
Saturation IDS
( )
−−−−−=
−
2
)())((
2
22
DDoutDDouttpDDinp
tninn
VVVVVVVk
VVk
( )0
2))((
2
)(22
=−
+−−−−− tnin
p
nDDouttpDDin
DDout VV
k
kVVVVV
VV
( )22)()()( tnin
p
ntpDDintpDDinDDout VV
k
kVVVVVVVV −−−−+−−=−
( )22)()( tnin
p
ntpDDintpinout VV
k
kVVVVVV −−−−+−=
3
3 March 2009 13
CMOS Inverter VTC
Vtn
VDD
Vout
Vout - |Vtp| Vout + Vtn
Vin
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 14
CMOS Inverter VTC
Vtn
VDD
Vout
Vout - |Vtp| Vout + Vtn
Vtn VDD - |Vtp| Vin
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 15
CMOS Inverter VTC
• Set nMOS Linear IDS equal to pMOSSaturation IDS
( )( )
−−=
−−
22
22
outouttninn
tpDDin
p
VVVVk
VVVk
( )( )
022
22
=−−
+−−tpDDin
n
p
outtninout
VVV
k
kVVV
V
( ) ( ) ( )22
tpDDin
n
p
tnintninoutVVV
k
kVVVVV −−−−−−=
3 March 2009 16
CMOS Inverter VTC
Vtn
VDD
Vout
Vout - |Vtp| Vout + Vtn
Vtn VDD - |Vtp| Vin
VDD
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 17
CMOS Inverter VTC
VDD
Vin
Vout
VDD
3 March 2009 18
CMOS Inverter(assume Vt = Vtn = |Vtp|)
4
3 March 2009 19
Switching Threshold
• The point (Vm) at which the inverter has both transistors in saturation (Vin = Vout)
22)(
2)(
2tpDDM
p
tnMn VVV
kVV
k−−=−
)()(tpDDM
n
p
tnMVVV
k
kVV −−−=−
)()1(tpDDtnM
VVrVrV ++=+
r
VVrVV
tpDDtn
M+
++=
1
)(
r is the relative driving strengths of the PMOS and NMOS transistors
r
3 March 2009 20
Switching Threshold
• When Vtn = -Vtp and r = 1,
• When Vtn = -Vtp and r > 1,
r
VVrVV
tpDDtn
M+
++=
1
)(
2
DDM
VV =
2
DDM
VV > Stronger PMOS
3 March 2009 21
00.5
1
1.52
2.5
0 0.5 1 1.5 2 2.5Vin (V)
Vo
ut(V
)
Balanced
Strong PMOS
Strong NMOS
Switching Threshold
3 March 2009 22
Noise Margin
• A measure of the acceptable noise at a gate input so that the output is not affected.
• Noise margin is closely related to the DC voltage characteristics
• Sources: supply noise, crosstalk, interference
3 March 2009 23
Noise Margin
VOLmax: Maximum low
output voltage produced
by the driving gate
VILmax: Maximum low input
voltage recognized by the
receiving gate
Low Noise Margin
High Noise Margin
Logical Low Input Voltage
Logical Low Output Voltage
Output Characteristics
Input Characteristics
3 March 2009 24
Noise Margins
• Voltage Transfer Function
• Voltage Transfer Function with Noise
• Perturbed voltage is the sum of the nominal output plus the gain times the noise
• Keep the gain less than 1
)( inout VfV =
)( noiseinout VVfV ∆+=
noisein
outinout
VdV
dVVfV ∆+≈ )(
5
3 March 2009 25
Noise Margins
VDD
Vin
Vout
VDD
VOH
VOL
Undefined region
VIL
VIH
3 March 2009 26
Static Load Inverter
3 March 2009 27
Static Load Inverter
3 March 2009 28
Static Load Inverter
Linear
Mode
3 March 2009 29
Static Load Inverter
• Transistor is in linear region
−−=
2)(
2
DSDSTGSnDS
VVVVkI
−−−=
2)(
2
OUTOUTTINnDDOUT
VVVVRkVV
0)1)((2
2=++−− DDOUTTINnOUT
n VVVVRkVRk
( )n
DD
n
TIN
n
TINOUTRk
V
RkVV
RkVVV 2
11)(
2
−
+−−+−=
3 March 2009 30
Static Load Inverter
6
3 March 2009 31
Static Load Inverter
• Transistor is in saturation
)1(2
)( 2
DSTGS
nDS VVV
kI λ+−
=
)1(2
)( 2
OUTTIN
nDDOUT VVV
RkVV λ+−
−=
2
2
)(2
)(2
TINn
TINnDDOUT
VVRk
VVRkVV
−+
−−=
λ
3 March 2009 32
Static Load Inverter
VOH
VOL
Undefined region
3 March 2009 33
Static Load Inverter
• Does not go down all the way to 0 due to the resistance path between VDD and ground when nMOS is on
• Static power
• Noise margins are tighter
• Switching threshold is not centered
• To get high gain in the transition region, bigger resistors are needed