operational amplifiers: theory and...

Operational Amplifiers: Theory and Design

TU Delft, the Netherlands, November 4-8, 2019

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Operational Amplifiers, Theory and Design1

Lesson 2Noise and Input Stages

Çağrı GürleyükNovember 2019


2

Input StagesCell: 03_Input_Stages

NMOS input stage PMOS input stage

10 µA

10 µA


3

Input StagesCell: 03_Input_Stages


4

Input StagesCell: 03_Input_StagesAssignment 1 A• Plot the differential output voltage for both NMOS and

PMOS input stages using DC sweep analysisConditions: differential input signal =10mV input CM voltage in the range (0V,2.5V).


5

Input StagesTip: plotting the difference• ADE-L à Tools à Calculator• Use the VS selection tool and click on the respective

net– VS(‘VOP+’)-VS(‘VOP-’)


6

Assignment 1

-3V 3V

3V0V

0

NMOS

PMOS


7

Input StagesCell: 03_Input_Stages• Notice the different input ranges of both stages.• Notice the overlapping operating region in the middle

of the supply range.


8

Input StagesCell: 04_NoiseAssignments 2 A• Run a noise simulation• Plot output and input referred noise• By using noise summary, find the

integrated noise in 1MHz bandwidth

• Can you comment on which noise sources are dominant?


9

Assignment 2

-3V 3V

3V0V

0


10

Rail-to-Rail Input StagesTop Cell: 05_IS_RR_TopCellMain Cell: InputStage_Rail2Rail


11


12


13


14

NMOS input off

PMOS input off

NMOSOnly

PMOSOnly

VCM IN (V)

Out

put D

iffer

entia

l Cur

rent

(V)


15

Total output current

VCM IN (V)

Tota

l Cur

rent

(A)

Total Current


16

Rail-to-Rail Input StagesTop Cell: 05_IS_RR_TopCellAssignment 3 A• Plot the output current (transient analysis, 10us) of rail-

to-rail input OTA.• Plot the output currents of the PMOS and NMOS input

stages.Conditions: input differential signal=10mV.

Input CM level: sweep from 0 to 2.5V.

Notice the input range of the RR-input stage. What is the problem with the total input Gm?


17

Desired Input Stage GM vs VCM

VCM

Gm

Gm Total

Gm P Gm N


18

Input StagesRail-to-Rail Input Stage with Gm Control (InputStage_Rail2Rail_Spill)

1.25V


19

1.25V


20

Translinear Loops

M1Q1

M2

M3

M4Q2

Q3

Q4

VBE1+VBE2=VBE3+VBE4 VGS1+VGS2=VGS3+VGS4

IE1 x IE2 = IE3 x IE4 IS1 + IS2 = IS3 + IS4

Bipolar transistors CMOS transistors in strong inversion


21

Translinear Loops

M1Q1

M2

M3

M4Q2

Q3

Q4

VBE1+VBE2=VBE3+VBE4 VGS1+VGS2=VGS3+VGS4

IE1 x IE2 = IE3 x IE4 IS1 x IS2 = IS3 x IS4

Bipolar transistors CMOS transistors in weak inversion


22

I1*I2=I5*I6=(2Iref-I1)(2Iref-I2)

I1+I2=2IrefI is the current density

2x2x

4Iref

1.25V


23

2x2x

4IrefI3*I4=I5*I6

=(2Iref-I1)(2Iref-I2)I3+I4=2IrefI is the current density

1.25V


24

2x2x

4IrefTo compensate mobility difference:WPMOS =3x WNMOSThe ratio is subjected to change!

1.25V


25-2 2

3.9

4.1

4.05

4.0

3.95


26

Rail-to-Rail Input StagesTop Cell: 06_IS_RR_Spill_TopCellAssignment 4 Level A• Plot the output current (transient analysis) of the RR-spill-input OTA.• Plot the output currents of the PMOS and NMOS input stages.

Conditions: input DF signals=10mV. CM level from 0 to 2.5 V.

Notice the ratio between the input transistors and the spill-over transistors. You canmodify the ratios between the spill-over transistors and the input transistors, or the NMOS and PMOS transistors to see how they influence the total Gm.

Assignment 5 Level A• Run AC simulations and plot the open-loop gain of the rail-to-rail input OTA

Conditions: Load capacitance=10pF, VCM (VDC)= 0V, 1.25V, 2.5V.

Assignment 6 Level C• Use another method to obtain a constant Gm and optimize the cascode bias current. Tips: consult Fig. 4.4.4 on pp. 84 and Fig. 4.4.10 on pp.89. Notice the change in the total power consumption.

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