Yoshio NishiProfessor, Electrical Engineering, Material Science and Engineering

Director of Research, Center for Integrated SystemsDirector, Stanford Nanofabrication Facility

Stanford Universitynishiy@stanford.edu

The Sixth U.S.-Korea Forum on Nanotechnology, April 28-29, 2009, Las Vegas, NV

Opportunities and Challenges forNanoelectronic Devices and Processes

• CMOS Scaling is not coming to an end • 45 nm is happening • 32 nm well on its way• 22 nm will happen

• Major ongoing transformation of scaling caused by power and power/density

• End of frequency scaling of single core processor• No “10 GHz” microprocessor (with the ~100 W cooling limit)

• System performance based on multi-low-power cores and accelerators• Move away from frequency scaling

• How many “Moore” generations?• As long as we have affordable lithography

Status Quo for Status Quo for ““MooreMoore”” and and ““More MooreMore Moore””

G. Shahidi, IBM

Paradigm Shift: Hitting the Cooling Limit• Moving a high power chip to the next node (with limitation

on cooling and maximum T rise), actually will slow it down

800

900

1000

1100

1200

1300

1400

Peak Frequency(100W/cm2 cooling @ max T 85C)

50 W

72 W

40 W

100 WNo Perf. scaling(Only Shrink)

With Performance Scaling

90nm 65nm 45nm 32nm 22nm

Per

form

ance

Technology

80 W65 W

50 W

25 W

End of frequency scaling @ ~4 GHz (with 100 W cooling)?

System Performance from Multi-CoresM

odul

e H

eat F

lux(

wat

ts/c

m2 )

0

2

4

6

8

10

12

14

Vacuum IBM 360 IBM 370

IBM ES9000

IBM 3090S

IBM 3090

IBM GP

Merced

Pentium II(DSIP)

Squadrons

Pentium 4

Prescott

Low-PowerMulti-Core

Bipolar

NMOS / PMOS /CMOS

1950 1960 1970 1980 1990 2000 2010

CMOS

CMOS CMOS

Performance

Density

“Beyond Moore” On-going Trends

• Nanoelectronics: Ge, III-V channel to nanowire/nanotubes and more

• Nano-bio/medical: Bio-sensing, imaging• Energy: nanowire solar, nanotube hydrogen

storage• Environmental sensing: Sensor network,

gaseous molecules sensing, ocean, air…• Fusion of nanoelectronics and

nanomechanical: New switches and memories

Year06 07 09 10 11 12 13 14 15 1608 17 18 19 20

65nm

45nm

32nm22nm

15nm10nm

7nm?

Flash

PCRAM

ReRAMMRAM?

Strained channel

Nanowire devices/nanotubes

Molecular devices

New channel materials, Ge, III-V

Spintronics

FERAM

Organic/Molecular?

5nm?

193nm+liquid immersionEUV?

Self-assembly/bottom up?

2D chip+3D package3D chip

Emerging Bio/Medical Chips

Optimistic scenario

SOI , FD, UTB

High mobility channel Ge and its issues

• Advantages– High electron/hole mobility– Compatibility to Si LSI– Lower temperature process– Possible Vdd scaling

• Process and device Issues1. Poor interface property of Ge

MOS gate• Loss of Qch and m degradation

2. Strong Fermi-level pinning at metal/Ge contact

• Increase contact resistance3. Small electron mobility gain

• Require mobility booster4. Poor N-type dopant activation5. Band-to-band tunneling leakage

0.661.12Band gap (eV, 300K)

1900430Hole µ (cm2/Vs)

1611.9Dielectric constant

39001600Electron µ (cm2/Vs)

GeSi

S D

G13 4

2

5Ge

Si or SiO24

NMOS Performance Comparison Simulation

S D

G

G

Channel

Gate dielectric LG=15 nm

TOX=0.7 nmVG=0.7V

Si GaAs InP Ge InAs InSb0

2

4

6

8

vinj

(107 cm

/s)

10nm5nm3nm

Si GaAs InP Ge InAs InSb0

5

10

15

Qi (

1012

#/cm

2 )

10nm5nm3nm

Channel Charge (Qi) Injecion Velocity (Vinj)

Si high Qi low VinjIII-V low Qi high VinjGe reasonably high Qi and Vinj has highest IONEffect of strain is being modeled

Si GaAs InP Ge InAs InSb0

1

2

3

4

5

6

ION (m

A/ µ

m)

10nm5nm3nm

On current (ION)

Kim, Krishnamohan & Saraswat, IEEE DRC 2008

Non-silicon high mobility channel approaches

• It will fulfill the needs for “higher speed and lower power consumption”

• High mobility materials-gate insulator interface is the biggest issue

• Ge option may provide an opportunity for on-chip optical interconnect; at least for detector, and maybe for transmitter

• Integration density would stay with Si VLSI trend line (ITRS)

• Preferential application on top of the Si platform looks rational option to go

ON/OFF & Bandgap vs. width for GNRs

0.5

0.4

0.3

0.2

0.1

0.0E

g(e

V)

50403020100W (nm)

100

101

102

103

104

105

106

107

I on/

I off

50403020100W (nm)

)/exp( /II offon TkE Bg=

( ) ( )nmWeVEg

8.0=

• All (> 40) sub-10nm GNRs measured thus far are semiconducting with high on/off switching at 300K

H. Dai, Stanford, 08

16

14

12

10

8

6

4

2

I on(

µΑ)

100 10

2 104 10

6

Ion/Ioff

Graphene ribbon vs. Carbon Nanotube

GNR w~3nm L~100nm

GNR w~2nm L~236nmSWNT d~1.6nm L~102nmSWNT d~1.6nm L~254nmSWNT d~1.3nm L~110nmSWNT d~1.1nm L~254nm

d~1.6nm, L~100nm

d~1.6nm, L~250nm

d~1.3nm, L~100nm

d~1.1nm

High on/off GNR comparable to~1.2nm SWNT FETsGNR FETs comparable to high performance SWNT FETs(d~1.4-1.5nm) remains illusive H. Dai, Stanford, 08

Integration Challenges of CNT, GNR etc

• Enough performance advantage over other options as individual devices

• A large variety of tunability for the band structure for a number of applications

• Questions for controlled growth for nanowires and nanotubes still remain without sacrificing integration density

• No top down lithographic technology for the geometry ranges of GNR

• Variability

Integration of Electronics into Cells

• nanoscale-functionalized probes at the end of AFM cantilever tips that can directly integrate into a cell membrane.

• “stealth electrodes” do not cause membrane damage, and specifically attach to the core of the lipid bilayer.

• future work will involve fabrication of planar arrays of the devices for on-chip electrophysiological measurements.

Professor Nicholas Melosh, Department of Materials Science and Engineering, Stanford University

10 nm

Si

Au

A nanoprobe tip.

AFM force measurements of the tip interaction with the bilayer.

Adhesion force

Nanowire Dye-Sensitized Solar-Cells

Dye-sensitized solar cell is one of the most promising third generation solar cells. Using semiconductor nanowires array, as the electron conducting material to replace nanoparticle film, can achieve both a large surface area and a low intrinsic resistance as well as an improved energy conversion efficiency.

The idea of this project is: First, using templated Sol-Gel method to grow high aspect ratio and high density TiO2nanowire array; Secondly, providing bonding of the wire array to a transparent and conductive layer by “after-growth”deposition of materials like ITO onto the back of the nanowire array; Then, dissolving the template following attaching the sample onto a substrate; Finally, this substrate can serve as the anode of the dye-sensitized solar cell.

The above nanowire fabrication method can exceed VLS or CVD in aspect ratio and density, and exceed powder based porous array deposition in minimized grain boundaries existing in the electron diffusion paths.

Template

NanowiresAfter Dissolving Template

Sputtering ITO

ITO

Scale bar: 2um

Ying Chen and Yoshio Nishi

Summary

• A large variety of opportunities in revolutionary “nano” spaces, from traditional electronics to bio/medical, energy and environment

• Manufacturing strategy is still missing and challenges in “variability”, “reproducibility”, “cost” and “reliability” requires strong attentions