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Optical Computing on Photonic Integrated Circuits
David Z. PanDept. of Electrical and Computer Engineering
The University of Texas at Austin
Acknowledgment
t Prof. Ray T. Chen at UT Austint Graduate students at UT
› Zheng Zhao› Zhoufeng Ying› Chenghao Feng› Shounak Dhar
t Sponsored by the DoD MURI (Multi-University Research Initiative) Program at UT Austin
2
Optical Computingt Early days: free-space, e.g., Fourier transform
› Large devices not friendly to scaling and integrationt Photonic integrated circuits (PICs) based on silicon-on-
insulator (SOI) › CMOS-compatible process › Monolithic integration of electronics and photonics
3
Optical Computing Components
t Micro-resonator based optical switches› Can be implemented with micro-rings/micro-disks
λ through
drop
2x2 optical switch
Ideal transmission
Optical Computing Components
t Y-branch combiner vs. directional coupler› Only one input will be light-on
t Size of a Y-branch – very smallt Size of a coupler ≈ 2x micro-resonator switch
In1
In2
Outk
In1
In2
Out
Pout = 0.5 PIn1Pout = 0.5 PIn2
Pout = k PIn1Pout = (1-k) PIn2
k: coupling constant
Power efficiency factor = Pout/Pin
Outline
t Introductiont Optical Adder Designst Optical Logic Synthesist Optical Neural Networkt Conclusion
6
Directed Logic Based EO Computing Architecture
7
All electrical SIMD architecture
Hybrid electrical-optical (EO) architecture• Light in, light out• No OE/EO conversion in OLU
Building Blocks for Directed Logics
8
[Zamir+, IEEE Photonics Soc. Opt. Interconnects Conf. OI’2017]
Schematic of Electrical and Optical Full Adders
9
2M design for each-bit [Ying+, Opt. Lett’2018, Ying+ CLEO’2017]
Signal Symbol Transitional signals Expression Transfer function Addends !", #" ‘Propagate’ $" $" = !" ⊕#" '" = $" ( '")* + ,"
Carry, Sum '", -" ‘Generate’ ," ," = !" ( #" -" = '")* ⊕ $"
Electrical vs. Optical Full Adder
10
Electrical full adder
Opticalfull adder
Latency of optical full adder
Latency of electrical full adder
,p g epbT nT T+ ´= ,p g sw opbT T T T n= + + ´
Reduced to
opb epbT T
Delay for generating P and G
Switch time of modulators
Optical propagation delay per bit
Electrical delay per bit
!",$ !%& !'"( !)"(
Candidates for EO Modulators
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MZIElectrical
AbsorptionModulator
Micro-ring Micro-disk
Footprint ~2,000×500 μm2 ~40×10 μm2 ~10×10 μm2 ~5×5 μm2
Wavelength-division
multiplexing
Multiple deviceswith extra
MUX/DEMUX
Multiple deviceswith extra
MUX/DEMUX
Multiple devicesonly
Multiple devices only
Industrymaturity
Available in PDKs offered by foundries
Available in PDKs offered by foundries
Available in PDKs offered by foundries
Available in PDKs offered by foundries
Insertion loss ~2.2 dB ~4.4 dB ~2.8 dB ~0.9 dBExtinction ratio ~4.1 dB ~4.2 dB ~6.6 dB ~ 7.8 dB
Expected energy
consumption~750 fJ/bit ~20 fJ/bit ~50 fJ/bit ~1 fJ/bit
[Timurdogan+, Nat. Commun’ 2014, Pantouvaki+, JLT’2017] [Ying+, APL’18]
Latency
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!",$ Delay for generating P and G
!%& Switch time of modulators
!'"( Optical propagation delay per bit
!)')*+ Total latency
!)')*+ = !",$ + !%& + !'"(× /!",$ = 1223!%& = 5023!'"( = 0.623
Power Consumption Comparison
13
t Calculation is based on 32nm node library
2-bit Thermal Optical Adder Fabrication and Measurement
14
[Ying+, Optics Letters 2018]
Experiment Results
15
AIM Chip
16
The chip is under test
2-bit full adder
4-bit full adder
4 mm
2 mmTesting area
Outline
t Introductiont Optical Adder Designst Optical Logic Synthesist Optical Neural Networkt Conclusion
17
λ S
a10
PD
CB
S
b10
S 1
c CB
S CB PDopticalswitch
combiner photodetector
a
b
1
f
c
BDD Based Optical Implementation
t Data structure and direct implementation
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Binary decision diagram(BDD)
Optical direct implementation:each multi-parent BDD nodehas a combiner
t Due to BDD’s single-path property, any combiners have at most one light input
t Power is cut by half (-3dB)
Problem with Direct Implementation
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Binary decision diagram (BDD)
Light stream to the lower/upper input port
a
b
1
f
c
abc = 101
Our Proposed Techniques
t Our goal: to improve the worst-case network optical power efficiency under a reasonable overhead and computational budget
t Two key techniques are proposed› Combiner elimination to avoid cascaded combiner
loss› Coupler assignment to redistribute the power
resourcet Applicable to any BDD-based architecture
› Not restricted by specific types of optical switches
20
λ S
a10
PD
S
b10
S 1
c CB
S 1
t Idea: avoid cascaded combiner loss› e.g., for abc=101
Technique 1: Combiner Elimination
1/4
1/3
Greater combiner loss at theterminal but not cascaded
a
b
1
f
c
λ S
a10
PD
CB
S
b10
S 1
c CB
1/2
0a
b
1
f
c c
λ S
a10
PD
CB
S
b10
S 1
c DC
t Idea: redistribute the power with directional couplers (DCs) instead of combiners
t Assign the coupling efficiency for each DC
Technique 2: Coupler Assignment
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1
1/2
1/3
*1/3
*2/3
Optical Power EfficiencyW
orst
-cas
e Te
rmin
alO
ptic
al P
ower
Effi
cien
cy (d
B)
Prev. work: [Wille+, ASPDAC’2015]Average power efficiency ratio over prev.: 27.02 x
Average/greatest CPU time: 1.88s / 14.5s
[Zhao+, ASPDAC’18]
And-Invertor Graphs (AIG) Based Logic Synthesis
§ Basic gates: three categories based on E/O interfaces§ And-Invertor Graphs (AIGs) based logic synthesis
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Basic Gate Library
[Ying+, Optics Express 2018]
AIG-Based Logic Synthesis
25[Ying+, Optics Express 2018]
AIG Optical Logic Examples!"# = (& + ()(* ⊕ , + -).
/012 = /34 · (& ⊕ () + & · (Full adder For each bit:
Elements in library Circuit size Redundancy GeneralityBDD Only one Large Large YesAIG Many, scalable Small Small No*
[Ying+, Optics Express 2018]
BDD vs. AIG Example
27
c d
output
E-XOR
O-OR
a b
E-XOR
!"# = a⊕ ' + ) ⊕ *
a
b
1
out
b
c
dd
BDD
AIG
AIG-based with multi-operand gates
BDD-based approach
Outline
t Introductiont Optical Adder Designst Optical Logic Synthesist Optical Neural Networkt Conclusion
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t Potential to achieve ~0 energy and speed of light for inference
Optical Neural Network (ONN)
…
……
Tn,1…Tn,n-1
Tn-1,1…Tn-1,n-2
T3,1…T3,2T2,1
Shen et al. Nature Photonics (2017).
SVD-decompositionweight matrix to U Σ V*
Transfer function of an n-dim MZI array:
ϕ
Inputcoupler
Outputcoupler
Mach-Zehnder interferometers (MZI) for SU(2)
ith row
jth row
ith column jth column
Transfer function:
Expand to n-dim:
Basic architecture for each MLP layer
MZI array for unitary
UV* Σx actf… …… y
W
Linear transform(MZI array)
Non-linear activation
(saturable absorber)
Proposed Co-design Methodt Software hardware co-design to reduce # of MZIs by co-
training weights with simpler hardware architecture
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Prop
osed
arch
itect
ure
3rd subtree
2nd subtree
1st subtree
inpu
ts
outp
uts
3rd subtreein
puts
outp
uts
Tree network (T) w/ single-out MZI or directional coupler
Prev
ious
UV* Σx actf… …… y
W = U Σ V*[m x n]
[n x 1] [m x 1][n x n] [n x m] [m x m]
# of MZI ~ (n^2+m^2)/2
TΣ Ux actf… …… y
W T U Σ[m x n]
[n x 1] [m x 1][n x n] [n x n] [m x n]
# of MZI ~ n^2/2
[Zhao+, ASPDAC 2019]
Proposed Co-design Methodt Previous way
› Train W directly › Use SVD-decomp to
obtain U, Σ, V*
t Training (software) and optical implementation (hardware) is separate
SVD decomp.
Trainingvariables
Optical Implementation
UV* ΣW
t Proposed co-design› T and Σ: Embed the device
parameters in training › U: Add unitary regularization and
approximate the trained U with the closest true unitary
t Training and implementation is closely related
ΣT
Trainingvariables
Optical Implementation
Uapprox. U(with reg.)
ΣT
=
=
Resultst Dataset: MNIST
› Much less # of MZIs (e.g., 50%)› Similar accuracy
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Accuracy
# of MZI’s
ONN configuration:
[Zhao+, ASPDAC 2019]
Results
33
t Better resilience to phase noise due to less cascaded components
Previous ONN Our ONN
[Zhao+, ASPDAC 2019]
Conclusion
34
t Optical computing with SOI-based PICs › CMOS-compatible › Applications such as large-bit carry-ripple adders› General optical logic synthesis› Specialized applications for optical neural network
t Still many challenges yet opportunities› Optical power loss and noise› Better devices and system integration› Optical still bulky compared to CMOS
» Shall work together with CMOS» New circuit/architecture (e.g., WDM) to scale
› Optical interconnect, memory (?)