optical receiver2 (1)

7/30/2019 Optical Receiver2 (1)

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Optical Receiver Design

ECE 453 FinalPresentation

Dave Bowen

Wei Min Chan

Ben Cipriany

Kent En Loh

December 2nd 2005


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Optical Network Motivations

Data transmission occurs typically atbasebandoptical wavelengthsfrequency is the carrier

Short, medium, and long-haulapplications

Typically high-data ratecommunications

Low extrinsic noise and interference atoptical frequencies

http://www.jdsu.com/site/primer/launch.html


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Basic Optical Receiver Front-End

Current to VoltageSignal Conversion

PhotodiodeTransimpendence

Amplifier (TIA)

Limiting

Amplifier (LA)

Output

Buffer (OB)

Automatic Gain

Control (AGC)

To Maintain SignalLinearity andGain Level

Reshapes Signal forInput to Digital

System

Output Drive andCircuit Buffer

Optical IN -> Electrical OUT


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Optical Receiver Application

Requirements General:

Low-noise electronics for optical to electrical signal conversion Short to medium haul application 2+ Gbps data rate

Input side: InGaAs Photodiode with junction capacitance ~ 100 fFs Optical powers ranging from -20 to +10 dBm, causing input

currents from 10uA to 10mA

Output side: Drive a capacitive load representing subsequent MOSFET gate Digital signal RZ-type output


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Transimpedance Amplifier

Adjustable gain

Prevent damage to subsequent stages

Maximize range of small-signal operation

Prevent data distortion from clipping Output 100+ mV to LA stage for proper operation

Simple and fast

Must provide 2+ GHz bandwidth over entire adjustablerange

Be able to provide a consistent DC bias level at stageoutput


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Variable Gain TIA

Common gateconfiguration

All NFETs formaximum bandwidth

Gain adjustmenttransistor operating inlinear regime

Fixed Gain DifferentialAmplifier Cascade

Basic NFETdifferential pairdesign for maximumbandwidth


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Achieved Specifications:

Variable Gain TIA

Bandwidth: 2.4 GHz+ (Over all gainlevels)

Variable Transimpedance Gain: 50620

Current Consumption: ~250 uA (for a2.5 single supply)

Fixed Gain Differential Amplifier Cascade Bandwidth: 2.2 GHz (Over all input

levels)

Composite Fixed Gain: 15


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Transimpedance Amplifier:

Adjustable Gain

Output Voltage vs. Time for Varying Current InputInput Conditions: 2GHz, square pulse, 50% duty cycle


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Linear Dynamic Range

Output Voltage vs. Time for Varying Current Input

Input Conditions: 2GHz, square pulse, 50% duty cycle


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Linear Dynamic Range

Output Voltage vs. Time for Varying Current Input

Input Conditions: 2GHz, square pulse, 50% duty cycle


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Automatic Gain Controller (AGC)


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Assume AC signal centered around some DCoffset

Mean of any periodic DC offset signal will bethe DC OffsetHow do we measure the ACportion?

Solution? Use the square of the input AC Signal.


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Envelope Detector: Math

This is the expected output of mixed

and integrated sinusoid with DC

voltage offset:

2

2

0

2

0

*2

0

22

0

02

2

0

2

0

2

0

22

0

2

0

2

0

*202

1)sin(

**2)(sin

2

)*)sin(*2)(sin(2

1

))sin((2

1

dc

pi

dc

dc

dcdc

dc

VA

dtVtdtVA

tdtA

dtVVtAtA

dtVtA

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.53.12

3.14

3.16

3.18

3.2

3.22

3.24

3.26

3.28Envelope detector Output

OutputDC

Voltage

Input AC Magnitude


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0 50 100 150 200 250 300 350 4000.5

1

1.5

2

2.5

3

3.5 Signal Input

Voltage

Time


AGC Input Signal


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0 50 100 150 200 250 300 350 4000.5

1

1.5

2

2.5

3

3.5 Mixer Output

Voltage

Time


AGC Output DC voltage


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Automatic Gain Control (AGC)

AGC response to varying input AC magnitudes


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AGC Signal response through output CS amplifier cascade


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Fanning effect of output amplifiers in AGC circuit


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TIA output controlled by AGC output


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Limiting Amplifier - Design

Considerations

TIA output - few hundred millivolts

To drive digital circuitry as our load

LA outputneed signal swing close to logicallevels

Need high voltage gain and swing

Bandwidth-Gain trade off Cascaded amplifier stages of diff amps


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Cascade Issues


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Gain-Bandwidth Trade-off

Higher, lower gain


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Limiting Amplifier - Schematic


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Differential Amplifier - Schematic


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Schmitt Trigger


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Limiting Amplifier - Simulation

LA output with noisy input


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Output Waveform of LA


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Output Buffer Signal vs. Time for Varying Current Inputs

Output Buffer Stage


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Output Buffer Implementation


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Output Buffer Stage


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Description

Cascaded inverter topology

Why use inverters?

Boost output of previous stage up to rail-to-rail voltage for driving

minimal inverter

First inverters have small swing and act as linear amplifiers

Somewhere in the chain it is amplified until it clips against the powersupply.

Subsequent inverters shape the signal by giving it faster rise and fall times.

Advantages

Large dynamic range

Simple design => less poles => easier to achieve high bandwidth

Output Buffer Topology


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Analog Option - Inductive Peaking Buffer


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Performance Review

Input Dynamic Range: 50uA - 5mA (+- 10% Non-linearity)

Bandwidth: 2.0 GHz

Bit rate: 4.0 Gbps (depending on coding)

Maximum Power Consumption: 108mW (2.5V supply)

Additional Tests to be Performed

CMRR and PSRR Operational Temperature Range

Extrinsic and Intrinsic Noise Affect on Dynamic Range

Etc.


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References

High Speed CMOS Circuits for Optical Receivers. J. Savoj andB. Razavi. Kluwer Academic Publishers, 2001.

Integrated CMOS Circuits for Optical Communications.M.Ingels and M.Steyaert. Springer Publications, 2004.

Optical Communication Receiver Design. S. Alexander. SPIEPress, 1997.


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Questions?

Thank you!


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