oses: 8. mem. mgmt. 1 operating systems v objectives –describe some of the memory management...

OSes: 8. Mem. Mgmt. 1

Operating SystemsOperating Systems

ObjectivesObjectives– describe some of the memory management describe some of the memory management

schemes used by an OS so that several schemes used by an OS so that several processes can be in memory (RAM) at onceprocesses can be in memory (RAM) at once

Certificate Program in Software DevelopmentCSE-TC and CSIM, AITSeptember -- November, 2003

8. Memory Management(Ch. 8, S&G)

ch 9 in the 6th ed.


ContentsContents

1.1. BackgroundBackground

2.2. Logical vs. Physical Address SpacesLogical vs. Physical Address Spaces

3.3. SwappingSwapping

4.4. Partition AllocationPartition Allocation

5.5. PagingPaging

6.6. SegmentationSegmentation


1. Background1. Background Fig. 8.1, p.241;VUW CS 305

Source

Compiler

Object

Linker

LoadModule

Loader

ExecutableImage

ObjectLibraries

SystemLibraries

DynamicLibraries

compile tme load time execution


1.1. Address Binding1.1. Address Binding compile timecompile time

– the compiler knows where a process will the compiler knows where a process will reside in memory so generates reside in memory so generates absolute codeabsolute code (code that starts at a fixed address)(code that starts at a fixed address)

load timeload time– the compiler does not know where a process the compiler does not know where a process

will reside so generates will reside so generates relocatable coderelocatable code (its (its starting address is determined at load time)starting address is determined at load time)

continued


execution timeexecution time– the process can move during its execution, so the process can move during its execution, so

its starting address is determined at run timeits starting address is determined at run time


1.2. Dynamic Loading1.2. Dynamic Loading

A routine (function, procedure, library, A routine (function, procedure, library, etc.) is not loaded until is is called by etc.) is not loaded until is is called by another programanother program– the routine must be stored as relocatable codethe routine must be stored as relocatable code

Unused routines are never loadedUnused routines are never loaded– saves spacesaves space


1.3. Dynamic Linking1.3. Dynamic Linking

Often used for system librariesOften used for system libraries– e.g. e.g. Dynamically Linked LibrariesDynamically Linked Libraries (DLLs) (DLLs)

The first call to a DLL from a program causes The first call to a DLL from a program causes the linking in and loading of the librariesthe linking in and loading of the libraries– i.e. linking/loading is determined at run timei.e. linking/loading is determined at run time

continued


Allows libraries to be changed/moved since Allows libraries to be changed/moved since linking/loading information is not fixed (as linking/loading information is not fixed (as much) in the calling program.much) in the calling program.


1.4. Overlays1.4. Overlays

Keep in memory only those pieces of code Keep in memory only those pieces of code that are needed at any given timethat are needed at any given time– saves spacesaves space

ExampleExample: a two-pass assembler: a two-pass assembler– Pass 1Pass 1 70K70K

Pass 2Pass 2 80K80KSymbol tableSymbol table 20K20KCommon routinesCommon routines 30K30K

continued


Loading everything requires 200KLoading everything requires 200K Use two overlays:Use two overlays:

– A: symbol table, common routines, pass 1A: symbol table, common routines, pass 1 requires 120Krequires 120K

– B: symbol table, common routines, pass 2B: symbol table, common routines, pass 2 requires 130Krequires 130K


3. Logical vs. Physical Address Space3. Logical vs. Physical Address Space

The user sees a The user sees a logical viewlogical view of the memory of the memory used by their codeused by their code– in one piece, unmovingin one piece, unmoving– sometimes called a sometimes called a virtual address spacevirtual address space

This is mapped to the This is mapped to the physical address spacephysical address space– code may be located in parts/partitioncode may be located in parts/partition– some parts may be in RAM, others in backing some parts may be in RAM, others in backing

storestorecontinued


The mapping from logical to physical is The mapping from logical to physical is done by the done by the Memory Management Unit Memory Management Unit (MMU).(MMU).

HidingHiding the mapping is one of the main aims the mapping is one of the main aims of memory management schemes.of memory management schemes.


Example: Dynamic RelocationExample: Dynamic RelocationFig. 8.3, p.246

relocationregister

14000

+

MMU

CPU

logicaladdress

346

physicaladdress

14346

memory


3. Swapping3. Swapping

If there is not enough memory (RAM) for If there is not enough memory (RAM) for all the ready processes then some of them all the ready processes then some of them may be swapped out to backing store.may be swapped out to backing store.

They will be swapped back in when the OS They will be swapped back in when the OS can find enough memory for them.can find enough memory for them.

continued


P1

P2

OS

swap out

swap in

user space

Fig. 8.4, p.247

continued

DiagramDiagram


With compile time / load time address With compile time / load time address binding, the process must be swapped binding, the process must be swapped back to its old locationback to its old location– no such need for processes with execution no such need for processes with execution

time address bindingtime address binding

Must be careful not to swap out a process Must be careful not to swap out a process that is waiting for I/O.that is waiting for I/O.


The Ready QueueThe Ready Queue

The ready queue consists of:The ready queue consists of:– processes in memory that are ready to runprocesses in memory that are ready to run

– processes swapped out to backing store that processes swapped out to backing store that are ready to runare ready to run

they will need to be swapped back in if they are they will need to be swapped back in if they are chosen by the CPU schedulerchosen by the CPU scheduler


Swap TimesSwap Times

The speed of swapping affects the design The speed of swapping affects the design of the CPU schedulerof the CPU scheduler– the amount of execution time it gives to a the amount of execution time it gives to a

process should be much greater than the swap process should be much greater than the swap time to bring it into memorytime to bring it into memory


Swap Time ExampleSwap Time Example Assume a transfer rate of 1MB/sec.Assume a transfer rate of 1MB/sec.

A transfer of 100K process will take:A transfer of 100K process will take:– 100/1000 = 100 ms100/1000 = 100 ms

Total swap time:Total swap time:= transfer out + transfer in + (2 * latency)= transfer out + transfer in + (2 * latency)

= 100 + 100 + (2 * 8)= 100 + 100 + (2 * 8)

= 216 ms= 216 ms


4. Partition Allocation4. Partition Allocation

Divide memory into a fixed no. of Divide memory into a fixed no. of partitions, and allocate a process to each.partitions, and allocate a process to each.

Partitions can be different Partitions can be different fixedfixed sizes. sizes.

continued

16 16 32 64 128


Processes are allocated to the smallest Processes are allocated to the smallest available partition. available partition.

Internal fragmentationInternal fragmentation will occur: will occur:


4.1. Variable-size Partitions4.1. Variable-size PartitionsFig. 8.7, p.252

OS

user space

0

400K

2560K

2160K

process memory time P1 600K 10 P2 1000K 5 P3 300K 20 P4 700K 8 P5 500K 15

Job Queue


Memory AllocationMemory Allocation Fig. 8.8., p.253

OS0

400K

2560K

P1

P2

P3

1000K

2000K

2300K

P2ends

OS0

400K

2560K

P1

P3

1000K

2000K

2300K

P4allocated

continued


OS0

400K

2560K

P1

P3

1000K

2000K

2300K

P1ends

OS0

400K

2560K

P3

1000K

2000K

2300K

P5allocated

continued

P41700K

P4allocated

P41700K


OS0

400K

2560K

P3

1000K

2000K

2300K

P5allocated

P41700K

P5900K external

fragmentationdevelops


4.2. Dynamic Storage Allocation4.2. Dynamic Storage Allocation

Where should a process of size N be stored Where should a process of size N be stored when there are a selection of when there are a selection of partitions/holes to choose from?partitions/holes to choose from?

First fitFirst fit– allocate the allocate the firstfirst hole that is big enough hole that is big enough– fastest choice to carry outfastest choice to carry out

continued


Best fitBest fit– allocate the allocate the smallestsmallest hole that is big enough hole that is big enough– leaves smallest leftover holeleaves smallest leftover hole

Worst fitWorst fit– allocate the allocate the largestlargest hole hole– leaves largest leftover holeleaves largest leftover hole


4.3. Compaction4.3. Compaction Fig. 8.10, p.255

OS0

400K

2560K

P3

1000K

2000K

2300K

P41700K

P5900K

OS0

400K

2560K

P31900K

P41600K

P5900K


Different StrategiesDifferent Strategies Fig. 8.11, p.256

OS0

300K

2100K

P4

600K

1500K

1900K

P31200K

P1500K

original allocation

P2

1000K

moved 600K

OS0

300K

2100K

P4

600KP3

1200K

P1500KP2

800K

Version 1


OS0

300K

2100K

P4

600K

1500K

1900K

P31200K

P1500K

original allocation

P2

1000K

moved 400K

OS0

300K

2100K

P3

600KP4

1200K

P1500KP2

1000K

Version 2

Or:Or:


OS0

300K

2100K

P4

600K

1500K

1900K

P31200K

P1500K

original allocation

P2

1000K

moved 200K

OS0

300K

2100K P3

600K

P41900K

P1500KP2

1500K

Version 3

Or:Or:


5. Paging5. Paging

Divide up the logical address space of a Divide up the logical address space of a process into fixed size process into fixed size pagespages..

These pages are mapped to same size These pages are mapped to same size framesframes in physical memory in physical memory– the frames may be located anywhere in memorythe frames may be located anywhere in memory


5.1. The Basic Method5.1. The Basic Method

Each logical address has two parts:Each logical address has two parts:< page number p, page offset d >< page number p, page offset d >

A A page tablepage table contains the mapping from a contains the mapping from a page number to the base address of its page number to the base address of its corresponding frame.corresponding frame.

Each process has its own page tableEach process has its own page table– stored in its PCBstored in its PCB


Paging HardwarePaging Hardware Fig. 8.12, p.258

CPU

logicaladdress

physicaladdress

physicalmemory

p d f d

f

p


5.2. Size of a Page5.2. Size of a Page

The size of a page is typically a power of 2:The size of a page is typically a power of 2:– 512 (2512 (299) -- 8192 (2) -- 8192 (21313) bytes) bytes

This makes it easy to split a machine This makes it easy to split a machine address into page number and offset parts.address into page number and offset parts.

continued


For example, assume: For example, assume: – the address space is 2the address space is 2mm bytes large bytes large– a page can be 2a page can be 2nn bytes in size (n < m) bytes in size (n < m)

The logical address format becomes:The logical address format becomes:

page number n page offset d

m-n n


5.3. Example5.3. Example

Address space is 32 bytes (2Address space is 32 bytes (255)) Page size: 4 bytes (2Page size: 4 bytes (222)) Therefore, there can be 8 pages (2Therefore, there can be 8 pages (233))

Logical address format:Logical address format:

p.258


3 2


Fig. 8.14, p.260

0 a1 b2 c3 d4 e5 f6 g7 h8 i9 j10 k11 l12 m13 n14 o15 p

logicalmemory

5

6

1

2

0

1

2

3

pagetable

0

4 i j k l8 m n o p12

16

20 a b c d24 e f g h28

physical memory


Using the Page TableUsing the Page Table

Logical AddressLogical Address Physical AddressPhysical Address00 (5*4) + 0 = 20 (5*4) + 0 = 20

33 (5*4) + 3 = 23 (5*4) + 3 = 23

55 (6*4) + 1 = 25 (6*4) + 1 = 25

1414 (2*4) + 2 = 10 (2*4) + 2 = 10


5.4. Features of Paging5.4. Features of Paging

No external fragmentationNo external fragmentation– any free frame can be used by a processany free frame can be used by a process

Internal fragmentation can occurInternal fragmentation can occur– small pages or large pages?small pages or large pages?

There is a clear separation between logical There is a clear separation between logical memory (the user’s view) and physical memory (the user’s view) and physical memory (the OS/hardware view).memory (the OS/hardware view).


5.5. Performance Issues5.5. Performance Issues

Every access must go through a page tableEvery access must go through a page table Small page table Small page table registers registers Large page table Large page table table in memory table in memory

– a memory access requires indexing into the a memory access requires indexing into the page table page table andand a memory access a memory access

Translation Look-aside BufferTranslation Look-aside Buffer (TLB) (TLB)– sometimes called an “associative cache”sometimes called an “associative cache”


5.6. Paging with a TLB5.6. Paging with a TLB Fig. 8.16, p.264

CPU

logicaladdress

physicaladdress

physicalmemory

p d

f d

f

pTLB

TLB hit

TLB miss

p f


PerformancePerformance Assume:Assume:

– memory access takes 100 nsecmemory access takes 100 nsec– TLB access takes 20 nsecTLB access takes 20 nsec

A 80% hit rate:A 80% hit rate:– effective access time iseffective access time is

== (0.8 * 120) + (0.2 * 220)(0.8 * 120) + (0.2 * 220)== 140 nsec140 nsec

– 40% slowdown40% slowdown in the memory access time in the memory access time

TLB +page table +memory access

continued



== (0.98 * 120) + (0.02 * 220)(0.98 * 120) + (0.02 * 220)== 122 nsec122 nsec



5.7. Multilevel Paging5.7. Multilevel Paging

In modern systems, the logical address In modern systems, the logical address space for a process is very large:space for a process is very large:– 223232, 2, 26464 bytes bytes– virtual memory allows it to be virtual memory allows it to be biggerbigger than than

physical memory (explained later)physical memory (explained later)– the page table becomes the page table becomes tootoo large large


ExampleExample

Assume:Assume:– a 32 bit logical address spacea 32 bit logical address space– page size is 4K bytes (2page size is 4K bytes (21212))



20 12

continued


The page table must store 2The page table must store 22020 addresses addresses (~ 1 million), each of size 32 bits (~ 1 million), each of size 32 bits (4 bytes)(4 bytes)– 4 MB page table4 MB page table– too bigtoo big

SolutionSolution: use a : use a two-level paging schemetwo-level paging scheme to make the page tables smaller.to make the page tables smaller.


Two-level Paging SchemeTwo-level Paging Scheme In essence: “page the page table”In essence: “page the page table”

– divide the page table into two levelsdivide the page table into two levels


– p1 = index into the p1 = index into the outer page tableouter page table– p2 = index into the page obtained from the p2 = index into the page obtained from the

outer page table outer page table

page number

page offset dp1 p2


DiagramDiagramFig. 8.18, p.266

:1

500

:100

708

:929

900

:

:

pg 0pg 1

pg 100

pg 500

pg 708

pg 929

pg 900

:

:

:

:

:

:

memory

pages

page tables

::

outer pagetable


Address TranslationAddress Translation Fig. 8.19, p.267

p1

p2

d

desired page

page table

outer pagetable

p1 p2 d

logical address


Two-level Page Table SizesTwo-level Page Table Sizes Assume the logical address format:Assume the logical address format:

The outer page table (and other page tables) The outer page table (and other page tables) will contain 2will contain 21010 addresses (~1000) , each of addresses (~1000) , each of size 32-bits (4 bytes)size 32-bits (4 bytes)– table size = 4Ktable size = 4K

page number

page offset dp1 p2

10 10 12


Three-level Paging SchemeThree-level Paging Scheme For a 64-bit logical address space, three For a 64-bit logical address space, three

levels may be requires to make the page levels may be requires to make the page table sizes manageable.table sizes manageable.

Possible logical address format:Possible logical address format:

page number

page offset dp1 p2

10 10 12

p3

32

continued


But now the But now the second outer page tablesecond outer page table (the new p1) will have to store 2(the new p1) will have to store 23232 addressesaddresses– go to a four-level paging scheme!go to a four-level paging scheme!


Three-level Paging SlowdownThree-level Paging Slowdown

Assume:Assume:– there is a TLB cache, with access time 20 nsecthere is a TLB cache, with access time 20 nsec– memory access takes 100 nsecmemory access takes 100 nsec


== (0.98 * 120) + (0.02 * 420)(0.98 * 120) + (0.02 * 420)== 126 nsec126 nsec


TLB +3 levels +memory access


5.8. Inverted Page Table5.8. Inverted Page Table

A page table maps each page of a process A page table maps each page of a process to a physical frame.to a physical frame.

If If virtual memoryvirtual memory is used, many tables may is used, many tables may refer to the same framesrefer to the same frames

virtual memory is explained in the next chapter virtual memory is explained in the next chapter

Each table may have millions of entries.Each table may have millions of entries.

continued


An An inverted page tableinverted page table has one entry for has one entry for each frame, which says which PID (process each frame, which says which PID (process ID) and page are using it (currently)ID) and page are using it (currently)– reduces the amount of physical memory reduces the amount of physical memory

required to store page required to store page frame mappings frame mappings

A logical address is represented by:A logical address is represented by:< process-ID, page-number, offset >< process-ID, page-number, offset >


Inverted Page Table DiagramInverted Page Table DiagramFig. 8.20, p.270

CPU

logicaladdress

physicaladdress

physicalmemory

pid d

i d

i

pid p

p

search

inverted page table


DrawbacksDrawbacks

Slow linear search time over the inverted Slow linear search time over the inverted page tablepage table– use hashinguse hashing– use TLBs for recent accessesuse TLBs for recent accesses

Still need (something like) ordinary page Still need (something like) ordinary page tables to record which pages are currently tables to record which pages are currently swapped out to backing store.swapped out to backing store.


5.9. Shared Pages5.9. Shared Pages

Ordinary page tables allow frames to be Ordinary page tables allow frames to be sharedshared– useful for reusing useful for reusing reentrant codereentrant code

(i.e. code that does not modify itself)(i.e. code that does not modify itself)

ExampleExample– three users of an editor (150K, split into three three users of an editor (150K, split into three

pages) and their data (50K each, one page each)pages) and their data (50K each, one page each)


Editor UsageEditor Usage Fig. 8.21, p.271

data 1memory

data 3ed 1ed 2

ed 3data 2

::

012345678910

ed 1ed 2ed 3

data 1

3461

P1pagetable

ed 1ed 2ed 3

data 3

3462

P3pagetable

ed 1ed 2ed 3

data 2

3467

P2pagetable


Memory SavingsMemory Savings

Total physical memory usage Total physical memory usage ((withwith sharing): sharing):

= 150 + (3 * 50)= 150 + (3 * 50) = 300K= 300K

Total physical memory usage Total physical memory usage ((withoutwithout sharing): sharing):

= 3 * (150 + 50)= 3 * (150 + 50) = 600K= 600K


ProblemsProblems

Sharing relies on being able to map several Sharing relies on being able to map several pages (logical memory) to a single frame pages (logical memory) to a single frame (physical memory).(physical memory).– not possible with an inverted page table which not possible with an inverted page table which

only allows one page to be associated with one only allows one page to be associated with one frameframe


6. Segmentation6. Segmentation

A user’s view of memory:A user’s view of memory:

Fig. 8.22, p.272

subroutine stack

symboltablemain

program

sqrt()

continued


A logical address consists of:A logical address consists of:< segment-number, offset >< segment-number, offset >

A compiler can create separate segements A compiler can create separate segements for the distinct parts of a program:for the distinct parts of a program:– e.g. global variables, call stack, e.g. global variables, call stack,

code for each function code for each function


Segmentation HardwareSegmentation HardwareFig. 8.23, p.274

CPUphysicalmemoryd

s

limit base

s

segment table

< +yes

no

trap: addressing error


ExampleExample Fig. 8.24, p.275

subroutine stack

symboltable

mainprogram

sqrt()

S0 S3

S1

S2S4

limit base0 1000 14001 400 63002 400 43003 1100 32004 1000 4700

S0

S3

S2

S4

S1logical address space

segment table

1400

2400

3200

4300

4700

5700

6300

6700physical memory


AdvantagesAdvantages

Segments can be used to store distinct parts Segments can be used to store distinct parts of a program, so it is easier to protect themof a program, so it is easier to protect them– e.g. make function code read-onlye.g. make function code read-only


Sharing of SegmentsSharing of Segments Fig. 8.25, p.277

editor data 1

S0 S1

limit base0 25286 430621 4425 68348

editor

data 1

data 2

logical memory for P1

segment table for P1 43062

68348

72773

90003

98553

editor data 2

S0 S1

limit base0 25286 430621 8850 90003

logical memory for P2

segment table for P2

oses: 8. mem. mgmt. 1 operating systems v objectives –describe some of the memory management...

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